Patent Application
20160099204
1. Field of the Invention
The present invention relates to package substrates, and, more particularly, to a package substrate having a high yield rate and a method of fabricating the same.
2. Description of Related Art
With the advancement in electronic industry, the demand for electronic products with light weight, low-profile and high functionality is increasing. Flip-chip technology is thus developed in order to meet the requirements for high integration, miniaturization and high functionality.
As shown in FIGS. 1 and 1′, a package structure 1 of a conventional flip-chip type comprises a substrate 10 having a plurality of conductive traces 11 and a plurality of conductive pads 13, a chip 16 disposed on the conductive pads 13 via a plurality of conductive bumps 15, and an encapsulant 17 that encapsulates the chip 16. The height d of the conductive pads 13 is equal to the height d of the conductive traces 11.
Due to the ever decreasing size of the package structure and the popular trend of miniaturization, the pitch between the contact points has become smaller For instance, the width of the conductive pads 13 is less than 75 um, and the width and pitch of the conductive traces 11 are 15 um.
However, in the conventional package structure 1, as the height d of the conductive pads 13 is equal to the height d of the conductive traces 11, that is, the path L from the top surface of the conductive pads 13 to the top surfaces of the conductive traces 11 appears to be a horizontal path of 15 μm, it is highly likely that the conductive bumps 15 make contact with the conductive traces 11 besides the conductive pads 13, resulting in short circuit and low yield.
Thus, there is an urgent need for providing the aforementioned problems in the prior art.
In view of the aforementioned drawbacks, the present invention provides a package structure, comprising: a package substrate, comprising: a board having a plurality of conductive traces; a plurality of conductive pads formed on the board and each having a height greater than a height of each of the conductive traces; and an electronic component disposed on and electrically connected to the conductive pads via a plurality of conductive elements, wherein at least one of the conductive traces is positioned in proximity of at least one of the conductive pads.
The present invention further provides a method of fabricating a package structure, comprising: forming a plurality of conductive pads on a board that has a plurality of conductive traces, wherein each of the conductive pads has a height greater than a height of each of the conductive traces, and at least one of the conductive traces is positioned in proximity of at least one of the conductive pads; and disposing an electronic component on the conductive pads, and electrically connecting the electronic component to the conductive pads via a plurality of conductive elements.
In an embodiment, the surface of each of the conductive traces is flush with or lower than the surface of the board.
In an embodiment, the surface of each of the conductive traces is exposed from the surface of the board.
In an embodiment, the conductive pads are formed on the conductive traces. For instance, more than one of the conductive pads are formed on one of the conductive traces.
In an embodiment, the method further comprises forming an insulating protection layer on the board, with the conductive pads exposed from the insulating protection layer.
In an embodiment, the method further comprises forming on the board an encapsulating layer that encapsulates the electronic component.
In summary, the package structure and the fabricating method thereof according to the present invention are characterized by making the height of each of the conductive pads to be greater than the height of each of the conductive traces, such that when the electronic component is disposed on each of the conductive pads, the conductive elements are prevented from making contact with the conductive traces, thereby preventing short circuit from occurrence.
FIG. 1′ is a partial, enlarged view of
The present invention is described in the following with specific embodiments, so that one skilled in the pertinent art can easily understand other advantages and effects of the present invention from the disclosure of the present invention.
It should be noted that all the drawings are not intended to limit the present invention. Various modification and variations can be made without departing from the spirit of the present invention. Further, terms, such as “on”, “first”, “second”, and “one” etc., are merely for illustrative purpose and should not be construed to limit the scope of the present invention.
As shown in
In an embodiment, the contact point areas 220 are terminals of the second conductive traces 22.
As shown in
In an embodiment, the conductive pads 23 are fabricated by deposition or electroplating.
Further, the first conductive trace 21 is formed between the conductive pads 23.
In an embodiment, the surfaces 21a of first conductive traces 21 and the surfaces of the second conductive traces 22 are flush with the surface 20a of the board 20. Alternatively, as shown in FIG. 2B′, through an etching process, the surfaces 21a′ of the first conductive traces 21′ and the surfaces of the second conductive traces 22 are lower than the surface 20a of the board 20, for example, about 0-10 μm lower than the surface 20a of the board 20.
As shown in FIG. 2C-2C″, an insulating protection layer 24 such as a solder mask layer is formed on the board 20, with the conductive pads 23 and a portion of the first and second conductive traces 21 and 22 exposed from the insulating protection layer 24 (as shown in
In the subsequent process, as shown in
In an embodiment, the electronic component 26 is a passive component, an active component, or a combination of thereof, the active component can be a semiconductor chip, and the passive component can be a resistor, capacitor and inductor for instance.
In another embodiment, as shown in FIG. 3′, the second conductive traces 22′ are formed higher, and each has a height greater than the height of each of the first conductive traces 21, and a portion of each of the second conductive traces 22′ serves as a conductive pad 23.
In an embodiment, as the height h of each of the conductive pads 23 is greater than the height t of each of the first conductive traces 21, the path from the surface 23a (i.e. top surface) of the conductive pad 23 to the surface 21a of the first conductive trace 21 is a diagonal line S, as shown in FIG. 3″. As compared to the conventional horizontal line L, the diagonal line S has the length of about 31.5 nm, which is greater than the length 15 nm of the horizontal line L. Thus, when the electronic component 26 is disposed on the conductive pads 23, the conductive elements 25 would not make contact with the first conductive traces 21, thereby preventing the conductive pads 23 and the first conductive traces 21 from being shorted.
As shown in
As shown in
The present invention further provides a package structure 3, comprising: a package substrate 2, 2′, 2″, an electronic component 26 disposed on the package substrate 2, 2′, 2″, and an encapsulating layer 27 that encapsulates the electronic component 26.
The package substrate 2, 2′, 2″ comprises: a board 20, a plurality of first conductive traces 21, 21′ and a plurality of conductive pads 23 formed on the board 20, the conductive pads 23, each having a height t greater than the height t of each of the first conductive traces 21, 21′, and at least one of the conductive traces 21, 21′ is positioned in proximity of at least one of the conductive pads 23. The surfaces 21a and 21a′ of the first conductive traces 21 and 21′ are flush with or lower than the surface 20a of the board 20, and the surfaces 21a and 21a′ of the first conductive traces 21 and 21′ are exposed from the surface 20a of the board 20.
The electronic component 26 is disposed on and electrically connected to the conductive pads 23 via a plurality of conductive elements 25.
In an embodiment, the conductive pads 23 are formed on the contact point area 220 of the second conductive traces 22. For instance, more than one of the conductive pads 23 are formed on one of the second conductive traces 52.
In an embodiment, the package substrate 2, 2′, 2″ further comprises an insulating protection layer 24 formed on the board 20, with the conductive pads 23 exposed from the insulating protection layer 24.
In summary, the package structure and the method of fabricating the same according to the present invention are characterized by providing conductive pads formed on the package substrate to increase or reduce the height of the first conductive traces at the vicinity of the conductive traces, such that when the electronic components are disposed on the conductive pads, the conductive elements is prohibited to make contact with the first conductive traces, thereby solving the problem of short circuit resulted from bridging.
The present invention has been described using exemplary preferred embodiments. However, it is to be understood that the scope of the present invention is not limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and similar arrangements. The scope of the claims, therefore, should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.
| Number | Date | Country | Kind |
|---|---|---|---|
| 103134528 | Oct 2014 | TW | national |
