Patent Application
20240355777
This application claims priority to Korean Patent Application No. 10-2023-0051102, filed Apr. 19, 2023, the disclosure of which is hereby incorporated herein by reference.
The present inventive concept relates to packaged integrated circuit devices.
Recently, semiconductor packages mounted in electronic devices have been required to have high performance and high capacity. Accordingly, a semiconductor package including a plurality of semiconductor chips and a control chip controlling operations of the semiconductor chips, has been developed.
The present inventive concept provides a semiconductor package capable of efficiently improving performance relative to a unit size and ensuring durability and/or reliability.
According to an aspect of the present inventive concept, there is provided a semiconductor package including: a substrate, a first semiconductor chip disposed on an upper surface of the substrate, bumps disposed between and connected to the substrate and the first semiconductor chip, a non-conductive film layer having at least a portion disposed between the bumps, a second semiconductor chip disposed on the upper surface of the substrate, and wires connecting between the second semiconductor chip and the upper surface of the substrate. The upper surface of the substrate may have a dam protruding between a region overlapping the second semiconductor chip (or a region connected to the wires) and a region overlapping the first semiconductor chip, and a trench recessed alongside at least a portion of the dam.
According to another aspect of the present inventive concept, there is provided a semiconductor package including: a substrate, a first semiconductor chip disposed on an upper surface of the substrate, bumps disposed between and connected to the substrate and the first semiconductor chip, a non-conductive film layer having at least a portion disposed between the bumps, second semiconductor chips disposed on the upper surface of the substrate, and wires connecting one of the second semiconductor chips and the upper surface of the substrate. The upper surface of the substrate may have a dam protruding between a region overlapping the other one of the second semiconductor chips and a region overlapping the first semiconductor chip and protruding between a region connected to the wires and the region overlapping the first semiconductor chip, and a trench recessed alongside at least a portion of the dam.
According to another aspect of the present inventive concept, there is provided a semiconductor package including: a substrate, first and second semiconductor chips disposed on an upper surface of the substrate, bumps disposed between and connected to the substrate and the first semiconductor chip, and a non-conductive film layer having at least a portion disposed between the bumps. The upper surface of the substrate may have a dam protruding and having a shape extending to surround a region overlapping the first semiconductor chip, and a trench recessed and having a shape extending partially alongside portion of the dam.
The above and other aspects, features, and advantages of the present inventive concept will be more clearly understood from the following detailed description, taken in conjunction with the accompanying drawings, in which:
Detailed description of the present inventive concept to be set forth below refers to the accompanying drawings which, by way of example, illustrate specific example embodiments in which the present inventive concept may be practiced. The example embodiments are described in sufficient detail to enable one skilled in the art to practice the present inventive concept. It should be understood that the various example embodiments of the present inventive concept are different from each other but are not necessarily mutually exclusive. For example, one example embodiment of specific shapes, structures, and characteristics described herein may be implemented in another example embodiment without departing from the spirit and scope of the present inventive concept. Additionally, it should be understood that the location or arrangement of individual components within each disclosed example embodiment may be changed without departing from the spirit and scope of the present inventive concept. Accordingly, the detailed description set forth below is not intended to be taken in a limiting sense, and the scope of the present inventive concept is limited only by the appended claims, with all equivalents as claimed by those claims. Like reference numbers in the drawings indicate the same or similar function throughout the various aspects.
Hereinafter, example embodiments of the present inventive concept will be described in detail with reference to the accompanying drawings, such that those skilled in the art could easily carry out the present inventive concept.
A cross-section I1-I1′ of
Referring to
The at least one insulating layer 111 may include an insulating material, and may include, for example, a thermosetting resin such as an epoxy resin or a thermoplastic resin such as polyimide. For example, the at least one insulating layer 111 may include a photosensitive insulating material such as photo imageable dielectric (PID) resin. Alternatively, the at least one insulating layer 111 may include a resin mixed with an inorganic filler, for example, an Ajinomoto build-up film (ABF). Alternatively, at least one insulating layer 111 may include prepreg, flame retardant (FR-4), or bismaleimide triazine (BT). The at least one insulating layer 111 may include the same or different materials. Depending on a material, a process, and the like of respective layers, a boundary therebetween may not be easily distinguished.
The substrate 110 may further include a solder resist layer SR disposed on an upper surface of the substrate 110. The insulating material that may be contained in the at least one insulating layer 111 may also be contained in the solder resist layer SR, and a type or composition (for example, an inorganic filler content, an organic filler content, and the like) of the insulating material contained in the solder resist layer SR may be different from that of the at least one insulating layer 111, and a material, such as a photosensitive insulating material or the like, which is advantageous for forming openings in which the bumps 138 are disposed may be included.
The first semiconductor chip 120 may be disposed on the upper surface of the substrate 110. For example, the first semiconductor chip 120 may include connection pads disposed on a lower surface of the first semiconductor chip 120, and may be electrically connected to the substrate 110 through the connection pads. For example, the connection pads may include a conductive material such as tungsten (W), aluminum (Al), copper (Cu), or the like, and may be pads of a bare chip, for example, aluminum (Al) pads. However, in some example embodiments, the connection pads may be pads of a packaged chip, for example, copper (Cu) pads.
For example, the first semiconductor chip 120 may include a body portion containing a semiconductor material such as silicon (Si), germanium (Ge), gallium arsenide (GaAs), or the like, and a device layer disposed on a lower portion of the body portion, the device layer including an integrated circuit (IC). The first semiconductor chip 120 may include a logic semiconductor chip and/or a memory semiconductor chip. The logic semiconductor chip may be a microprocessor, for example, a central processing unit (CPU), a graphics processing unit (GPU), a field programmable gate array (FPGA), an application processor (AP), a digital signal processor, a cryptographic processor, a controller, or an application specific integrated circuit (ASIC). The memory semiconductor chip may be a volatile memory such as dynamic random access memory (DRAM), static random access memory (SRAM), or the like or a nonvolatile memory such as flash memory or the like.
The bumps 138 may be disposed between and connected to the substrate 110 and the first semiconductor chip 120. The first semiconductor chip 120 may be mounted on the upper surface of the substrate 110 through the bumps 138 in a flip-chip bonding manner. Accordingly, the first semiconductor chip 120 may be electrically connected to the electrical connection paths of the substrate 110. A portion of each of the bumps 138 may be inserted into openings of the solder resist layer SR, and may be connected to at least one interconnection layer 112 exposed through the openings. Substrate bumps 118, connected to a lower surface of the substrate 110, may also be implemented in a similar manner to the bumps 138.
For example, the bumps 138 may have a ball or column shape, and may include solder containing tin (Sn) or an alloy (Sn—Ag—Cu) including tin (Sn). The bumps 138 may have a relatively low melting point as compared to other metal materials, such that the connection pads of the first semiconductor chip 120 may be connected and fixed to the substrate pads of the substrate 110 using a thermal compression bonding (TCB) process or a reflow process.
At least a portion of the non-conductive film layer 135 may be disposed between the bumps 138, and may surround the bumps 138. The non-conductive film layer 135 may improve reliability of the bumps 138 by making them more resistant to stress. For example, the non-conductive film layer 135 may be formed using an underfill process, such that the non-conductive film layer 135 may be referred to as an underfill layer, may include a non-conductive polymer, and may include a non-conductive paste (NCP). When the non-conductive film layer 135 is formed, the non-conductive film layer 135 may have fluidity, such that a portion of the non-conductive film layer 135 may flow in a horizontal direction. In order to ensure reliability of the bumps 138, an overflow prevention unit 130 may prevent the non-conductive film layer 135 from overflowing in the horizontal direction.
Referring to
The second semiconductor chips 141 and 142 may be connected to wire bonding pads 114P1 and 114P2 on the upper surface of the substrate 110 through second semiconductor chip pads 141P and 142P on upper surfaces of the second semiconductor chips 141 and 142. The second semiconductor chip pads 141P and 142P may be electrically connected to a device layer including integrated circuits of the second semiconductor chips 141 and 142, and the wire bonding pads 114P1 and 114P2 may be electrically connected to at least one interconnection layer 112 of the substrate 110. For example, the wires 141W and 142W may contain a metal material having high conductivity, such as gold (Au), aluminum (Al), or copper (Cu), and may have a melting point higher than those of the bumps 138, but the present inventive concept is not limited thereto. At least a portion of the wire bonding pads 114P1 and 114P2 may be disposed in a region 114 connected to the wires on the upper surface of the substrate 110.
Each of the second semiconductor chips 141 and 142 may include two or more stacked sub-semiconductor chips. The adhesive films 141L and 142L may attach the sub-semiconductor chips to each other. A lowermost adhesive film, among the adhesive films 141L and 142L, may attach, to each other, the second semiconductor chip 141 and the solder resist layer SR on the upper surface of the substrate 110, and may attach, to each other, the second semiconductor chip 142 and a spacer 150 (and adhesive film 150L).
For example, one of the second semiconductor chips 142 may be a NAND flash memory semiconductor chip, the other one 141 of the second semiconductor chips may be a DRAM memory semiconductor chip, and the first semiconductor chip 120 may be a control semiconductor chip controlling the semiconductor chips 141 and 142 and may be electrically connected to the second semiconductor chips 141 and 142 through the substrate 110. For example, the first semiconductor chip 120 may determine a data processing sequence of sub-semiconductor chips of each of the second semiconductor chips 141 and 142, may perform a control operation for preventing errors and defective sectors, may include a buffer circuit for controlling loading of the sub-semiconductor chips, and may perform a frequency boosting interface (FBI) operation.
An area of the upper surface of the substrate 110 may be limited. Thus, when at least one of the second semiconductor chips 141 and 142 and the first semiconductor chip 120 are disposed together on one substrate 110, a separation distance between at least one of the second semiconductor chips 141 and 142 or the wires 141W and 142W and the first semiconductor chip 120 may decrease.
As the separation distance decreases, a distance between the first semiconductor chip 120 and the overflow prevention unit 130 may also decrease. As the distance between the first semiconductor chip 120 and the overflow prevention unit 130 decreases, the overflow prevention unit 130 may be required to have higher performance to block the non-conductive film layer 135.
If the non-conductive film layer 135 excessively overflows into the other one 141 of the second semiconductor chips, the non-conductive film layer 135 may affect adhesion between the other one 141 of the second semiconductor chips and an adhesive film 141L, such that the risk of detachment of the other one 141 of the second semiconductor chips may increase, or connection of the wires 141W to the second semiconductor chip pads 141P and the wire bonding pads 114P1 may have lowered reliability. If the non-conductive film layer 135 excessively overflows into a region 114 connected to wires connected to one 142 of the second semiconductor chips, connection reliability between the wires 142W and the wire bonding pads 114P2 may be lowered.
The upper surface of the substrate 110 of the semiconductor package 100a according to an example embodiment of the present inventive concept may have a dam 131 protruding between a region overlapping the second semiconductor chip 141 and/or a region 114 connected to the wires 142W and a region overlapping the first semiconductor chip 120, and a trench 135 recessed alongside at least a portion of the dam 131. The dam 131 may block the flow of the non-conductive film layer 135 in a horizontal direction, and the trench 132 may trap any portion of the non-conductive film layer 135 that overflows. Moreover, because the performance of the overflow prevention unit 130 to block the non-conductive film layer 135 may depend on a sum of a thickness of the dam 131 and a depth of the trench 132, an optimized combination of the dam 131 and the trench 132 may efficiently improve the performance of the overflow prevention unit 130 to block the non-conductive film layer 135.
Accordingly, the performance of the overflow prevention unit 130 to block the non-conductive film layer 135 may be efficiently improved, such that arrangement stability of the second semiconductor chip 141 may be improved and connection stability of the wires 142W may be improved without a substantial increase in the area of the upper surface of the substrate 110. Accordingly, the semiconductor package 100a may have efficiently improved performance relative to a unit size thereof, and durability and reliability of the semiconductor package 100a may also be ensured.
As shown, the dam 131 may have a shape extending to surround a region overlapping the first semiconductor chip 120, and the trench 132 may have a shape extending partially alongside a portion of the dam 131. For example, when a direction in which the region overlapping the first semiconductor chip 120 and the region overlapping the second semiconductor chip 141 and/or the region 114 connected to the wires 142W oppose each other is a Y-direction, the trench 132 may be disposed only to cover a portion of the dam 131, opposing the region overlapping the first semiconductor chip 120 in the Y-direction, and may not be disposed to cover the other portion of the dam 131, opposing the region overlapping the first semiconductor chip 120 in an X-direction. Accordingly, a flow direction of the non-conductive film layer 135 may be more concentrated in the X-direction than in the Y-direction, thereby more effectively suppressing overflow of the non-conductive film layer 135 into the region overlapping the second semiconductor chip 141 and/or the region 114 connected to the wires 142W.
Spacers 151 and 152, which oppose the region overlapping the first semiconductor chip 120 in the X-direction, may be dummy silicon spacer chips, such that overflow of the non-conductive film layer 135 in the X-direction may not substantially affect durability and reliability of the semiconductor package 100a. Even when the spacers 151 and 152 are replaced with additional semiconductor chips, a separation distance between the additional semiconductor chips and the first semiconductor chip 120 may be greater than a distance between the first semiconductor chip 120 and the second semiconductor chip 141, and may be greater than a distance between the first semiconductor chip 120 and the wires 142W, such that the non-conductive film layer 135 may not substantially affect reliability of the additional semiconductor chips.
For example, one 142 of the second semiconductor chips may be disposed on an upper surface of the first semiconductor chip 120, and the first semiconductor chip 120 may be disposed on a portion of the one 142 of the second semiconductor chips and the substrate 110, and the other one 141 of the second semiconductor chips may be disposed between the other portion of the one 142 of the second semiconductor chips and the substrate 110. Accordingly, the first semiconductor chip 120 and the second semiconductor chips 141 and 142 may be compactly disposed on a limited area of the upper surface of the substrate 110. The spacers 150, 151, and 152 may be disposed in an empty space corresponding to a thickness difference between the first semiconductor chip 120 and the second semiconductor chips 141 and 142, and thus may support the one 142 of the second semiconductor chips and may be dummy silicon spacer chips.
Thus, as the first semiconductor chip 120 and the second semiconductor chips 141 and 142 are compactly disposed, a distance between the first semiconductor chip 120 and the second semiconductor chip 141 and a distance between the first semiconductor chip 120 and the wires 142W may further decrease, and the overflow prevention unit 130 may be required to have higher performance to block the non-conductive film layer 135. A combined structure of the dam 131 and the trench 132 may efficiently improve the performance of the overflow prevention unit 130 to block the non-conductive film layer 135, thereby ensuring durability and reliability of the semiconductor package 100a and further improving miniaturization efficiency of the semiconductor package 100a. Alternatively, an allowable maximum volume of each of the second semiconductor chips 141 and 142 may be increased, thereby further increasing the performance of the second semiconductor chips 141 and 142, and more efficiently improving the performance of the semiconductor package 100a relative to a size of the semiconductor package 100a.
The semiconductor package 100a according to an example embodiment may further include an encapsulant 160 encapsulating the first and second semiconductor chips 120, 141, and 142. The encapsulant 160 may fill an empty space on the upper surface of the substrate 110, may provide an upper surface and a side surface of the semiconductor package 100a, and may improve durability (for example, robustness against external impact) or reliability (internal warpage prevention performance) of the semiconductor package 100a.
For example, the encapsulant 160 may contain a molding material such as an epoxy molding compound (EMC), but the present inventive concept is not limited thereto, and may contain an insulating material that may have protective properties or high ductility similar to those of the molding material. For example, the insulating material may be a build-up film (for example, an ABF), a thermosetting resin such as an epoxy resin, or a thermoplastic resin such as polyimide, and may be an insulating material in which an inorganic filler and/or a glass fiber are appropriately added to the insulating material of the first insulating layer 111.
Referring to
For example, two 132b of at least four trenches 132 may be surrounded by the dam 131 and spaced apart from each other, and the other two 132a of the at least four trenches 132 may be spaced apart from each other without being surrounded by the dam 131. Accordingly, a flow direction of the non-conductive film layer 135 may be more concentrated in an X-direction than in a Y-direction, thereby more effectively suppressing overflow of the non-conductive film layer 135 into a region overlapping the second conductive chip 141 and/or a region 114 connected to the wires 142W.
Referring to
Referring to
For example, a length of extension in one direction (for example, the X-direction) of at least one of the trenches 132 may be greater than or equal to a length in the one direction (for example, the X-direction) of one of sub-semiconductor chips of the second semiconductor chip 141. For example, a difference between the length of extension in the one direction (for example, the X-direction) of at least one of the trenches 132 and a length of extension in the one direction (for example, the X-direction) of the dam 131 may be greater than a difference between the length of extension in the one direction (for example, the X-direction) of at least one of the trenches 132 and the length in the one direction (for example, the X-direction) of one of the sub semiconductor chips of the second semiconductor chip 141.
Referring to
Each of the slits may have a short length in one direction (for example, the X-direction) of, such that each of the slits may have little effect on the possibility that the non-conductive film layer 135 overflows into at least one of the trenches 132. For example, a length in the one direction (for example, the X-direction) of each of the slits may be 1% or more and 10% or less of a length of extension in the one direction (for example, the X-direction) of the dam 131, and a total length of the slits may be less than a total length of the trenches 132, but the present inventive concept is not limited thereto.
A solder resist layer SR may provide an upper surface of the substrate 110. The dam 131 may protrude from an upper surface of the solder resist layer SR. The trench 132 may have a shape in which the solder resist layer SR is recessed. An insulating material contained in the dam 131 may be the same as that of the solder resist layer SR, but the present inventive concept is not limited thereto.
A ratio of widths W11 and W12 and thicknesses T11 and T12 of the dam 131 may be within a range determined in consideration of material properties of the dam 131. Accordingly, when the thicknesses T11 and T12 of the dam 131 increase, the widths W11 and W12 of the dam 131 may also be widen. However, the widths W11 and W12 of the dam 131 may be further limited as a distance between a first semiconductor chip 120 and a second semiconductor chip 141 decreases or when a distance between the first semiconductor chip 120 and wires 142W decreases. Accordingly, the thicknesses T11 and T12 of the dam 131 may also be limited, and the performance of the dam 131 to prevent overflow of the non-conductive film layer 135 solely may also be limited. Here, at least one of the trenches 132 may effectively compensate for the limited performance of the dam 131.
A depth of the trench 132 may be equal to the thicknesses T21 and T22 of the solder resist layer SR. In order to extend the depth of the trench 132, the trench 132 may upwardly expose at least one insulating layer of the substrate 110. Accordingly, a volume of the trench 132 trapping the non-conductive film layer 135 may be increased, thereby further improving the performance of trapping the non-conductive film layer 135.
The encapsulant 160 or the non-conductive film layer 135 may be in direct contact with at least one insulating layer of the substrate 110 through the trench 132. The adhesion between the at least one insulating layer of the substrate 110 (for example, prepreg) and the encapsulant 160 may be stronger than the adhesion between the solder resist layer SR and the encapsulant 160, such that overall durability and reliability of the semiconductor packages 100b and 100c may be further improved.
Referring to
For example, the second semiconductor chip 143 may also have second semiconductor chip pads 143P, and the wires 143W may connect between the second semiconductor chip pads 143P and wire bonding pads 114P3. The first semiconductor chip 120 and the second semiconductor chips 141 and 143 may be electrically connected to each other through an interconnection of at least one interconnection layer of the substrate 110. A specific arrangement position of second semiconductor chip pads 141P and 142P on upper surfaces of sub-semiconductor chips of each of the second semiconductor chips 141 and 142 may vary depending on design.
According to example embodiments of the present inventive concept, a semiconductor package may efficiently improve performance relative to a unit size and ensure durability and/or reliability.
While example embodiments have been illustrated and described above, it will be apparent to those skilled in the art that modifications and variations could be made without departing from the scope of the present inventive concept as defined by the appended claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10-2023-0051102 | Apr 2023 | KR | national |
