BACKGROUND
System on integrated chips (SoICs) are known to be fabricated using hybrid die-to-die bonding processes. To achieve well bonding between the dice, pick and place processes require extreme precision to prevent misalignment between the dice. Therefore, when the pick and place processes are disturbed, the picked die must be scrapped because the picked die cannot be accurately realigned, resulting in decreased manufacturing yield.
BRIEF DESCRIPTION OF THE DRAWINGS
Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It should be noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
FIG. 1 illustrates a top view of an example of a pick and place apparatus according to some embodiments of the present disclosure.
FIG. 2 illustrates a cross-sectional view along line A-A of FIG. 1.
FIG. 3 illustrates a schematic view of an example of a semiconductor element according to some embodiments of the present disclosure.
FIG. 4 illustrates a cross-sectional view of one or more stages of an example of a pick and place method according to some embodiments of the present disclosure.
FIG. 5 illustrates an enlarged view of a region B of FIG. 4.
FIG. 6 illustrates a cross-sectional view of one or more stages of an example of a pick and place method according to some embodiments of the present disclosure.
FIG. 7 illustrates a cross-sectional view of one or more stages of an example of a pick and place method according to some embodiments of the present disclosure.
FIG. 8 illustrates a cross-sectional view of one or more stages of an example of a pick and place method according to some embodiments of the present disclosure.
FIG. 9 illustrates a cross-sectional view of one or more stages of an example of a pick and place method according to some embodiments of the present disclosure.
FIG. 10 illustrates a cross-sectional view of one or more stages of an example of a pick and place method according to some embodiments of the present disclosure.
FIG. 11 illustrates a cross-sectional view of one or more stages of an example of a pick and place method according to some embodiments of the present disclosure.
FIG. 12 illustrates a cross-sectional view of one or more stages of an example of a pick and place method according to some embodiments of the present disclosure.
FIG. 13 illustrates a cross-sectional view of one or more stages of an example of a pick and place method according to some embodiments of the present disclosure.
FIG. 14 illustrates a cross-sectional view of one or more stages of an example of a pick and place method according to some embodiments of the present disclosure.
FIG. 15 illustrates a cross-sectional view of one or more stages of an example of a pick and place method according to some embodiments of the present disclosure.
FIG. 16 illustrates a cross-sectional view of one or more stages of an example of a pick and place method according to some embodiments of the present disclosure.
FIG. 17 illustrates a cross-sectional view of one or more stages of an example of a pick and place method according to some embodiments of the present disclosure.
FIG. 18 illustrates a flow chart of a pick and place method according to some embodiments of the present disclosure.
DETAILED DESCRIPTION
The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of elements and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “over,” “upper,” “on” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
As used herein, although the terms such as “first,” “second” and “third” describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms may be only used to distinguish one element, component, region, layer or section from another. The terms such as “first,” “second” and “third” when used herein do not imply a sequence or order unless clearly indicated by the context.
Notwithstanding that the numerical ranges and parameters setting forth the broad scope of the disclosure are approximations, the numerical values set forth in the specific examples are reported as precisely as possible. Any numerical value, however, inherently contains certain errors necessarily resulting from the standard deviation found in the respective testing measurements. Also, as used herein, the terms “substantially,” “approximately” and “about” generally mean within a value or range that can be contemplated by people having ordinary skill in the art. Alternatively, the terms “substantially,” “approximately” and “about” mean within an acceptable standard error of the mean when considered by one of ordinary skill in the art. People having ordinary skill in the art can understand that the acceptable standard error may vary according to different technologies. Other than in the operating/working examples, or unless otherwise expressly specified, all of the numerical ranges, amounts, values and percentages such as those for quantities of materials, durations of times, temperatures, operating conditions, ratios of amounts, and the likes thereof disclosed herein should be understood as modified in all instances by the terms “substantially,” “approximately” or “about.” Accordingly, unless indicated to the contrary, the numerical parameters set forth in the present disclosure and attached claims are approximations that can vary as desired. At the very least, each numerical parameter should at least be construed in light of the number of reported significant digits and by applying ordinary rounding techniques. Ranges can be expressed herein as from one endpoint to another endpoint or between two endpoints. All ranges disclosed herein are inclusive of the endpoints, unless specified otherwise.
FIG. 1 through FIG. 12 illustrate a pick and place method according to some embodiments of the present disclosure. Referring to FIG. 1 through FIG. 3, at least one semiconductor element 8 and a pick and place apparatus 1 are provided. FIG. 1 illustrates top views of the semiconductor element 8 and the pick and place apparatus 1 according to some embodiments of the present disclosure. FIG. 2 illustrates a cross-sectional view along line A-A of FIG. 1. FIG. 3 illustrates a schematic view of a semiconductor element 8 according to some embodiments of the present disclosure. The at least one semiconductor element 8 can be, for example, semiconductor die or semiconductor chip. The pick and place apparatus 1 is configured to transfer the at least one semiconductor element 8.
In some embodiments, as shown in FIG. 3, the at least one semiconductor element 8 can include a substrate 81, a dielectric structure 82, at least one circuit layer 83, a plurality of inner vias 84, a first sealing structure 85, at least one bonding pad 86, a second sealing structure 87 and at least one conductive pad 88. The substrate 81 can be, for example, silicon substrate. The substrate 81 has a first surface 811 (e.g., a top surface) and a second surface 812 (e.g., a bottom surface) opposite to the first surface 811.
The dielectric structure 82 is located over the second surface 812 of the substrate 81. In some embodiments, as shown in FIG. 3, the dielectric structure 82 can include a plurality of dielectric layers 825. The dielectric layers 825 are stacked on one another.
The at least one circuit layer 83 is embedded in the dielectric structure 82 (including, for example, the plurality of dielectric layers 825). In some embodiments, the at least one circuit layer 83 can include a plurality of circuit layers 83. The plurality of circuit layers 83 can be longitudinally spaced apart from each other.
The inner vias 84 can be disposed between the plurality of circuit layers 83 for electrically connecting the plurality of circuit layers 83. In some embodiments, the inner vias 84 can extend through the dielectric layers 825. In some embodiments, the inner vias 84 can taper upward.
The first sealing structure 85 is embedded in the dielectric structure 82 (e.g., the plurality of dielectric layers 825). The first sealing structure 85 surrounds the at least one circuit layer 83 and the inner vias 84 to prevent the at least one circuit layer 83 and the inner vias 84 from being corroded by moisture.
The at least one bonding pad 86 is electrically connected to the at least one circuit layer 83 through one of the inner vias 84. In some embodiments, a bottom surface 861 of the at least one bonding pad 86 can be exposed from a bottom surface 821 of the dielectric structure 82.
The second sealing structure 87 is embedded in the dielectric structure 82 (e.g., the plurality of dielectric layers 825). The second sealing structure 87 surrounds the at least one bonding pad 86 to prevent the at least one bonding pad 86 from being corroded by moisture. In some embodiments, a bottom surface 871 of the second sealing structure 87 can be exposed from the bottom surface 821 of the dielectric structure 82.
The at least one conductive pad 88 can be disposed between the first sealing structure 85 and the second sealing structure 87 for connecting the first sealing structure 85 and the second sealing structure 87. In some embodiments, the at least one conductive pad 88 can be, for example, aluminum (Al) pad.
In some embodiments, as shown in FIG. 1 and FIG. 2, the pick and place apparatus 1 can include a source storage location 11, a destination storage location 12, a temporary storage device 3, a controller 14 and a suction device 15. The source storage location 11 can be, for example, frame type die source. The source storage location 11 is configured to store the at least one semiconductor element 8. That is, the at least one semiconductor element 8 can be disposed on the source storage location 11. The destination storage location 12 can be, for example, wafer, die on wafer, chip on wafer on substrate (CoWoS), die on glue film, interposer or substrate. The destination storage location 12 is configured to receive the at least one semiconductor element 8.
The temporary storage device 3 can be disposed at a side of the source storage location 11 and is configured to position the at least one semiconductor element 8 if required. In some embodiments, as shown in FIG. 2, the temporary storage device 3 can be disposed between the source storage location 11 and the destination storage location 12.
In some embodiments, the temporary storage device 3 can include a platform 31, at least one optical detector 32, an optical camera 33 and a moving stage 34. The platform 31 is configured to place the at least one semiconductor element 8 to be positioned. In order to prevent the at least one semiconductor element 8 from being damaged by the platform 31, the platform 31 can include a non-metal material. In some embodiments, the platform 31 can have a top surface 311 facing the at least one semiconductor element 8 and a bottom surface 312 opposite to the top surface 311.
The at least one optical detector 32 is disposed below the platform 31 and configured to detect the position of the at least one semiconductor element 8 on the platform 31. In some embodiments, the at least one optical detector 32 can also be referred to as “lower optical detector.” In some embodiments, the platform 31 can include a transparent material. Thus, a detecting light R1 (FIG. 9) of the at least one optical detector 32 can penetrate the platform 31 to arrive the at least one semiconductor element 8. In some embodiments, the at least one optical detector 32 can be, for example, infrared ray (IR) detector. In some embodiments, the at least one optical detector 32 can include a plurality, of optical detectors 32.
The optical camera 33 is disposed below the platform 31 and corresponds to the at least one semiconductor element 8. In some embodiments, the optical camera 33 can also be referred to as “lower optical camera.” The optical camera 33 is configured to capture an image of the at least one semiconductor element 8. The captured image can assist the at least one optical detector 32 to detect the position of the at least one semiconductor element 8. In some embodiments, an image light R2 (FIG. 9) of the optical camera 33 can penetrate the platform 31 to arrive the at least one semiconductor element 8 when the platform 31 includes the transparent material.
The moving stage 34 is located below the platform 31 and configured to move the platform 31 for adjusting a position of the at least one semiconductor element 8. In some embodiments, the moving stage 34 can move the platform 31 horizontally or rotate the platform 31. In some embodiments, the moving stage can include a transparent material. Thus, the detecting light R1 (FIG. 9) of the at least one optical detector 32 and the image light R2 (FIG. 9) of the optical camera 33 can penetrate the moving stage 34 to arrive the at least one semiconductor element 8.
In some embodiments, as shown in FIG. 1, the controller 14 is configured to output or send a signal S to the suction device 15 after detecting an event. In some embodiments, the signal can be, for example, reset signal, alarm signal, or failure signal. The event can be, for example, earthquake, software failure, hardware failure, or power outage.
The suction device 15 is configured to pick and place the at least one semiconductor element 8. In some embodiments, the suction device 15 can transfer the at least one semiconductor element 8 from the source storage location 11 to the destination storage location 12. In some embodiments, the suction device 15 can transfer the at least one semiconductor element 8 from the source storage location 11 to the temporary storage device 3. In some embodiments, the suction device 15 can transfer the at least one semiconductor element 8 from the temporary storage device 3 to the destination storage location 12.
Referring to FIG. 4 and FIG. 5, the at least one semiconductor element 8 is picked up from the source storage location 11 through the suction device 15. In some embodiments, as shown in FIG. 5, the suction device 15 can contact the substrate 81 (e.g., the first surface 811) of the at least one semiconductor element 8.
Referring to FIG. 6 through FIG. 8, the at least one semiconductor element 8 is transferred to the temporary storage device 3 through the suction device 15 according to the signal S sent by the controller 14 after detecting the event. The at least one semiconductor element 8 can be placed on the platform 31. In some embodiments, the transfer operation of the at least one semiconductor element 8 can be acted immediately after the suction device 15 received the signal S. In this stage, the suction device 15 does not need to be reset.
In some embodiments, as shown in FIG. 8, the substrate 81 is farther from the at least one optical detector 32 than the at least one circuit layer 83 is. Thus, the detecting light R1 (FIG. 9) of the at least one optical detector 32 and the image light R2 (FIG. 9) of the optical camera 33 cannot be blocked by the substrate 81. In some embodiments, the substrate 81 is also farther from the at least one optical detector 32 than the dielectric structure 82 is. In some embodiments, the substrate 81 is also farther from the at least one optical detector 32 than the inner via 84 is. In some embodiments, the substrate 81 is also farther from the at least one optical detector 32 than the first sealing structure 85 is. In some embodiments, the substrate 81 is also farther from the at least one optical detector 32 than the at least one bonding pad 86 is. In some embodiments, the substrate 81 is also farther from the at least one optical detector 32 than the second sealing structure 87 is. In some embodiments, the substrate 81 is also farther from the at least one optical detector 32 than the conductive pad 88 is. In some embodiments, the at least one bonding pad 86 and the second sealing structure 87 can be disposed adjacent to the platform 31. In some embodiments, as shown in FIG. 8, the at least one bonding pad 86 and the second sealing structure 87 can contact the platform 31 (e.g., the top surface 311). In some embodiments, the bottom surface 861 of the at least one bonding pad 86 and the bottom surface 871 of the second sealing structure 87 can be substantially coplanar with the top surface 311 of the platform 31.
Referring to FIG. 9 the at least one semiconductor element 8 is positioned through the temporary storage device 3. In some embodiments, the image of the at least one semiconductor element 8 can be captured from below the platform 31 through the image light R2 of the optical camera 33, and the position of the at least one semiconductor element 8 can be detected from below the platform 31 through the detecting light R1 of the at least one optical detector 32. According to the detected position of the at least one semiconductor element 8, the moving stage 34 can move or rotate the platform 31 to adjust the position of the at least one semiconductor element 8. Thus, the at least one semiconductor element 8 can be accurately realigned.
In some embodiments, a position of the suction device 15 can be adjusted according to the position of the at least one semiconductor element 8. That is, the position of the suction device 15 can be moved or rotated to match the position of the at least one semiconductor element 8, allowing for realignment. Thus, the moving stage 34 can be omitted.
Referring to FIG. 10 through FIG. 12, the positioned semiconductor element 8 is picked up from the temporary storage device 3 through the suction device 15. Then, the positioned semiconductor element 8 is placed on the destination storage location 12 through the suction device 15 to proceed subsequent processes.
The method of the present disclosure can be applied in hybrid die-to-die bonding processes; however, the disclosure is not limited thereto. As shown in the embodiments illustrated in FIG. 1 through FIG. 12, when the event (e.g., earthquake, software failure, hardware failure, or power outage) is detected, the at least one semiconductor element 8 on the suction device 15 can be transferred to the temporary storage device 3 for positioning and realignment. Thus, the at least one semiconductor element 8 on the suction device 15 does not need to be scrapped, resulting in increased manufacturing yield.
FIG. 13 illustrates a cross-sectional view of one or more stages of an example of a pick and place method according to some embodiments of the present disclosure. The stage illustrated in FIG. 13 is the same as, or similar to, the stage illustrated in FIG. 8, except for a structure of the platform 31a. In some embodiments, as shown in FIG. 13, the platform 31a can include a cavity 315 recessed from the top surface 311. An edge 80 of the at least one semiconductor element 8 can be misaligned with the cavity 315. That is, the at least one semiconductor element 8 contacts the platform 31a only through the edge 80 to prevent the at least one semiconductor element 8 from being damaged by the platform 31a. In some embodiments, the at least one bonding pad 86 and the second sealing structure 87 can be located above the cavity 315 to prevent the at least one bonding pad 86 and the second sealing structure 87 from being damaged by the platform 31a. In some embodiments, the at least one circuit layer 83 and the inner vias 84 can be located in an upward projection area of the cavity 315.
FIG. 14 illustrates a cross-sectional view of one or more stages of an example of a pick and place method according to some embodiments of the present disclosure. The stage illustrated in FIG. 14 is the same as, or similar to, the stage illustrated in FIG. 9, except for positions of the at least one optical detector 32a and the optical camera 33a of the temporary storage device 3a. In some embodiments, as shown in FIG. 14, the at least one optical detector 32a and the optical camera 33a are disposed above the platform 31. Thus, the at least one optical detector 32a can also be referred to as “upper optical detector.” The optical camera 33a can also be referred to as “upper optical camera.” In some embodiments, the image of the at least one semiconductor element 8 can be captured from above the platform 31 through the image light R2a of the optical camera 33a, and the position of the at least one semiconductor element 8 can be detected from above the platform 31 through the detecting light R1a of the at least one optical detector 32a.
In some embodiments, as shown in FIG. 14, the substrate 81 can contact the platform 31. That is, the substrate 81 is farther from the at least one optical detector 32a than the at least one circuit layer 83 is. Thus, the detecting light R1a of the at least one optical detector 32a and the image light of the optical camera 33a cannot be blocked by the substrate 81. In some embodiments, the substrate 81 is more adjacent to the platform 31 than the dielectric structure 82 is. In some embodiments, the substrate 81 is more adjacent to the platform 31 than the inner via 84 is. In some embodiments, the substrate 81 is more adjacent to the platform 31 than the first sealing structure 85 is. In some embodiments, the substrate 81 is more adjacent to the platform 31 than the at least one bonding pad 86 is. In some embodiments, the substrate 81 is more adjacent to the platform 31 than the second sealing structure 87 is. In some embodiments, the substrate 81 is more adjacent to the platform 31 than the conductive pad 88 is.
FIG. 15 illustrates a cross-sectional view of one or more stages of an example of a pick and place method according to some embodiments of the present disclosure. The stage illustrated in FIG. 15 is the same as, or similar to, the stage illustrated in 9, except that the temporary storage device 3b further includes at least one upper optical detector 32b and an upper optical camera 33b. In some embodiments, as shown in FIG. 15, the at least one upper optical detector 32b and the upper optical camera 33b are disposed above the platform 31. In some embodiments, the image of the at least one semiconductor element 8 can be captured from above the platform 31 through the image light R2b of the upper optical camera 33b, and the position of the at least one semiconductor element 8 can be detected from above the platform 31 through the detecting light R1b of the at least one upper optical detector 32b. The optical detector 32 and the optical camera 33 of FIG. 15 can be the same as the optical detector 32 and the optical camera 33 of FIG. 9. Thus, the image of the at least one semiconductor element 8 can also be captured from below the platform 31 through the image light R2 of the optical camera 33, and the position of the at least one semiconductor element 8 can also be detected from below the platform 31 through the detecting light R1 of the optical detector 32.
To ensure the detecting light R1b of the at least one upper optical detector 32b and the image light R2b of the upper optical camera 33b can penetrate the substrate 81, the at least one upper optical detector 32b can be, for example, infrared ray (IR) detector. The upper optical camera 33b can be, for example, infrared ray (IR) camera.
FIG. 16 illustrates a cross-sectional view of one or more stages of an example of a pick and place method according to some embodiments of the present disclosure. The stage illustrated in FIG. 16 is the same as, or similar to, the stage illustrated in FIG. 1, except for a configuration of the temporary storage device 3c of the pick and place apparatus 1c. In some embodiments, as shown in FIG. 16, the top surface 311 of the platform 31c can have a plurality of areas 313 configured to place a plurality of semiconductor elements S. The plurality of areas 313 can be spaced apart from each other. In some embodiments, the plurality of areas 313 can have the same size to place the plurality of semiconductor elements 8 of the same size. In some embodiments, the plurality of areas 313 can have different sizes to place the plurality of semiconductor elements 8 of the different sizes.
FIG. 17 illustrates a cross-sectional view of one or more stages of an example of a pick and place method according to some embodiments of the present disclosure. The stage illustrated in FIG. 17 is the same as, or similar to, the stage illustrated in FIG. 1, except for an amount of the temporary storage device 3d of the pick and place apparatus 1d. In some embodiments, as shown in FIG. 17, the pick and place apparatus 1d can include a plurality of temporary storage devices 3d configured to position a plurality of semiconductor elements 8. The plurality of temporary storage devices 3d can be spaced apart from each other. In some embodiments, the plurality of temporary storage devices 3d of FIG. 17 can be the same as the temporary storage device 3 of FIG. 1.
FIG. 18 illustrates a flow chart of a pick and place method 90 according to some embodiments of the present disclosure.
In some embodiments, the pick and place method 90 can include a step S91, providing at least one semiconductor element disposed on a source storage location. For example, as shown in FIG. 1 and FIG. 2, the at least one semiconductor element 9 is provided. The at least one semiconductor element 9 is disposed on the source storage location 11.
In some embodiments, the pick and place method 90 can include a step S92, picking up the at least one semiconductor element from the source storage location. For example, as shown in FIG. 4 and FIG. 5, the at least one semiconductor element 8 is picked up from the source storage location 11.
In some embodiments, the pick and place method 90 can include a step S93, transferring the at least one semiconductor element to a temporary storage device according to a signal. For example, as shown in FIG. 6 through FIG. 8, the at least one semiconductor element 8 is transferred to the temporary storage device 3 according to the signal S.
In some embodiments, the pick and place method 90 can include a step S94, positioning the at least one semiconductor element through the temporary storage device. For example, as shown in FIG. 9, the at least one semiconductor element 8 is positioned through the temporary storage device 3.
In some embodiments; the pick and place method 90 can include a step S95, picking up the positioned semiconductor element from the temporary storage device and placing the positioned semiconductor element on a destination storage location. For example, as shown in FIG. 10 through FIG. 12, the positioned semiconductor element 8 is picked up from the temporary storage device 3. Then, the positioned semiconductor element 8 is placed on the destination storage location 12.
In accordance with some embodiments of the present disclosure, a pick and place method includes: providing at least one semiconductor element disposed on a source storage location; picking up the at least one semiconductor element from the source storage location; transferring the at least one semiconductor element to a temporary storage device according to a signal; positioning the at least one semiconductor element through the temporary storage device; and picking up the positioned semiconductor element from the temporary storage device and placing the positioned semiconductor element on a destination storage location. The signal is sent by a controller after detecting an event.
In accordance with some embodiments of the present disclosure, a pick and place method includes: picking up at least one semiconductor element through a suction device; sending a signal to the suction device after detecting an event; and placing the at least one semiconductor element on a temporary storage device according to the signal.
In accordance with some embodiments of the present disclosure, a pick and place apparatus includes a source storage location, a destination storage location, a temporary storage device; a controller and a suction device. The source storage location is configured to store at least one semiconductor element. The destination storage location is configured to receive the at least one semiconductor element. The temporary storage device is disposed at a side of the source storage location and configured to position the at least one semiconductor element. The controller is configured to send a signal after detecting an event. The suction device is configured to pick and place the at least one semiconductor element and transfers the at least one semiconductor element to the temporary storage device according to the signal sent by the controller. The temporary storage device includes a platform and at least one optical detector. The platform is configured to place the at least one semiconductor element. The at least one optical detector is configured to position the at least one semiconductor element. The at least one semiconductor element includes a substrate, a dielectric structure located over a surface of the substrate and at least one circuit layer embedded in the dielectric structure. The substrate is farther from the at least one optical detector than the at least one circuit layer is. The at least one optical detector is disposed below the platform. The platform has a surface facing the at least one semiconductor element and includes a cavity recessed from the surface. An edge of the at least one semiconductor element is misaligned with the cavity. The temporary storage device further includes an optical camera disposed below the platform. The optical camera is configured to capture an image of the at least one semiconductor element. The temporary storage device further includes a moving stage located below the platform. The moving stage is configured to move the platform for adjusting a position of the at least one semiconductor element.
The foregoing outlines features of several embodiments so that those skilled in the art may better understand aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.
Patent Application
20230025157
