Patent Application
20110221053
The present disclosure generally relates to integrated circuits. More specifically, the present disclosure relates to packaging integrated circuits.
Semiconductor dies include collections of transistors and other components in an active layer of a substrate. Commonly, these substrates are semiconductor materials, and, in particular, silicon. Additionally, these substrates are conventionally thicker than necessary to obtain desirable device behavior. The semiconductor dies are singulated or diced from a semiconductor wafer.
Mold placed on the wafers have different stresses than the wafer resulting in unbalanced stress. As a result, the wafer may warp or bend to reach an equilibrium stress. Thick wafers are able to counterbalance the stress imposed by the mold better than thin wafers. Additionally, thick wafers have the robustness to withstand the dozens of processes, high temperatures, and transfers between tools or even fabrication sites.
However, thin wafers are employed, for example, in stacked ICs. Stacked ICs increase device functionality and decrease die size by stacking dies vertically. Similar to high-rise towers that fit more office space in a smaller land area, stacked ICs offer more space for transistors and other components while occupying the same area. Thin wafers are employed in stacked ICs to reduce the form factor of the stacked IC and to reduce the aspect ratio of some manufacturing processes. For example, etching of through vias is an aspect ratio limited process, which limits the thickness of the wafer. When handling a thin wafer a thicker carrier wafer is attached to provide mechanical support.
Manufacturing a stacked IC includes attaching a first tier wafer to a carrier wafer for support before thinning the first tier wafer. After thinning, second tier dies are placed on the first tier wafer, a mold compound is placed on the first tier wafer and second tier dies, and the first tier wafer is released from the carrier wafer. Once released from the carrier wafer, the first tier wafer may have an unbalanced stress between the wafer and the mold compound of the first tier wafer resulting in wafer warpage. The stress imbalance is due, in part, to thinning the first tier wafer such that the first tier wafer no longer provides sufficient support for the mold compound. That is, without support the first tier wafer is unable to resist the mechanical stress due to the mold compound.
A conventional group of stacked integrated circuits before carrier wafer release is illustrated in
The stacked IC group 100 after release from the carrier wafer 102 is shown in
Conventional methods for reducing wafer warpage include selecting a mold compound having a coefficient of thermal expansion similar to the first tier wafer. However, these method have not significantly reduced wafer warpage.
Thus, there is a need for reduce wafer warpage during packaging processes.
According to one aspect of the disclosure, a method for packaging a stacked integrated circuit includes attaching a carrier wafer to a first tier wafer. The method also includes coupling second tier dies to the first tier wafer to form a group of stacked integrated circuits after attaching the carrier wafer to the first tier wafer. The method further includes applying a mold compound to the second tier dies coupled to the first tier wafer after coupling the second tier dies to the first tier wafer. The method also includes pre-processing the group of stacked integrated circuits. The method further includes releasing the first tier wafer from the carrier wafer after pre-processing the group of stacked integrated circuits.
According to another aspect of the disclosure, an integrated circuit includes first tier dies stacked on a carrier wafer. The first tier dies are at least partially separated. The integrated circuit also includes second tier dies stacked on the first tier dies. The integrated circuit further includes a mold compound surrounding the first tier dies and surrounding the second tier dies. The mold compound fills spaces between the first tier dies.
According to a further aspect of the disclosure, a method for packaging a stacked integrated circuit includes the step of attaching a carrier wafer to a first tier wafer. The method also includes the step of coupling second tier dies to the first tier wafer to form a group of stacked integrated circuits after attaching the carrier wafer to the first tier wafer. The method further includes the step of pre-processing the group of stacked integrated circuits. The method also includes the step of releasing the first tier wafer from the carrier wafer after pre-processing the group of stacked integrated circuits.
According to another aspect of the disclosure, a stacked integrated circuit is manufactured by a process including attaching a carrier wafer to a first tier wafer. The process also includes coupling second tier dies to the first tier wafer to form a group of stacked integrated circuits, after attaching the carrier wafer to the first tier wafer. The process further includes pre-processing the group of stacked integrated circuits. The process also includes releasing the first tier wafer from the carrier wafer after pre-processing the group of stacked integrated circuits.
According to a further aspect of the disclosure, an integrated circuit includes a first tier wafer stacked on a carrier wafer. The first tier wafer includes means for separating the first tier wafer into first tier dies. The integrated circuit also includes second tier dies stacked on the first tier wafer. The first tier wafer further includes a mold compound surrounding the first tier dies and surrounding the second tier dies. The mold compound fills the separating means.
The foregoing has outlined rather broadly the features and technical advantages of the present disclosure in order that the detailed description that follows may be better understood. Additional features and advantages will be described hereinafter which form the subject of the claims of the disclosure. It should be appreciated by those skilled in the art that the conception and specific embodiments disclosed may be readily utilized as a basis for modifying or designing other structures for carrying out the same purposes of the present disclosure. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the technology of the disclosure as set forth in the appended claims. The novel features which are believed to be characteristic of the disclosure, both as to its organization and method of operation, together with further objects and advantages will be better understood from the following description when considered in connection with the accompanying figures. It is to be expressly understood, however, that each of the figures is provided for the purpose of illustration and description only and is not intended as a definition of the limits of the present disclosure.
For a more complete understanding of the present disclosure, reference is now made to the following description taken in conjunction with the accompanying drawings.
One technique for reducing warpage while manufacturing stacked ICs during packaging is pre-processing the first tier wafer before carrier wafer release. Pre-processing the portions of the stacked IC before release of the carrier wafer allows the first tier wafers to expand or contract to alleviate stresses in the stacked IC. Additionally, pre-processing aids dicing into individual stacked ICs. According to one embodiment, pre-processing of the first tier wafer includes dicing into separate dies. With the first tier wafer already diced, dicing into individual stacked ICs involves cutting through only the mold compound. According to another embodiment, pre-processing includes partially dicing the first tier wafer to balance stress and reduce wafer warpage. In a further embodiment, pre-processing includes partially dicing the mold compound. In yet another embodiment, pre-processing includes a wafer-level etch of the first tier wafer. Where pre-processing includes a wafer-level etch of the first tier wafer, this technique of reducing warpage may be combined with either one of the previously mentioned techniques for reducing warpage.
According to one embodiment, the first tier dies 210 are diced from a first tier wafer before attachment of the second tier dies 220. Subsequently, application of the mold compound 230 fills in space between the first tier dies 210. After detachment from the carrier wafer 202, the space between the first tier dies 210 allows expansion or contraction of the first tier dies 210 to accommodate stresses in the stacked ICs.
Turning to
At block 305 a first tier wafer is mounted on a carrier wafer.
At block 310 backside processing of the first tier wafer is performed. Backside processing may include, for example, thinning, recess etching, microbumping, materials deposition, through via formation, redistribution layer formation, patterning, and passivation.
At block 312 it is determined whether wafer level pre-processing will be performed. Wafer-level pre-processing reduces warpage by creating a discontinuity in the first tier wafer 410 to allow the first tier dies to expand or contract to alleviate stresses. If wafer level pre-processing is to be performed, lines are etched in the first tier wafer at block 314 and the process continues to block 315. The lines may, for example, match the dicing pattern used during later back-end assembly. The lines may be patterned according to known processes, such as, depositing a photoresist, patterning the photoresist, and etching the first tier wafer using the photoresist as a hard mask. As another example, a material may be deposited on the first tier wafer before deposition of the photoresist and act as a hard mask for patterning lines in the first tier wafer. The results of wafer level-pre-processing are not illustrated in
At block 315 second tier dies are placed on the first tier wafer. Second tier dies may include, for example, memory circuitry, logic circuitry, telecommunications circuitry, passive components, and active components.
At block 316 it is determined whether pre-processing will be performed. If pre-processing is not to be performed at this time (for example when wafer level pre-processing occurred at block 314), the process continues to block 325. If pre-processing is to be performed, the process continues to block 318 to decide if full dicing is to be performed. If full dicing is to be performed the process continues to block 320 to dice the first tier wafer into first tier dies.
If full dicing is not performed the process continues to block 322 to partially dice the first tier wafer. Partial dicing through a fraction of the first tier wafer may be performed with a laser or mechanical saw. The remaining thickness of the first tier wafer may be diced in subsequent processing such as during or after the back-end assembly. A partially diced first tier wafer is not illustrated in
Alternatively at blocks 320, 322, partial or full dicing may be performed with dry and/or wet etching in replacement of or in combination with other dicing methods such as, for example, laser dicing and diamond sawing. In one embodiment, the etching parameters may be varied during the etch to create a non-uniform wall that allows a mold compound (deposited later) to lock to the first tier dies 415. For example, etching parameters such as gas pressures, electrode voltages, and/or etch rate may alter the shape of the wall of the first tier dies 415.
At block 325 a wafer level mold is applied, which fills in between first tier dies.
At block 326 it is determined whether the mold compound 430 is to be pre-processed. If the mold compound 430 is not pre-processed, the process continues to block 330.
At block 330 the carrier wafer is released from the first tier dies. After carrier wafer release, the first tier wafer would warp to balance stresses with the mold compound. However, pre-processing assists in balancing stresses and reduces wafer warpage after release of the carrier wafer.
At block 335 the group of stacked ICs are diced/singulated, i.e. the mold compound is diced.
At block 340 back-end assembly is completed on the individual stacked ICs. For example, a pick-and-place process may be used for placing individual stacked ICs on packaging substrates.
Alternatively or in addition to pre-processing of the first tier wafer, the mold compound may be pre-diced before demount from the carrier wafer 402. In the flowchart of
Referring to
According to another embodiment, the pre-processing of the mold compound 430 is performed without pre-processing of the first tier dies 415. Referring to
After pre-processing the mold compound 430 at block 327, the process continues to block 330.
At block 330 the carrier wafer is released. Referring to
Processing on wafers with pre-processed mold compound as shown in
Pre-processing may be performed before and/or after placement of the tier two die. According to one embodiment, wafer-level pre-processing is performed to at least partially dice the first tier wafer before placement of tier two dies. According to another embodiment, pre-processing is performed after placement of the second tier die to at least partially dice the first tier wafer. According to yet another embodiment, pre-processing is performed after mold compound is applied to the first tier wafer and second tier dies to create openings in the mold compound. Any of the above mentioned embodiments may be combined.
Pre-processing a stacked IC during packaging processes before carrier wafer release reduces wafer warpage and improves wafer handling. The reduced wafer warpage increases reliability and increases assembly yield of the packaging process.
Additionally, in the embodiments completely dicing through the first tier wafer before molding, dicing of the ICs is separated into two dicing processes, each cutting through only a single material. Dicing of only one material improves reliability of the dicing process. Further, in some embodiments, pre-processing allows mold compound to encapsulate sides of the first tier dies for protection of the first tier die during subsequent processing.
In
Data recorded on the storage medium 704 may specify logic circuit configurations, pattern data for photolithography masks, or mask pattern data for serial write tools such as electron beam lithography. The data may further include logic verification data such as timing diagrams or net circuits associated with logic simulations. Providing data on the storage medium 704 facilitates the design of the circuit design 710 or the semiconductor component 712 by decreasing the number of processes for designing semiconductor wafers.
The methodologies described herein may be implemented by various components depending upon the application. For example, these methodologies may be implemented in hardware, firmware, software, or any combination thereof. For a hardware implementation, the processing units may be implemented within one or more application specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), processors, controllers, micro-controllers, microprocessors, electronic devices, other electronic units designed to perform the functions described herein, or a combination thereof.
For a firmware and/or software implementation, the methodologies may be implemented with modules (e.g., procedures, functions, and so
If implemented in firmware and/or software, the functions may be stored as one or more instructions or code on a computer-readable medium. Examples include computer-readable media encoded with a data structure and computer-readable media encoded with a computer program. Computer-readable media includes physical computer storage media. A storage medium may be any available medium that can be accessed by a computer. By way of example, and not limitation, such computer-readable media can comprise RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store desired program code in the form of instructions or data structures and that can be accessed by a computer; disk and disc, as used herein, includes compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk and blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media.
In addition to storage on computer readable medium, instructions and/or data may be provided as signals on transmission media included in a communication apparatus. For example, a communication apparatus may include a transceiver having signals indicative of instructions and data. The instructions and data are configured to cause one or more processors to implement the functions outlined in the claims.
Although the terminology “through silicon via” includes the word silicon, it is noted that through silicon vias are not necessarily constructed in silicon. Rather, the material can be any device substrate material.
Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the technology of the disclosure as defined by the appended claims. Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present disclosure. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.
