Patent Application
20250163606
The present invention relates to a production method for a single crystal semiconductor film, a production method for a multilayer film of a single crystal semiconductor film, and a semiconductor element.
In the production steps of semiconductors, one of the most important steps is an impurity doping step. A steep impurity profile and lowering the temperature of the steps have been demanded with the miniaturization of the element dimensions. As a means for impurity doping, techniques have been conventionally used, such as a thermal diffusion method, a chemical vapor deposition method (CVD method), and ion implantation followed by activation annealing.
In the CVD method, a substrate is usually heated to 600° C. or higher, and a raw material gas is decomposed on the substrate to form a film such as a Si layer. When the growth temperature is lower than 600° C., the decomposition efficiency of the source gas is reduced, the film-forming rate is significantly reduced, and hydrogen derived from the source gas remains in the film. On the other hand, when the growth temperature is raised, impurities are easily diffused, and the controllability of the impurity profile is low.
Non-patent Literature 1, for example, discloses a technique for growing a silicon (Si) crystal film doped with impurities by the CVD method using monosilane (SiH4), disilane (Si2H6), phosphine (PH3) or diborane (B2H6) as a source gas. It also describes that the growth temperature is 800 to 900° C. or higher.
In the ion implantation method, an appropriate mask can be provided on the substrate before implantation to restrict a region where impurities are implanted; however, the range thereof is a stochastic process of collision with a crystal lattice, and thus the impurity profile is the Gaussian distribution in principle. In addition, because the crystal is broken due to collision with the crystal lattice, crystal recovery annealing (activation annealing) generally at about 1000° C. is essential, which causes diffusion of impurities.
Non-Patent Literature 2, Non-patent Literature 3 and Non-patent Literature 4 disclose techniques on ion implantation and activation annealing. The temperature of activation annealing is 720 to 950° C. as an example, and in the activation annealing coupled with the ion implantation method, essentially a stochastic process, impurity diffusion is pointed out as a problem.
The thermal diffusion method is a thermal diffusion process, and thus the controllability of the impurity profile is low and the process temperature is also generally high, 800° C. or higher.
Another method for forming a semiconductor crystal film is a method for forming a film by sputtering (sputter epitaxy).
Patent Literature 1 (by the present inventor) discloses the sputter epitaxy method for forming a SiGe semiconductor thin film using Si and Ge targets. It describes that in order to form a doped semiconductor thin film, B, Al, Ga, In, N, P, Sb and the like as doping elements for the semiconductor may be contained in these targets, but does not disclose any specific growth conditions such as the growth temperature and the growth rate.
Patent Literature 2 (by the present inventors and others) describes that when a SiGe semiconductor layer is formed by the sputter epitaxy method, a dopant to provide conductivity for the laminated semiconductor film may be contained, and the growth temperature at this time is 350° C. or higher, but does not disclose any data to support that.
In the methods described in Non-patent Literatures 1 to 4, conventional doping methods include a high temperature step, 700° C. or higher, and cannot cope with lowering the temperature of steps, which is demanded in the production steps of semiconductors that have been increasingly miniaturized. In the method described in Non-patent Literature 4, impurity diffusion is unavoidable in the high temperature step, which makes it difficult to secure a steep impurity profile. Furthermore, in the ion implantation step itself, essentially a stochastic process, there has been a problem in that impurity distribution expands before thermal diffusion.
The present inventors obtained findings that by discharge sputtering of one or two or more of targets obtained by doping a group 14 element such as silicon (Si) with boron (B) as impurities in an inert gas atmosphere using a magnetron sputtering device, and by using a target with a predetermined plane orientation, a boron-doped single crystal semiconductor film having a sufficient impurity activation rate at a lower temperature than that in the conventional methods was obtained on the Si substrate.
One of the objects according to some aspects of the present invention is to provide, in the production of an impurity-containing group 14 single crystal semiconductor film, a production method for a single crystal semiconductor film having a sufficient activation rate at a much lower temperature than that in the conventional methods and having a steep impurity profile, and a semiconductor device produced by the method.
The present invention is a production method for a single crystal semiconductor film by means of crystal growth using a magnetron sputtering device to which an impurity-doped group 14 semiconductor target is attached, wherein the film-forming temperature is 300° C. or higher, and the growth rate is 10 nm or less per minute.
According to the production method of the present invention, it is possible to provide an impurity-containing group 14 semiconductor single crystal film having a sufficient activation rate at a low temperature.
An embodiment of the present invention will now be illustrated as examples in detail using the drawings. It should be noted, however, that constituent elements described in this embodiment are shown as examples, and the scope of this invention is not limited only to those. In addition, all combinations of features illustrated in the embodiment are not essential for the solution of the invention.
First, the structure of the semiconductor crystal film growth apparatus according to the present embodiment will be illustrated with reference to a drawing.
The vacuum chamber 10 has an evacuation pump, not shown. The evacuation pump is desirably a contamination-free pump, for example, a turbomolecular pump, a sputter ion pump, a cryopump or a dry pump. The target 20 and target 21 are each any of a high purity group 14 element target or a group 15 element-doped group 14 element target or a boron-doped group 14 element target. The Si substrate 30 to grow a crystal is put on a place opposed to the target 20 and target 21. The target 20 and the target 21 can be put with the direction of the surface thereof inclined to the Si substrate 30. The mechanism to retain the inclined surfaces of the target 20 and the target 21 is achieved, for example, by a method for turning a flange to attach a target in the vacuum chamber 10 to a desired direction or an equivalent method.
The high-frequency power source 51 to apply a high-frequency voltage (e.g. a frequency of 13.56 MHz) is connected to the target 20 via the matching box 52, and the DC power source 50 to apply a DC voltage is connected to the target 21, respectively.
In the substrate mounting table with a heater 40, for example, the temperature of the substrate is measured by the radiation thermometer 60 provided outside the vacuum chamber, and the temperature is controlled so that the Si substrate 30 will have a predetermined temperature by control equipment (not shown).
This device is a magnetron sputtering device, in which magnets (not shown) are placed on the back of the target 20 and the target 21.
It should be noted that an embodiment having two targets is shown as an example in
When simultaneously sputtering two or more of the same element targets, the targets may be placed symmetrically to the straight line passing through the center of the substrate to improve the uniformity of a grown film.
The process for growing a semiconductor crystal film according to the embodiment of the present invention will now be illustrated with reference to
First, the vacuum chamber 10 is evacuated to a very high vacuum (about 10−10 Torr) in S21.
In the subsequent S22, the Si substrate 30 is introduced on the substrate mounting table with a heater 40. It should be noted that the Si substrate 30 may be immersed in dilute hydrofluoric acid before being introduced to remove native oxide film.
Subsequently, the Si substrate 30 is heated by the substrate mounting table with a heater 40 in S23. At this time, the temperature of the substrate may be temporarily raised to a temperature higher than the growth temperature and reduced to the growth temperature after thermal cleaning.
Subsequently, an inert gas is introduced into the vacuum chamber 10 while adjusting the flow rate so that the growth pressure will be obtained in S24. It should be noted that the inert gas is argon (Ar) in the present embodiment; however, any inert gas may be used. The sputtering gas pressure of the vacuum chamber 10 is set to a value between 1.2 [mTorr] and 5 [mTorr] by adjusting the flow rate of the inert gas. In the present embodiment below, the pressure is set to 3 [mTorr] or 5 [mTorr].
In S25, subsequently, high-frequency electric power or DC voltage is applied to the target 20 or the target 21 or the target 20 and the target 21 simultaneously. The inert gas plasma was generated to sputter the target 20 or the target 21 or the target 20 and the target 21 simultaneously, which causes crystal growth on the Si substrate 30.
According to the above process, atoms contained in the target 20 and the target 21 are sputtered by ions from the inert gas plasma by applying DC voltage and high-frequency electric power in an inert gas atmosphere, which causes crystal growth on the Si substrate 30 opposed to the targets.
First, the semiconductor multilayer film according to the present embodiment will be illustrated with reference to a drawing.
In the present embodiment, a single crystal N-type Si substrate is used as the Si substrate 110; however, an SOI (Silicon on Insulator) substrate and an SOQ (Silicon on Quartz) substrate may be used, in which a single crystal Si thin film is formed on an insulator. The N-type Si substrate 110 may be e.g. a substrate with (100) plane orientation. In the present embodiment, the Si crystal layer not containing impurities 120 is provided on the N-type Si substrate 110 by the sputter epitaxy method; however, this Si layer not containing impurities may be also provided by other crystal growth methods such as the CVD method. Alternatively, Si and Ge mixed crystals may be provided by the sputter epitaxy method or other crystal growth methods. Si and C mixed crystals may be also grown.
Using a target with (100) plane orientation (boron concentration 2.0×1019/cm3) and a target with (111) plane orientation (boron concentration 2.1×1019/cm3), which contain boron as impurities, the semiconductor layer 130 containing boron as impurities was grown. Ar was used as the inert gas, the pressure thereof was 3 [mTorr], and the growth rates of the Si crystal layer not containing impurities 120 and the boron-containing semiconductor crystal film 130 were both 5 nm per minute. When the growth rate is slower, the activation rate is further improved as shown in
The group 15 element-doped semiconductor crystal multilayer film according to the present embodiment will be illustrated with reference to a drawing.
The Si substrate 210 may be also a single crystal Si substrate. The Si substrate 210 may be also an SOI (Silicon on Insulator) substrate and an SOQ (Silicon on Quartz) substrate, in which a single crystal Si thin film is formed on an insulator. The Si substrate 210 may be also e.g. a Si substrate with (100) plane orientation.
In the present example, the Si crystal layer not containing impurities 220 is provided on the Si substrate 210 by the sputter epitaxy method; however, the same Si crystal layer or Si and Ge mixed crystals may be also provided by other methods such as the CVD method.
The group 15 element-containing Si crystal film 230 is provided on the Si crystal layer not containing impurities 220. It should be noted that phosphorus (P) is used as the group 15 element in the present embodiment below; however, any group 15 element may be used.
The Si crystal layer not containing impurities 240 is provided on the group 15 element-containing Si crystal film 230. In the present embodiment, the Si crystal layer not containing impurities 240 is grown by the sputter epitaxy method; however, the same Si crystal layer may be also provided by other methods such as the CVD method, and in the semiconductor crystal multilayer film, all crystal layers are grown at the same temperature, including the Si substrate 210, the Si crystal layer not containing impurities 220, the semiconductor crystal film containing a group 15 element as impurities 230, and the Si crystal layer not containing impurities 240.
In the present embodiment, a phosphorus (P)-doped Si crystal film was grown using a target including phosphorus (P) as impurities (100 plane orientation, phosphorus concentration 6×1019/cm3) by the sputter epitaxy method. Ar was used as the inert gas and the pressure thereof was 5 [mTorr].
Changes in the impurity activation rate with respect to the crystal growth rate will now be illustrated.
As can be seen from the graph, as the growth rate is raised, the impurity activation rate is linearly reduced. As specific values, an activation rate of 72% at a growth rate of 2.7 nm per minute (growth rate of 20 atomic layers per minute), and an activation rate of 81% at a growth rate of 0.66 nm per minute (growth rate of 5 atomic layers per minute) are obtained. It is therefore found that a slower growth rate indicates a higher impurity activation rate. It was found that a semiconductor crystal film having an impurity activation rate of above 72% could be formed when the growth rate of the semiconductor crystal film was 2.7 nm or less per minute, and a semiconductor crystal film having an impurity activation rate of above 50% could be formed when the growth rate was 7 nm or less per minute at a growth temperature of 400° C.
From
Next, when a phosphorus-doped Si crystal film was grown on a non-doped Si crystal film by the sputter epitaxy method, the degree of diffusion of doped impurities was measured.
In the table above, the backward diffusion represents a depth at which the concentration of impurities, which are reduced and diffused in an exponential manner in the depth direction from the semiconductor crystal film 230 containing group 15 impurities into the semiconductor layer 220 grown using a target not containing impurities, is reduced to 1/10. The forward diffusion represents the average value of concentrations of impurities, which are diffused from the semiconductor crystal film 230 containing group 15 impurities into the semiconductor layer 240 grown using a target not containing impurities, in an approximately constant impurity concentration part in a depth of about 15 nm to 35 nm. As can be seen with reference to the table 1 above, there is no diffusion into the non-doped semiconductor crystal film, a base of the impurity-doped semiconductor crystal film, at a growth temperature of lower than 600° C. and more desirably 500° C. or lower.
On the other hand, it is found that when the non-doped Si semiconductor crystal film is grown on the impurity-doped semiconductor crystal film at a growth temperature of 320 to 600° C., forward diffusion into the non-doped Si semiconductor crystal film is less at a lower temperature.
From the above experimental results, it is found that when a phosphorus (P)-doped semiconductor crystal film is grown by the sputter epitaxy method, the growth temperature is preferably 320 to 500° C.
Using an intrinsic semiconductor not containing impurities as a Si target or a Ge target, an intrinsic semiconductor crystal film of Si or SiGe can be grown in the same manner. Using the crystal growth method which can laterally form the above steep impurity profile, a P-type semiconductor film, an N-type semiconductor film, and an I-type semiconductor film are formed, and various semiconductor junctions such as a PN junction and a PIN junction can be formed. When the I layer of the PIN junction is SiGe, the bandgap is narrower than the bandgap of Si depending on the composition ratio thereof, and thus a photodiode which can respond to a longer wavelength region can be produced.
In the production method for a semiconductor crystal film according to the present invention, a target doped to a concentration D1 and a target not containing a dopant may be simultaneously sputtered. By adjusting the electric power applied to the two targets, the concentration of impurities in a grown crystal film can be controlled (provided that the concentration is equal to or lower than D1).
In the production method for a semiconductor crystal film according to the present invention, a target doped to a concentration D1, a target doped to a concentration D2 and a target not containing a dopant may be simultaneously sputtered. By adjusting electric power applied to the three targets, the concentration of impurities in a grown crystal film can be controlled (provided that the concentration is equal to or lower than D1 and D2).
In addition, impurity elements contained in each of the target doped to the concentration D1 and the target doped to the concentration D2 may be the same or different.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2022-027293 | Feb 2022 | JP | national |
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/JP2023/006605 | 2/23/2023 | WO |
