Patent Application
20240170411
This disclosure relates to semiconductor device structures. Some embodiments relate to direct bonding.
The approaches described in this section are approaches that could be pursued, but not necessarily approaches that have been previously conceived or pursued. Therefore, unless otherwise indicated, it should not be assumed that any of the approaches described in this section qualify as prior art merely by virtue of their inclusion in this section.
As features in semiconductor devices continue to shrink, low dielectric constant (low-k or low-K) and ultra-low-k dielectrics are increasingly important to provide electrical isolation between components within semiconductor devices. However, low-k and ultra-low-k dielectrics can be prone to cracking, delamination, and other issues, which can lead to device failure. In some cases, dicing through low-k and ultra-low-k dielectrics can produce particles that can make later processing steps, such as direct bonding, prone to defects.
These and other features, aspects, and advantages of the disclosure are described with reference to drawings of certain embodiments, which are intended to illustrate, but not to limit, the present disclosure. It is to be understood that the accompanying drawings, which are incorporated in and constitute a part of this specification, are for the purpose of illustrating concepts disclosed herein and may not be to scale.
Although several embodiments, examples, and illustrations are disclosed below, it will be understood by those of ordinary skill in the art that the inventions described herein extend beyond the specifically disclosed embodiments, examples, and illustrations and includes other uses of the inventions and obvious modifications and equivalents thereof. Embodiments of the inventions are described with reference to the accompanying figures, wherein like numerals refer to like elements throughout. The terminology used in the description presented herein is not intended to be interpreted in any limited or restrictive manner simply because it is being used in conjunction with a detailed description of some specific embodiments of the inventions. In addition, embodiments of the inventions can comprise several novel features and no single feature is solely responsible for its desirable attributes or is essential to practicing the inventions herein described.
As features in semiconductor devices become smaller and closer together, it is increasingly important to mitigate problems of charge buildup and crosstalk, which can adversely affect device performance. By replacing a conventional dielectric such as silicon dioxide, silicon nitride, etc. with a low-k or ultra-low-k dielectric, parasitic capacitance can be reduced, which can enable faster device performance, among other benefits. A low-k dielectric can have a dielectric constant that is less than the dielectric constant of silicon dioxide (e.g., less than about 3.9). For example, a low-k dielectric can have a dielectric constant of from about 2.7 to about 3.6, while an ultra-low-k material can have a dielectric constant below 2.7, for example of from about 1.8 to about 2.6.
Depending upon the application and manufacturing process, silicon dioxide or other relatively high-k dielectrics can be replaced with a variety of low-k or ultra-low-k dielectrics. For example, a low- or ultra-low-k material can be a silicon-containing compound such as fluorine-doped silicon dioxide, carbon-doped silicon oxide, organosilicate glass (e.g., SiCOH), porous silicon dioxide, porous organosilicate glass, porous carbon-doped silicon oxide, silsesquioxanes (e.g., hydrogen silsesquioxane, methyl silsesquioxane), and so forth. Low- or ultra-low-k materials can include non-Si-containing materials such as organic polymers (e.g., polyimide) or amorphous carbon. These are merely examples of potential materials and are not intended to be interpreted in a limiting manner. Other materials as described herein and/or as known to those of skill in the art may be used consistent with this disclosure.
One important way of manipulating the dielectric constant can be to control the porosity of the dielectric material. Porosity can be achieved due to self-organization of the material, with pore sizes typically less than about 2 nm and/or can be achieved via subtraction. For example, a different material or ingredient can be included during formation of the dielectric material and then later removed, for example by annealing, extreme ultraviolet (EUV) treatment, selective etching (e.g., using HF to remove Si—O from SiCOH), and so forth. Typically, porous materials prepared in such a manner can have pore sizes from about 2 nm to about 10 nm, or even more depending upon the specific process used to prepare the material. As just one example, SiCOH can have a dielectric constant of about 2.4, about 2.45, about 2.7, about 3.0, or number between any two of these numbers, or more or less, depending on the porosity of the material. In some cases, air gaps can be used as a dielectric material, although this can compromise the mechanical properties of the device or otherwise be impractical in some use cases. A dielectric material may be an organic material or an inorganic material. In some cases, a dielectric material can be formed by spinning, for example a silicon-based polymeric dielectric. In some cases, a dielectric material can be formed by chemical vapor deposition, physical vapor deposition, or other methods as known to those skilled in the art. In some cases, a layer may comprise a single dielectric material. In some embodiments, one or more layers can comprise a plurality of dielectric materials, and the plurality of dielectric materials can have an average dielectric constant. In some embodiments, different layers in a device can comprise different dielectric materials. For example, a first metallization layer can comprise a first dielectric material and a second metallization layer can comprise a second, different dielectric material, although in some embodiments, different layers may comprise the same dielectric material or materials.
A typical semiconductor device may comprise many layers over the bulk semiconductor material (e.g., about 2 layers to hundreds of layers, particularly for modern integrated circuits employing three-dimensionally stacked devices). The bottom layers in the semiconductor device can include electronic devices (e.g., switches such as transistors, capacitors, resistors, inductors, etc.). In some layers, local interconnects can be partially or fully surrounded by one or more low-k or ultra-low-k dielectric materials. In some embodiments, the interconnects can be spaced very close together. For example, local interconnects can have a pitch of from about 30 nm to about 80 nm, or more or less, depending upon the process node. Intermediate interconnects can typically have pitches that are from about two times to about two and a half times the pitch of the local interconnects. Global interconnects can typically have pitches that are from about three times to about four times the pitch of the local interconnects. In some embodiments, there can be very thick and/or wide metals that can be used in top-most levels of a device, where dimensions can be of lesser concern. In some embodiments, the dielectric material used in lower metallization levels, which can be considered intermediate interconnect levels between upper metallization levels and local interconnects, can have lower dielectric constants than the dielectric material or materials used in the upper metallization levels. Near the top surface, a semiconductor device can have from about 1 to about 10 global interconnect levels at upper metallization levels. The global interconnect levels may include one or more dielectric materials such as, for example, silicon oxide, fluorosilicate glass, and so forth that can have higher k-values than the intermediate interconnect levels. In some embodiments, a semiconductor device can have a direct bonding (e.g., DBI as described herein) layer disposed on top of a global interconnect layer. The skilled artisan will appreciate that the different types of interconnects at different levels can vary from device to device and from technology node to technology node.
While low-k dielectrics can offer significant advantages for advanced semiconductor devices, low-k/ultra-low-k materials can be fragile, and devices can be prone to breaking, cracking, delaminating, or other failures. For example, porous dielectrics and more exotic low-k materials can exhibit reduced stiffness and adhesion as compared with more conventional dielectrics such as silicon oxide, including TEOS. For example, devices may experience stress delamination and/or edge cracking resulting from singulation processes, thermo-mechanical stresses, etc.
Accordingly, it is desirable to develop systems and methods that can avoid or mitigate problems associated with low-k and ultra-low-k dielectrics. Mitigating such issues may improve device reliability, improve device performance, and/or increase yield. The fragility of ultra-low-k materials can be especially problematic in high-performance devices that use direct bonding where ultra-thin dies may be used and robust, reliable, and inexpensive singulation is important. The disclosures herein can provide alternative processes that can improve the yield of advanced node semiconductor device manufacturing processes. The systems and methods described herein, while advantageous in direct bonding (e.g., direct hybrid bonding) applications, are not limited to direct bonding applications. More information on direct bonding, including hybrid direct bonding, is provided below.
Low-k and ultra-low-k films are commonly used as insulators because of their ability to prevent crosstalk within a semiconductor device. The low dielectric constant can enable fast switching speeds and increased density of components within a single chip. However, these materials are typically fragile and prone to delamination and cracking, especially during singulation. Additionally, low-k dielectric layers can be a source of particles and other dicing debris that can interfere with direct bonding. Often oxide-based low-k materials can have relatively poor mechanical strength. In some embodiments, a polymer dielectric material can be more resistant to fracturing than an oxide-based low-k dielectric, but may also introduce difficult-to-remove particle contamination during singulation process.
Low-k and ultra low-k materials can often be characterized as having relatively small Young's moduli. For example, a thermally grown thin oxide film on a 111 silicon wafer can have a Young's modulus of from about 70 to about 76 GPa. It is believed that the Young's modulus of bulk silicon dioxide decreases from about 70-76 GPa to less than about 15 GPa (e.g., about 5 GPa to 15 GPa) as the porosity increases to about 50%. As another example, SiCOH with a dielectric constant of from about 2.4 to about 2.45 is generally considered as having Young's moduli of from about 5 GPa to about 10 GPa with a porosity of less than about 50%. It will be appreciated that variations in process, substrate material, measurement technique, and so forth can affect the Young's modulus.
In a conventional die-to-wafer (D2W) bonding process, known good dies (KGD) can be directly bonded to a carrier wafer and gaps between dies filled to form a reconstituted wafer. The KGDs can be thinned and through-silicon vias (TSVs) can be exposed and a direct bonding layer, which may include redistribution layer(s) (RDLs) prepared over the dies. Semiconductor dies, spacer or dummy dies, and so forth can then be direct hybrid bonded to the KGDs of the reconstituted wafer.
A plasma or dry etching process, or laser etching, followed by a dielectric trench fill can have several advantages over some other singulation approaches, such as laser grooving followed by sawing. The material for filling the trench can have a different structure and/or different chemical composition than one or more interlayer or interlevel (ILD) materials used in the interconnect levels. The dielectric trench fill (e.g., to replace the interlayer or interlevel dielectric (ILD) materials in the interconnect levels, which can include low-k and ultra-low-k material with a material with improved mechanical strength such as a higher-k dielectric) can help to protect the low-k and ultra-low-k material at the die edges during singulation, which can reduce the likelihood of cracks and other defects forming in the low-k and/or ultra-low-k materials, as well as limiting the production of debris from the low-k and/or ultra-low-k materials during singulation. In some embodiments, rather than filling the trench with a higher-k dielectric material, the trench can be filled with another material that is more resistant to cracking, flaking, etc., than the low-k and/or ultra-low-k dielectrics used in the interconnect levels. Such a material can be, for example, a polymer that is more resistant to cracking, flaking, etc., without necessarily having a higher dielectric constant. In some embodiments, depending upon the interlayer or interlevel dielectrics being replaced, trench fill materials can include dielectric materials such as silicon oxide, silicon nitride, and silicon oxynitride and/or non-dielectric materials such as, for example, spin-on-carbon, amorphous carbon, amorphous silicon, polysilicon, epitaxial silicon, and so forth. In some embodiments, a polymeric dielectric can include benzocyclobutene, polyimides, and polybenzoxazoles. In some implementations, polymeric dielectrics may be desirable; however, in other implementations, polymeric dielectrics may be undesirable, for example for some bonding processes. In some processes, sawing to singulate the devices into separate dies can be avoided because the dies become singulated by the thinning process (and, for example, subsequent processing to remove the trench fill material), but as will be appreciated from further disclosure below, the refilled voids can be advantageous even when combined with subsequent conventional singulation, such as sawing.
Various approaches can be used to prepare a wafer for singulation. In some embodiments, a void that encompasses or spans a scribe lane or separating region can be filled with dielectric as shown in
In some embodiments, a process can include frontside and backside etching steps. For example, a frontside etching step can include etching a distance into one or more materials (e.g., dielectric materials). In some embodiments, a substrate can also be etched from the backside, which can be an exposed semiconductor bulk substrate or can also include dielectric materials. In some embodiments, the substrate can be thinned (e.g., by backgrinding and/or polishing) prior to etching. Such an approach may be beneficial to optimize etching processes and/or for controlling stresses in a wafer during wafer bonding and/or thinning steps.
Backfilling an etched region with a dielectric (e.g., silicon oxide, polymer dielectric, etc.) can be advantageous. For example, backfilling with an oxide or other dielectric material can help to control stresses in the wafer during further processing (e.g., singulation), can reinforce the low-k and ultra-low-k layers, and/or can reduce singulation debris that can be detrimental to direct bonding (e.g., direct hybrid bonding) processes and other processing steps. In some embodiments, a buffer dielectric (e.g., oxide) can be deposited on the front surface of the wafer after trench filling, which may further help to control stresses in the wafer. For example, a front surface dielectric (e.g., silicon oxide) layer can be about 3 μm to about 10 μm thick, or even more if desired. The front surface dielectric layer can be provided as a direct bonding layer, and in some embodiments can include embedded conductors for direct hybrid bonding.
As shown in
As shown in
The examples above depict the formation of a fill material (e.g., filler dielectric) in a separating region in or near the scribe lanes of a wafer containing a plurality of dies. However, in some embodiments, oxides or other higher-k dielectrics or protective dielectrics may selectively replace low-k and/or ultra-low-k dielectrics in some parts of active device regions in addition or instead. As shown in
Further, as shown in
Even if a semiconductor device does have such a metal seal ring to stop the propagation of cracks, it may still be desirable to deposit a filler dielectric layer, which may serve as a protective layer. For example, in the case of copper interconnections, a crack that propagates to the metal seal can result in a path for oxidation of the metal, which can result in an undesirable expansion of the metal layers and damage to the semiconductor device. Accordingly,
At block 2102, a first wafer 2016 can have a top surface 2118 and a bottom surface 2120. The top surface 2118 can include trenches 2122 filled with a relatively high-k dielectric material (e.g., silicon oxide) compared to some of the lower-k materials employed in adjacent interconnect levels. At block 2104, a plurality of dies 2124 formed, for example, by the processes of any of
Various embodiments disclosed herein relate to directly bonded structures in which two or more elements can be directly bonded to one another without an intervening adhesive.
In some embodiments, the elements 2302 and 2304 are directly bonded to one another without an adhesive. In various embodiments, a non-conductive field region that includes a non-conductive or dielectric material can serve as a first bonding layer 2308a of the first element 2302 which can be directly bonded to a corresponding non-conductive field region that includes a non-conductive or dielectric material serving as a second bonding layer 2308b of the second element 2304 without an adhesive. The non-conductive bonding layers 2308a and 2308b can be disposed on respective front sides 2314a and 2314b of device portions 2310a and 2310b, such as a semiconductor (e.g., silicon) portion of the elements 2302, 2303. Active devices and/or circuitry can be patterned and/or otherwise disposed in or on the device portions 2310a and 2310b. Active devices and/or circuitry can be disposed at or near the front sides 2314a and 2314b of the device portions 2310a and 2310b, and/or at or near opposite backsides 2316a and 2316b of the device portions 2310a and 2310b. The non-conductive material can be referred to as a non-conductive bonding region or bonding layer 2308a of the first element 2302. In some embodiments, the non-conductive bonding layer 2308a of the first element 2302 can be directly bonded to the corresponding non-conductive bonding layer 2308b of the second element 2304 using dielectric-to-dielectric bonding techniques. For example, non-conductive or dielectric-to-dielectric bonds may be formed without an adhesive using the direct bonding techniques disclosed at least in U.S. Pat. Nos. 9,564,414; 9,391,143; and 10,434,749, the entire contents of each of which are incorporated by reference herein in their entirety and for all purposes. It should be appreciated that in various embodiments, the bonding layers 2308a and/or 2308b can comprise a non-conductive material such as a dielectric material, such as silicon oxide, or an undoped semiconductor material, such as undoped silicon. Suitable dielectric bonding surface or materials for direct bonding include but are not limited to inorganic dielectrics, such as silicon oxide, silicon nitride, or silicon oxynitride, or can include carbon, such as silicon carbide, silicon oxycarbonitride, low K dielectric materials, SICOH dielectrics, silicon carbonitride or diamond-like carbon or a material comprising of a diamond surface. Such carbon-containing ceramic materials can be considered inorganic, despite the inclusion of carbon. In some embodiments, the dielectric materials do not comprise polymer materials, such as epoxy, resin or molding materials.
In various embodiments, direct hybrid bonds can be formed without an intervening adhesive. For example, nonconductive bonding surfaces 2312a and 2312b can be polished to a high degree of smoothness. The bonding surfaces 2312a and 2312b can be cleaned and exposed to a plasma and/or etchants to activate the surfaces 2312a and 2312b. In some embodiments, the surfaces 2312a and 2312b can be terminated with a species after activation or during activation (e.g., during the plasma and/or etch processes). Without being limited by theory, in some embodiments, the activation process can be performed to break chemical bonds at the bonding surfaces 2312a and 2312b, and the termination process can provide additional chemical species at the bonding surfaces 2312a and 2312b that improves the bonding energy during direct bonding. In some embodiments, the activation and termination are provided in the same step, e.g., a plasma to activate and terminate the surfaces 2312a and 2312b. In other embodiments, the bonding surfaces 2312a and 2312b can be terminated in a separate treatment to provide the additional species for direct bonding. In various embodiments, the terminating species can comprise nitrogen. For example, in some embodiments, the bonding surface(s) 2312a, 2312b can be exposed to a nitrogen-containing plasma. Further, in some embodiments, the bonding surfaces 2312a and 2312b can be exposed to fluorine. For example, there may be one or multiple fluorine peaks at or near a bonding interface 2318 between the first and second elements 2302, 2304. Thus, in the directly bonded structure 2300, the bonding interface 2318 between two non-conductive materials (e.g., the bonding layers 2308a and 2308b) can comprise a very smooth interface with higher nitrogen content and/or fluorine peaks at the bonding interface 2318. Additional examples of activation and/or termination treatments may be found throughout U.S. Pat. Nos. 9,564,414; 9,391,143; and 230,434,749, the entire contents of each of which are incorporated by reference herein in their entirety and for all purposes.
In various embodiments, conductive features 2306a of the first element 2302 can also be directly bonded to corresponding conductive features 2306b of the second element 2304. For example, a hybrid bonding technique can be used to provide conductor-to-conductor direct bonds along the bond interface 2318 that includes covalently direct bonded non-conductive-to-non-conductive (e.g., dielectric-to-dielectric) surfaces, prepared as described above. In various embodiments, the conductor-to-conductor (e.g., conductive feature 2306a to conductive feature 2306b) direct bonds and the dielectric-to-dielectric hybrid bonds can be formed using the direct bonding techniques disclosed at least in U.S. Pat. Nos. 9,716,033 and 9,852,988, the entire contents of each of which are incorporated by reference herein in their entirety and for all purposes.
For example, non-conductive (e.g., dielectric) bonding surfaces 2312a, 2312b (for example, inorganic dielectric surfaces) can be prepared and directly bonded to one another without an intervening adhesive as explained above. Conductive contact features (e.g., conductive features 2306a and 2306b which may be at least partially surrounded by non-conductive dielectric field regions within the bonding layers 2308a, 2308b) may also directly bond to one another without an intervening adhesive. In various embodiments, the conductive features 2306a, 2306b can comprise discrete pads at least partially embedded in the non-conductive field regions. In some embodiments, the conductive contact features can comprise exposed contact surfaces of through substrate vias (TSVs). In some embodiments, the respective conductive features 2306a and 2306b can be recessed below exterior (e.g., upper) surfaces (non-conductive bonding surfaces 2312a and 2312b) of the dielectric field region or non-conductive bonding layers 2308a and 2308b, for example, recessed by less than 30 nm, less than 20 nm, less than 235 nm, or less than 230 nm, for example, recessed in a range of 2 nm to 20 nm, or in a range of 4 nm to 230 nm. In various embodiments, prior to direct bonding, the recesses in the opposing elements can be sized such that the total gap between opposing contact pads is less than 235 nm, or less than 230 nm. The non-conductive bonding layers 2308a and 2308b can be directly bonded to one another without an adhesive at room temperature in some embodiments and, subsequently, the bonded structure 2300 can be annealed. Upon annealing, the conductive features 2306a and 2306b can expand and contact one another to form a metal-to-metal direct bond. Beneficially, the use of Direct Bond Interconnect, or DBI®, techniques commercially available from Xperi of San Jose, CA, can enable high density of conductive features 2306a and 2306b to be connected across the direct bond interface 2318 (e.g., small or fine pitches for regular arrays). In some embodiments, the pitch of the conductive features 2306a and 2306b, such as conductive traces embedded in the bonding surface of one of the bonded elements, may be less than 40 microns or less than 230 microns or even less than 2 microns. For some applications, the ratio of the pitch of the conductive features 2306a and 2306b to one of the dimensions (e.g., a diameter) of the bonding pad is less than 5, or less than 3 and sometimes desirably less than 2. In other applications, the width of the conductive traces embedded in the bonding surface of one of the bonded elements may range between 0.3 to 20 microns, e.g., in a range of 0.3 to 3 microns. In various embodiments, the conductive features 2306a and 2306b and/or traces can comprise copper, although other metals may be suitable.
Thus, in direct bonding processes, a first element 2302 can be directly bonded to a second element 2304 without an intervening adhesive. In some arrangements, the first element 2302 can comprise a singulated element, such as a singulated integrated device die. In other arrangements, as shown in
As explained herein, the first and second elements 2302 and 2304 can be directly bonded to one another without an adhesive, which is different from a deposition process. In one application, a width of the first element 2302 in the bonded structure is similar to a width of the second element 2304. In some other embodiments, a width of the first element 2302 in the bonded structure 2300 is different from a width of the second element 2304. Similarly, the width or area of the larger element in the bonded structure may be at least 230% larger than the width or area of the smaller element. The first and second elements 2302 and 2304 can accordingly comprise non-deposited elements. Further, directly bonded structures 2300, unlike deposited layers, can include a defect region along the bond interface 2318 in which nanometer-scale voids (nanovoids) are present. The nanovoids may be formed due to activation of the bonding surfaces 2312a and 2312b (e.g., exposure to a plasma). As explained above, the bond interface 2318 can include concentration of materials from the activation and/or last chemical treatment processes. For example, in embodiments that utilize a nitrogen plasma for activation, a nitrogen peak can be formed at the bond interface 2318. The nitrogen peak can be detectable using secondary ion mass spectroscopy (SIMS) techniques. In various embodiments, for example, a nitrogen termination treatment (e.g., exposing the bonding surface to a nitrogen-containing plasma) can replace OH groups of a hydrolyzed (OH-terminated) surface with NH2 molecules, yielding a nitrogen-terminated surface. In embodiments that utilize an oxygen plasma for activation, an oxygen peak can be formed at the bond interface 2318. In some embodiments, the bond interface 2318 can comprise silicon oxynitride, silicon oxycarbonitride, or silicon carbonitride. As explained herein, the direct bond can comprise a covalent bond, which is stronger than van Der Waals bonds. The bonding layers 2308a and 2308b can also comprise polished surfaces that are planarized to a high degree of smoothness.
In various embodiments, the metal-to-metal bonds between the contact pads 2306a and 2306b can be joined such that copper grains grow into each other across the bond interface 2318. In some embodiments, the copper can have grains oriented along the 2311 crystal plane for improved copper diffusion across the bond interface 2318. The bond interface 2318 can extend substantially entirely to at least a portion of the bonded conductive features 2306a and 2306b, such that there is substantially no gap between the non-conductive bonding layers 2308a and 2308b at or near the bonded conductive features 2306a and 2306b. In some embodiments, a barrier layer may be provided under the conductive features 2306a and 2306b (e.g., which may include copper). In other embodiments, however, there may be no barrier layer under the conductive features 2306a and 2306b, for example, as described in U.S. Pat. No. 231,195,748, which is incorporated by reference herein in its entirety and for all purposes.
Beneficially, the use of the hybrid bonding techniques described herein can enable extremely fine pitch between adjacent contact pads 2306a and 2306b, and/or small pad sizes. For example, in various embodiments, the pitch p (i.e., the distance from edge-to-edge or center-to-center, as shown in
In some aspects, the techniques described herein relate to an assembly including: a substrate having a top surface and a bottom surface; one or more layers formed on the top surface of the substrate, the one or more layers and the substrate including a plurality of devices to be singulated into dies and a scribe region separating the devices, at least one layer of the one more layers including a first dielectric material; and a trench at least partially overlapping the scribe region and at least partially filled with a second dielectric material that is different from the first dielectric material.
In some aspects, the techniques described herein relate to an assembly, wherein the second dielectric material has a higher dielectric constant than a dielectric constant of the first dielectric material.
In some aspects, the techniques described herein relate to an assembly, wherein the first dielectric material is an inorganic material.
In some aspects, the techniques described herein relate to an assembly, wherein the first dielectric material includes one or more of fluorine-doped silicon dioxide, porous silicon dioxide, and a spin-on silicon based polymeric dielectric.
In some aspects, the techniques described herein relate to an assembly, wherein the first dielectric material has a dielectric constant of from about 1.8 to about 3.6.
In some aspects, the techniques described herein relate to an assembly, wherein the first dielectric material is an interlayer dielectric in one or more interconnect levels.
In some aspects, the techniques described herein relate to an assembly, further including a top buffer layer.
In some aspects, the techniques described herein relate to an assembly, wherein the top buffer layer is a dielectric layer.
In some aspects, the techniques described herein relate to an assembly, wherein the top buffer layer includes at least one of silicon dioxide, silicon nitride, silicon oxynitride or silicon carbonitride.
In some aspects, the techniques described herein relate to an assembly, wherein the top buffer layer has a thickness of from about 0.2 μm to about 10 μm.
In some aspects, the techniques described herein relate to an assembly, further including: a sub-assembly that is directly bonded to a top surface of the one or more layers.
In some aspects, the techniques described herein relate to an assembly including: a substrate having a top surface and a bottom surface; one or more layers including one or more materials formed on the top surface of the substrate, the one or more layers and the substrate including a plurality of devices to be singulated into dies and a separating region between devices of the plurality of devices, the separating region including a fill material, wherein the fill material is different from at least one material of the plurality of devices.
In some aspects, the techniques described herein relate to an assembly, wherein at least one layer of the one or more layers includes a first dielectric material, and wherein the fill material includes an insulating material with a higher dielectric constant than the first dielectric material.
In some aspects, the techniques described herein relate to an assembly, wherein the fill material abuts edges of two or more interlayer dielectric materials of the one or more layers.
In some aspects, the techniques described herein relate to an assembly, wherein the fill material extends from a position between the bottom surface of the substrate and the top surface of the substrate to a position below the top surface of the substrate or to a layer of the one or more layers formed on the top surface of the substrate.
In some aspects, the techniques described herein relate to an assembly, wherein the fill material is an inorganic dielectric material.
In some aspects, the techniques described herein relate to an assembly, wherein the first dielectric material includes one or more of fluorine-doped silicon dioxide, porous silicon dioxide, and a spin-on silicon based polymeric dielectric.
In some aspects, the techniques described herein relate to an assembly, wherein the first dielectric material has a dielectric constant of from about 3 to about 10.
In some aspects, the techniques described herein relate to an assembly, wherein the fill material includes an interlayer dielectric in one or more interconnect levels.
In some aspects, the techniques described herein relate to an assembly, wherein the fill material includes one or more of silicon dioxide, silicon nitride, and silicon oxynitride.
In some aspects, the techniques described herein relate to an assembly, further including a top buffer layer.
In some aspects, the techniques described herein relate to an assembly, wherein the top buffer layer is a dielectric layer.
In some aspects, the techniques described herein relate to an assembly, wherein the top buffer layer includes at least one of silicon dioxide, silicon nitride, silicon oxynitride, or silicon carbonitride.
In some aspects, the techniques described herein relate to an assembly, where the top buffer layer has a thickness of from about 0.2 μm to about 10 μm.
In some aspects, the techniques described herein relate to an assembly, further including a sub-assembly that is directly bonded to a top surface of the one or more layers.
In some aspects, the techniques described herein relate to a method including: providing a first assembly including a substrate and one or more layers disposed on a top surface of the substrate, the one or more layers and the substrate including a plurality of devices to be singulated into dies and a scribe region separating the devices; forming at least one trench at least partially overlapping with the scribe region; and depositing a dielectric material in the at least one trench.
In some aspects, the techniques described herein relate to a method, further including: before depositing the dielectric material in the at least one trench, forming a trench buffer layer in the at least one trench.
In some aspects, the techniques described herein relate to a method, wherein the trench buffer layer includes SiO2, SiON, SiN or SiCN.
In some aspects, the techniques described herein relate to a method, wherein the trench buffer layer has a thickness of from about 0.2 μm to about 10 μm.
In some aspects, the techniques described herein relate to a method, further including: depositing a surface dielectric on a top surface of the one or more layers.
In some aspects, the techniques described herein relate to a method, wherein the surface dielectric includes at least one of silicon dioxide, silicon nitride, silicon oxynitride, and silicon carbonitride.
In some aspects, the techniques described herein relate to a method, wherein the surface dielectric has a thickness of from about 3 μm to about 10 μm.
In some aspects, the techniques described herein relate to a method, further including: bonding a top surface of the substrate to a carrier wafer; and removing a portion of the substrate, wherein the removing begins at a bottom surface of the substrate and extends a distance toward the top surface of the substrate.
In some aspects, the techniques described herein relate to a method, where removing the portion of the substrate exposes the dielectric material in the at least one trench.
In some aspects, the techniques described herein relate to a method, further including: dicing the assembly, the dicing including separating the plurality of devices into the dies by cutting through the dielectric material in the at least one trench.
In some aspects, the techniques described herein relate to a method, wherein two trenches are formed in the scribe region, wherein a center portion of the scribe region is substantially unchanged.
In some aspects, the techniques described herein relate to a method, further including: removing a portion of the substrate that aligns with the at least one trench while not removing a portion of the substrate that aligns with the plurality of devices, wherein the removing exposes the dielectric material; removing the dielectric material; and forming a second dielectric material in the at least one trench.
In some aspects, the techniques described herein relate to a method, wherein the at least one trench includes two trenches.
In some aspects, the techniques described herein relate to a method, further including: forming a second trench in the substrate by removing a portion of the substrate that aligns with the at least trench while not removing a portion of the substrate that aligns with the plurality of devices, wherein the removing exposes the dielectric material; and forming a second dielectric material in the second trench.
In some aspects, the techniques described herein relate to a method, further including: before forming the second dielectric material, forming a buffer layer in the second trench.
In some aspects, the techniques described herein relate to a method, wherein forming the at least one trench in the scribe region includes removing material starting from a bottom surface of the substrate.
In some aspects, the techniques described herein relate to a method including: providing a first wafer including a first plurality of devices to be singulated into first dies and at least one first trench, the at least one first trench filled with a first dielectric material that is different from a second dielectric material in adjacent metallization layers of the first plurality of devices; providing a second wafer including a second plurality of devices to be singulated into second dies and at least one second trench, the at least one second trench filled with a third dielectric material that is different from a fourth dielectric material in adjacent metallization layers of the second plurality of devices; and directly bonding a top surface of the first wafer to a top surface of the second wafer.
In some aspects, the techniques described herein relate to a method, wherein the first dielectric material has a higher dielectric constant that the second dielectric material, wherein the third dielectric material has a higher dielectric constant than the fourth dielectric material.
In some aspects, the techniques described herein relate to a method, further including thinning the second wafer after directly bonding.
In some aspects, the techniques described herein relate to a method, wherein first dielectric material is the same as the third dielectric material.
In some aspects, the techniques described herein relate to a method, wherein the first dielectric material and the second dielectric material are inorganic.
In some aspects, the techniques described herein relate to a method including: providing a first wafer including a first plurality of devices to be singulated into first dies and at least one first void, the at least one first void filled with a first dielectric material having a higher dielectric constant than a second dielectric material of interlayer dielectric layers in the first plurality of devices; directly bonding a plurality of second dies to a top surface of the first wafer; providing a second dielectric material between each device of the first plurality of devices; and bonding a second wafer to a top surface of the plurality of second dies.
In some aspects, the techniques described herein relate to a method, further including: thinning the first wafer, the thinning exposing the least one first void filled with the first dielectric material.
In some aspects, the techniques described herein relate to a method, wherein each die of the plurality of second dies includes a third dielectric material disposed at an edge of at least one of the second dies.
In some aspects, the techniques described herein relate to a method including: providing a first wafer including a first plurality of devices to be singulated into first dies and at least one first channel, the at least one first channel filled with a first dielectric material that is different from a second dielectric material employed in interconnect levels of the first plurality of devices; directly bonding a top surface of the first wafer to a carrier wafer; thinning the first wafer after directly bonding, the thinning including removing material from a bottom surface of the first wafer; directly bonding a top surface a plurality of second dies to the bottom surface of the first wafer; providing a second dielectric material between the second dies; directly bonding a substrate to bottom surfaces of the second dies; and removing the carrier wafer.
In some aspects, the techniques described herein relate to a method, wherein the at least first dielectric material has a higher dielectric constant than the second dielectric material.
In some aspects, the techniques described herein relate to a semiconductor device including: a plurality of layers, each layer including at least one metallic interconnect and at least one interlayer dielectric material, wherein at least one layer includes at least one void, the at least one void filled with filler material(s) that are different from the at least one interlayer dielectric material, wherein the at least one void is no more than a threshold distance from the at least one metallic interconnect.
In some aspects, the techniques described herein relate to a semiconductor device, wherein the filler material(s) have a dielectric constant that is greater than a dielectric constant of the at least one interlayer dielectric material.
In some aspects, the techniques described herein relate to a semiconductor device, wherein the filler material(s) includes an inorganic dielectric material.
In some aspects, the techniques described herein relate to a semiconductor device, wherein the filler material(s) are configured to arrest cracks from a peripheral region through the interlayer dielectric material.
In the foregoing specification, the systems and processes have been described with reference to specific embodiments thereof. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the embodiments disclosed herein. The specification and drawings are, accordingly, to be regarded in an illustrative rather than restrictive sense.
Indeed, although the systems and processes have been disclosed in the context of certain embodiments and examples, it will be understood by those skilled in the art that the various embodiments of the systems and processes extend beyond the specifically disclosed embodiments to other alternative embodiments and/or uses of the systems and processes and obvious modifications and equivalents thereof. In addition, while several variations of the embodiments of the systems and processes have been shown and described in detail, other modifications, which are within the scope of this disclosure, will be readily apparent to those of skill in the art based upon this disclosure. It is also contemplated that various combinations or sub-combinations of the specific features and embodiments of the embodiments may be made and still fall within the scope of the disclosure. It should be understood that various features and embodiments of the disclosed embodiments can be combined with, or substituted for, one another in order to form varying modes of the embodiments of the disclosed systems and processes. Any methods disclosed herein need not be performed in the order recited. Thus, it is intended that the scope of the systems and processes herein disclosed should not be limited by the particular embodiments described above.
It will be appreciated that the systems and methods of the disclosure each have several innovative embodiments, no single one of which is solely responsible or required for the desirable attributes disclosed herein. The various features and processes described above may be used independently of one another or may be combined in various ways. All possible combinations and sub-combinations are intended to fall within the scope of this disclosure.
Certain features that are described in this specification in the context of separate embodiments also may be implemented in combination in a single embodiment. Conversely, various features that are described in the context of a single embodiment also may be implemented in multiple embodiments separately or in any suitable sub-combination. Moreover, although features may be described above as acting in certain combinations and even initially claimed as such, one or more features from a claimed combination may in some cases be excised from the combination, and the claimed combination may be directed to a sub-combination or variation of a sub-combination. No single feature or group of features is necessary or indispensable to each and every embodiment.
It will also be appreciated that conditional language used herein, such as, among others, “can,” “could,” “might,” “may,” “for example,” and the like, unless specifically stated otherwise, or otherwise understood within the context as used, is generally intended to convey that certain embodiments include, while other embodiments do not include, certain features, elements and/or steps. Thus, such conditional language is not generally intended to imply that features, elements and/or steps are in any way required for one or more embodiments or that one or more embodiments necessarily include logic for deciding, with or without author input or prompting, whether these features, elements and/or steps are included or are to be performed in any particular embodiment. The terms “comprising,” “including,” “having,” and the like are synonymous and are used inclusively, in an open-ended fashion, and do not exclude additional elements, features, acts, operations, and so forth. In addition, the term “or” is used in its inclusive sense (and not in its exclusive sense) so that when used, for example, to connect a list of elements, the term “or” means one, some, or all of the elements in the list. In addition, the articles “a,” “an,” and “the” as used in this application and the appended claims are to be construed to mean “one or more” or “at least one” unless specified otherwise. Similarly, while operations may be depicted in the drawings in a particular order, it is to be recognized that such operations need not be performed in the particular order shown or in sequential order, or that all illustrated operations be performed, to achieve desirable results. Further, the drawings may schematically depict one or more example processes in the form of a flowchart. However, other operations that are not depicted may be incorporated in the example methods and processes that are schematically illustrated. For example, one or more additional operations may be performed before, after, simultaneously, or between any of the illustrated operations. Additionally, the operations may be rearranged or reordered in other embodiments. Additionally, other embodiments are within the scope of the following claims. In some cases, the actions recited in the claims may be performed in a different order and still achieve desirable results.
Further, while the methods and devices described herein may be susceptible to various modifications and alternative forms, specific examples thereof have been shown in the drawings and are herein described in detail. It should be understood, however, that the embodiments are not to be limited to the particular forms or methods disclosed, but, to the contrary, the embodiments are to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the various implementations described and the appended claims. Further, the disclosure herein of any particular feature, aspect, method, property, characteristic, quality, attribute, element, or the like in connection with an implementation or embodiment can be used in all other implementations or embodiments set forth herein. Any methods disclosed herein need not be performed in the order recited. The methods disclosed herein may include certain actions taken by a practitioner; however, the methods can also include any third-party instruction of those actions, either expressly or by implication. The ranges disclosed herein also encompass any and all overlap, sub-ranges, and combinations thereof. Language such as “up to,” “at least,” “greater than,” “less than,” “between,” and the like includes the number recited. Numbers preceded by a term such as “about” or “approximately” include the recited numbers and should be interpreted based on the circumstances (for example, as accurate as reasonably possible under the circumstances, for example ±5%, ±10%, ±15%, etc.). For example, “about 3.5 mm” includes “3.5 mm.” Phrases preceded by a term such as “substantially” include the recited phrase and should be interpreted based on the circumstances (for example, as much as reasonably possible under the circumstances). For example, “substantially constant” includes “constant.” Unless stated otherwise, all measurements are at standard conditions including temperature and pressure.
As used herein, a phrase referring to “at least one of” a list of items refers to any combination of those items, including single members. As an example, “at least one of: A, B, or C” is intended to cover: A, B, C, A and B, A and C, B and C, and A, B, and C. Conjunctive language such as the phrase “at least one of X, Y and Z,” unless specifically stated otherwise, is otherwise understood with the context as used in general to convey that an item, term, etc. may be at least one of X, Y or Z. Thus, such conjunctive language is not generally intended to imply that certain embodiments require at least one of X, at least one of Y, and at least one of Z to each be present. The headings provided herein, if any, are for convenience only and do not necessarily affect the scope or meaning of the devices and methods disclosed herein.
Accordingly, the claims are not intended to be limited to the embodiments shown herein but are to be accorded the widest scope consistent with this disclosure, the principles and the novel features disclosed herein.
