Patent Application
20250040214
Semiconductor devices are used in a variety of electronic applications, such as, for example, personal computers, cell phones, digital cameras, and other electronic equipment. Semiconductor devices are typically fabricated by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers of material over a semiconductor substrate, and patterning the various material layers using lithography to form circuit components and elements thereon.
The semiconductor industry continues to improve the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continual reductions in minimum feature size, which allow more components to be integrated into a given area. However, as the minimum feature sizes are reduced, additional problems arise that should be addressed.
Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting.
For the sake of brevity, conventional techniques related to conventional semiconductor device fabrication may not be described in detail herein. Moreover, the various tasks and processes described herein may be incorporated into a more comprehensive procedure or process having additional functionality not described in detail herein. In particular, various processes in the fabrication of semiconductor devices are well-known and so, in the interest of brevity, many conventional processes will only be mentioned briefly herein or will be omitted entirely without providing the well-known process details. As will be readily apparent to those skilled in the art upon a complete reading of the disclosure, the structures disclosed herein may be employed with a variety of technologies, and may be incorporated into a variety of semiconductor devices and products. Further, it is noted that semiconductor device structures include a varying number of components and that single components shown in the illustrations may be representative of multiple components.
It should be understood that, although the terms first, second, third etc. may be used herein to describe various elements, components, regions, layers, portions and/or sections, these elements, components, regions, layers, portions and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, portion or section from another region, layer, or section. Thus, a first element, component, region, layer, portion, or section discussed below could be termed a second element, component, region, layer, portion, or section without departing from the teachings of the present disclosure.
Furthermore, spatially relative terms, such as “over”, “overlying”, “above”, “upper”, “top”, “under”, “underlying”, “below”, “lower”, “bottom”, and the like, may be used herein for ease of description to describe one element's or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. When a spatially relative term, such as those listed above, is used to describe a first element with respect to a second element, the first element may be directly on the other element, or intervening elements or layers may be present.
In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
It is noted that references in the specification to “one embodiment,” “an embodiment,” “an example embodiment,” “exemplary,” “example,” etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. Further, when a particular feature, structure or characteristic is described in connection with an embodiment, it would be within the knowledge of one skilled in the art to affect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described.
In certain embodiments herein, a “material layer” is a layer that includes at least 50 wt. % of the identified material, for example at least 60 wt. % of the identified material, at least 75 wt. % of the identified material, at least 90 wt. % of the identified material, at least 95 wt. % of the identified material, or at least 99 wt. % of the identified material; and a layer that is a “material” includes at least 50 wt. % of the identified material, for example at least 60 wt. % of the identified material, at least 75 wt. % of the identified material, at least 90 wt. % of the identified material, at least 95 wt. % of the identified material, or at least 99 wt. % of the identified material. For example, certain embodiments, each of an aluminum layer and a layer of aluminum is a layer that is at least 50 wt. %, at least 60 wt. %, at least 75 wt. %, at least 90 wt. %, at least 95 wt. %, or at least 99 wt. % of aluminum.
It is to be understood that the phraseology or terminology herein is for the purpose of description and not of limitation, such that the terminology or phraseology of the present specification is to be interpreted by those skilled in relevant art(s) in light of the teachings herein.
The following disclosure provides many different embodiments, or examples, for implementing different features of the disclosed subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. Throughout the description herein, unless otherwise specified, the same reference numeral in different figures refers to the same or similar component formed by a same or similar method using a same or similar material(s).
Various embodiments are discussed herein in a particular context, namely, for forming a semiconductor structure that includes a fin-like field-effect transistor (FinFET) device. The semiconductor structure, for example, may be a complementary metal-oxide-semiconductor (CMOS) device including a P-type metal-oxide semiconductor (PMOS) FinFET device and an N-type metal oxide semiconductor (NMOS) FinFET device. Embodiments will now be described with respect to particular examples including FinFET manufacturing processes. Embodiments, however, are not limited to the examples provided herein, and the ideas may be implemented in a wide array of embodiments. Thus, various embodiments may be applied to other semiconductor devices/processes, such as planar transistors, and the like. Further, some embodiments discussed herein are discussed in the context of devices formed using a gate-last process. In other embodiments, a gate-first process may be used.
While the figures illustrate various embodiments of a semiconductor device, additional features may be added in the semiconductor device depicted in the Figures and some of the features described below can be replaced, modified, or eliminated in other embodiments of the semiconductor device.
Additional operations can be provided before, during, and/or after the stages described in these embodiments. Some of the stages that are described can be replaced or eliminated for different embodiments. Additional features can be added to the semiconductor device structure. Some of the features described below can be replaced or eliminated for different embodiments. Although some embodiments are discussed with operations performed in a particular order, these operations may be performed in another logical order.
As used herein, a “layer” is a region, such as an area comprising arbitrary boundaries, and does not necessarily comprise a uniform thickness. For example, a layer can be a region comprising at least some variation in thickness.
The present disclosure is generally related to semiconductor devices and the fabrication thereof, and more particularly to multi-gate devices. Multi-gate devices include those transistors whose gate structures are formed on at least two-sides of a channel region. These multi-gate devices may include an n-type metal-oxide-semiconductor device or a p-type metal-oxide-semiconductor multi-gate device. Specific examples herein may be presented and referred to herein as a type of multi-gate transistor referred to as a gate-all-around (GAA) device. A GAA device includes any device that has its gate structure, or portion thereof, formed on 4-sides of a channel region (e.g., surrounding a portion of a channel region). Devices presented herein also include embodiments that have channel regions disposed in nanosheet channel(s), nanowire channel(s), bar-shaped channel(s), and/or other suitable channel configurations. Presented herein are embodiments of devices that may have one or more channel regions (e.g., nanosheets) associated with a single, contiguous gate structure. However, one of ordinary skill would recognize that the teaching can apply to a single channel or any number of channels, such as a FinFET device, on account of its fin-like structure. One of ordinary skill may recognize other examples of semiconductor devices that may benefit from aspects of the present disclosure.
As with the other method embodiments and exemplary devices discussed herein, it is understood that parts of the semiconductor devices may be fabricated by semiconductor technology process flow, and thus some processes are only briefly described herein. Further, the exemplary semiconductor devices may include various other devices and features, such as other types of devices such as additional transistors, bipolar junction transistors, resistors, capacitors, inductors, dials, fuses, and/or other logic devices, etc., but is simplified for better understanding of concepts of the present disclosure. In some embodiments, exemplary devices include a plurality of semiconductor devices (e.g., transistors), including PFETs, NFETs, etc., which may be interconnected. Moreover, it is noted that the process steps of method 100, include any descriptions given with reference to the figures, as with the remainder of the method and exemplary figures provided in this disclosure, are merely exemplary and are not intended to be limiting beyond what is specifically recited in the claims that follow.
At block 102, the example method 100 includes providing a substrate. Referring to the example of
At block 104, the example method 100 then includes forming one or more epitaxial layers over the substrate. Referring to the example of
In some embodiments, the sacrificial epitaxial layer 214 has a thickness ranging from about 4 nm to about 12 nm. The sacrificial epitaxial layers 214 may be substantially uniform in thickness. In some embodiments, the channel epitaxial layer 216 has a thickness ranging from about 3 nm to about 6 nm. In some embodiments, the channel epitaxial layers 216 of the stack are substantially uniform in thickness.
As described in more detail below, the channel epitaxial layer 216 may serve as channel region(s) for a subsequently-formed multi-gate device and its thickness is chosen based on device performance considerations. The sacrificial epitaxial layer 214 may serve to reserve a spacing (or referred to as a gap) between adjacent channel region(s) for a subsequently-formed multi-gate device and its thickness is chosen based on device performance considerations.
By way of example, epitaxial growth of the epitaxial stack 212 may be performed by a molecular beam epitaxy (MBE) process, a metalorganic chemical vapor deposition (MOCVD) process, and/or other suitable epitaxial growth processes. In some embodiments, the epitaxially grown layers, such as the channel epitaxial layers 216, include the same material as the substrate 202, such as silicon (Si). In some embodiments, the epitaxially grown layers 214 and 216 include a different material than the substrate 202. As stated above, in at least some examples, the sacrificial epitaxial layer 214 includes an epitaxially grown Si1-xGex layer (e.g., x is about 25˜55%) and the channel epitaxial layer 216 includes an epitaxially grown Si layer. Alternatively, in some embodiments, either of the sacrificial epitaxial layers 214 and channel epitaxial layers 216 may include other materials such as germanium, a compound semiconductor such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide, an alloy semiconductor such as SiGe, GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, and/or GaInAsP, or combinations thereof. As discussed, the materials of the sacrificial epitaxial layers 214 and channel epitaxial layers 216 may be chosen based on providing differing oxidation and etch selectivity properties. In various embodiments, the epitaxial layers 214 and 216 are substantially dopant-free (i.e., having an extrinsic dopant concentration from about 0 cm−3 to about 1×1017 cm−3), where for example, no intentional doping is performed during the epitaxial growth process.
At block 106, the example method 100 includes patterning the epitaxial stack to form semiconductor fins (also referred to as fins). Referring to the example of
The fins 220 may be fabricated using suitable processes including photolithography and etch processes. The photolithography process may include forming a photoresist layer over the substrate 202 (e.g., over the epitaxial stack 212), exposing the resist to a pattern, performing post-exposure bake processes, and developing the resist to form a masking element including the resist. In some embodiments, pattering the resist to form the masking element may be performed using an electron beam (e-beam) lithography process. The masking element may then be used to protect regions of the substrate 202, and epitaxial stack 212 formed thereupon, while an etch process forms trenches in unprotected regions through masking layer(s) such as hard mask, thereby leaving the plurality of extending fins. The trenches may be etched using a dry etch (e.g., reactive ion etching), a wet etch, and/or other suitable processes. The trenches may be filled with dielectric material forming, for example, shallow trench isolation features interposing the fins.
At block 108, the example method includes performing tuning operations to keep a width of the sacrificial epitaxial layer in the fins not greater than a width of the channel epitaxial layer in the fins. In various embodiments, this is accomplished by performing tuning operations that prevent the sacrificial epitaxial layer in the fins from expanding beyond a width of the channel epitaxial layer in the fins during operations to form isolation features between the plurality of fins. In one example, performing tuning operations includes etching the sidewalls of sacrificial epitaxial layers (e.g., nano sheet reverse etching) to allow for expansion of the sacrificial epitaxial layers during subsequent STI forming operations. In various embodiments, the sacrificial epitaxial layers are formed from SiGe and the etching the sidewalls of sacrificial epitaxial layers comprises SiGe etching. In various embodiments, the SiGe etching can be performed as a plasma etch in a plasma etching chamber with an etch gas of CH4/CHF3/HBr/Cl2/H2, etc.; a passivation gas for selectivity of N2/O2, etc.; a dilute gas of He/Ar/N2, etc.; at a power of approximately 10 W to approximately 4000 W; at a pressure of approximately 1 mTorr to approximately 800 mTorr; and with a gas Flow of approximately 20 sccm to approximately 3000 sccm. Referring to the example of
In another example, performing tuning operations includes adjusting the temperatures used during heat treatment to form STI layers to keep a width of the sacrificial epitaxial layer not greater than a width of the channel epitaxial layer. In various embodiments, adjusting the temperatures used during heat treatment prevents the width of the sacrificial epitaxial layers from expanding beyond the width of the channel epitaxial layers during heat treatment.
At block 110, the example method 100 includes forming STI features on the substrate. In various embodiments, the STI features are formed by filling trenches between adjacent fins with a dielectric material to form an isolation feature. Referring to the example of
The isolation feature 222 may include one or more dielectric layers. Suitable dielectric materials for the isolation feature 222 may include silicon oxides, silicon nitrides, silicon carbides, fluorosilicate glass (FSG), low-K dielectric materials, and/or other suitable dielectric materials. The dielectric material may be deposited by any suitable technique including thermal growth, CVD, HDP-CVD, PVD, ALD, and/or spin-on techniques. The deposited isolation features 222 are subsequently recessed to form shallow trench isolation (STI) features (also denoted as STI features 222). In the illustrated embodiment, the STI features 222 are disposed on sidewalls of the protruding portion of the substrate 202. A top surface of the STI feature 222 may be coplanar with a bottom surface of the epitaxial stack 212 or lower than the bottom surface of the epitaxial stack 212 for about 1 nm to about 10 nm. Any suitable etching technique may be used to recess the isolation features 222 including dry etching, wet etching, RIE, and/or other etching methods, and in an exemplary embodiment, an anisotropic dry etching is used to selectively remove the dielectric material of the isolation features 222 without etching the fins 220.
At block 112, the example method 100 includes forming sacrificial layers/features over the substrate. Referring to the example of
At block 114, the example method 100 includes patterning the sacrificial layers/features to form a dummy gate structure on channel regions of the fins. Referring to the example of
The sacrificial gate structure 224 is subsequently removed as discussed with reference to block 126 of the method 100 and will be replaced by a final gate stack at a subsequent processing stage of the device 200. In particular, the sacrificial gate structure 224 is replaced at a later processing stage by a high-K dielectric layer (HK) and metal gate electrode (MG) as discussed below.
At block 116, the example method 100 includes forming gate sidewall spacers on sidewalls of the dummy gate stack. Referring to the example of
At block 118, the example method includes recessing the fins in the source drain/regions. The stacked epitaxial layers 214 and 216 are etched down at the S/D regions to form a recess 234. A top portion of the substrate 202 is also etched. In various embodiments, the recessing is performed by a suitable etching process, such as a dry etching process, a wet etching process, or an RIE process. Dry etching may be implemented using an etchant including a bromine-containing gas (e.g., HBr and/or CHBR3), a fluorine-containing gas (e.g., CF4, SF6, CH2F2, CHF3, and/or C2F6), other suitable gases, or combinations thereof. Referring to the example of
At block 120, the example method 100 Includes forming inner spacers. Forming inner spacers include recessing sacrificial epitaxial layers (e.g., SiGe), depositing inner spacer material, and etching back inner spacer material.
At block 122, the example method 100 includes forming source/drain (S/D) features. Referring to the example of
At block 124, the example method 100 includes forming CESL and ILD layers. Referring to the example of
At block 126, the example method 100 includes removing the dummy gate stack to form a gate trench. Referring to the example of
At block 128, the example method 100 includes removing the sacrificial epitaxial layers to form nanosheets. Referring to the example of
At block 130, the example method 100 includes forming high-K metal gate structures. Referring to the example of
At block 132, the example method 100 includes performing further fabrication. A semiconductor device may undergo further processing to form various features and regions known in the art. For example, subsequent processing may form contact openings, contact metal, as well as various contacts/vias/lines and multilayer interconnect features (e.g., metal layers and interlayer dielectrics) on the substrate, configured to connect the various features to form a functional circuit that may include one or more multi-gate devices. In furtherance of the example, a multilayer interconnection may include vertical interconnects, such as vias or contacts, and horizontal interconnects, such as metal lines. The various interconnection features may employ various conductive materials including copper, tungsten, and/or silicide. In one example, a damascene and/or dual damascene process is used to form a copper related multilayer interconnection structure. Moreover, additional process steps may be implemented before, during, and after the method 100, and some process steps described above may be replaced or eliminated in accordance with various embodiments of the method 100.
In the alternative plane view 406, the gate spacer 410 and the inner spacer 412 may form with a first gap S1, a second gap S2, a first critical dimension stop layer CD1, and a second critical dimension stop layer CD2. The first gap S1 and second gap S2 depict gaps that may form between the gate spacer 410 and the inner spacer 412 during fabrication. The first critical dimension stop layer CD1 and the second critical dimension stop layer CD2 depict gaps that may form between the S/D region 414 and the metal gate 416. The alternative plane view 406 also includes areas 418, 419 where EPI damage may occur due to the dimensions of the first gap S1, second gap S2, first critical dimension CD1, and second critical dimension CD2. In this example, S1 and S2 are too large and the critical dimension of the stop layers CD1 and CD2 are too small. Short circuits between the metal drain in S/D region 414 and the metal gate 416 may occur in the areas 418, 419 due to insufficient separation provided by the gate spacer 410 and inner spacer 412.
In the first plane view 404, the gate spacer 410 and the inner spacer 412 may form with a third gap S3, a fourth gap S4, a third critical dimension stop layer CD3, and a fourth critical dimension stop layer CD4. The third gap S3 and fourth gap S4 depict gaps that may form between the gate spacer 410 and the inner spacer 412 during fabrication. The third critical dimension stop layer CD3 and the fourth critical dimension stop layer CD4 depict gaps that may form between the S/D region 414 and the metal gate 416. The first plane view 404 does not include areas where EPI damage may occur due to the dimensions of the third gap S3, fourth gap S4, third critical dimension CD3, and fourth critical dimension CD4. In this example, S3, S4, CD3, and CD4 are sufficient. Short circuits between the metal drain in the S/D region 414 and the metal gate 416 should not occur (e.g., probability of occurrence is close to 0%) because the gate spacer 410 and inner spacer 412 provide sufficient separation. The third gap S3 and fourth gap S4 between the gate spacer 410 and the inner spacer 412 are small enough to prevent a short circuit between the metal gate 416 and the metal drain in the S/D region 414. The third critical dimension stop layer CD3 and the fourth critical dimension stop layer CD4 formed by the gate spacer 410 and the inner spacer 412 is large enough to prevent a short circuit between the metal gate 416 and the metal drain in the S/D region 414.
In various embodiments, CD3 is equal to or approximately equal to CD4, and both CD3 and CD4 are greater than both CD1 and CD2. In various embodiments, CD1 and CD2 are approximately 0.3 nm (nanometer) to approximately 3 nm, whereas CD3 and CD4 have a thicker block wall of approximately 3 nm to approximately 10 nm.
In various embodiments, S2≥S1 and both (S2 and S1)>S4≥S3. In various embodiments, S1 and S2 are approximately 3 nm to approximately 5 nm. In various embodiments, S3 and S4 are approximately 0.3 to approximately 2 nm.
In various embodiments, a first curvature angle θa′ is defined around a border between the gate spacer 410 and the inner spacer 412 in the first plane view 404, and an alternative curvature angle θa is defined between around a border between the gate spacer 410 and the inner spacer 412 in the alternative plane view 406. In various embodiments, the first curvature angle θa′ is greater than the alternative curvature angle θa.
In various embodiments, for the bottom nanosheet MG position, θa′ is approximately 100° to approximately 120°, whereas θa is approximately 80° to approximately 100°. In various embodiments, for the middle nanosheet MG position, θa′ is approximately 130° to approximately 160°, whereas θa is approximately 100° to approximately 130°. In various embodiments, for the first nanosheet MG position, θa′ is approximately 160° to approximately 180°, whereas ea is approximately 160° to approximately 180°. If the semiconductor device has more than three nanosheets, then θa′ is approximately 160° to approximately 180°, whereas θa is approximately 160° to approximately 180°.
In the example of
In the example of
In the example of
Improved systems, fabrication methods, fabrication techniques, and articles have been described. The described systems, methods, techniques, and articles can be used with a wide range of semiconductor devices including Gate-all-around FET (GAAFET/NSFET)/Fork-sheet/CFET/VFET/MOSFET. The described systems, methods, techniques, and articles can improve the production yield by improving the shape of the operation definition (OD) nano sheet.
A thermal effect from STI formation can affect SiGe used in an epitaxial stack. The described systems, methods, techniques, and articles can compensate for the thermal effect, which can cause dummy gate etch residue, which in turn can lead to metal gate extrusion, epi damage, and shorting between the metal gate and the metal drain. The dummy gate etch residue can be more pronounced at the median or bottom of the dummy gate wherein the lower the channel in a multi-channel device, the worse the gate residue. The described systems, methods, techniques, and articles can tune the manufacturing process so that the OD is smooth and reduce the amount of dummy gate etch residue. The described systems, methods, techniques, and articles can implement nano sheet reverse etching or SiGe thermal control for OD shape change to reduce dummy gate etch residue and prevent shorting between the metal gate and the metal drain.
In some aspects, the techniques described herein relate to a fabrication method, including: forming, on a substrate, an epitaxial stack including at least one sacrificial epitaxial layer and at least one channel epitaxial layer; forming a plurality of fins in the epitaxial stack; performing tuning operations to keep a width of the sacrificial epitaxial layer in the fins not greater than a width of the channel epitaxial layer in the fins; forming a sacrificial gate stack on channel regions of the fins; forming gate sidewall spacers on sidewalls of the sacrificial gate stack; forming inner spacers around the sacrificial epitaxial layer and the channel epitaxial layer in the fins; forming source/drain features; removing the sacrificial gate stack and sacrificial epitaxial layer in the fins; and forming a metal gate to replace the sacrificial gate stack and sacrificial epitaxial layer, wherein the metal gate is shielded from the source/drain features by the gate sidewall spacers and the inner spacers.
In some aspects, the techniques described herein relate to a fabrication method, wherein performing tuning operations includes etching sidewalls of the sacrificial epitaxial layer.
In some aspects, the techniques described herein relate to a fabrication method, further including forming isolation features between the plurality of fins, wherein the width of the sacrificial epitaxial layer does not expand beyond the width of the channel epitaxial layer, and wherein performing tuning operations includes adjusting temperatures used during heat treatment to form the isolation features.
In some aspects, the techniques described herein relate to a fabrication method, wherein forming a sacrificial gate stack on channel regions of the fins includes forming a sacrificial gate stack on channel regions of the fins with a sacrificial gate residue that does not extend beyond 3 nanometers (nm) horizontally in an x-direction or a y-direction.
In some aspects, the techniques described herein relate to a fabrication method, wherein forming the gate spacer and forming the inner spacer include forming the gate spacer and the inner spacer with a gap between the gate spacer and the inner spacer.
In some aspects, the techniques described herein relate to a fabrication method, wherein the gap between the gate spacer and the inner spacer is approximately 0.3 nm to approximately 2 nm.
In some aspects, the techniques described herein relate to a fabrication method, wherein forming the gate spacer and forming the inner spacer include forming the gate spacer and the inner spacer with a critical dimension stop layer formed by the gate spacer and the inner spacer.
In some aspects, the techniques described herein relate to a fabrication method, wherein the critical dimension stop layer provides a block wall of approximately 3 nm to approximately 10 nm.
In some aspects, the techniques described herein relate to a fabrication method, wherein forming the gate spacer and forming the inner spacer include forming the gate spacer and the inner spacer with a curvature angle defined around a border between the gate spacer and the inner spacer that is: approximately 100° to approximately 120° for a bottom nanosheet position; and approximately 130° to approximately 160° for a middle nanosheet position.
In some aspects, the techniques described herein relate to a method of forming a semiconductor device, including: forming, on a substrate, an epitaxial stack including a plurality of sacrificial epitaxial layers and a plurality of channel epitaxial layers; forming a plurality of fins in the epitaxial stack; etching sidewalls of the sacrificial epitaxial layers to keep a width of the sacrificial epitaxial layers in the fins less than a width of the channel epitaxial layers in the fins during operations to form shallow trench isolation (STI) features between the plurality of fins; forming a sacrificial gate stack on channel regions of the fins; forming gate sidewall spacers on sidewalls of the sacrificial gate stack; forming inner spacers around the sacrificial epitaxial layers and the channel epitaxial layers in the fins; forming source/drain features; removing the sacrificial gate stack and sacrificial epitaxial layers in the fins; and forming a metal gate to replace the sacrificial gate stack and sacrificial epitaxial layers, wherein the metal gate is shielded from the source/drain features by the gate sidewall spacers and the inner spacers.
In some aspects, the techniques described herein relate to a method, wherein etching the sidewalls of the sacrificial epitaxial layers includes performing a plasma etch with an etch gas of CH4, CHF3, HBr, Cl2, and/or H2; a passivation gas for selectivity of N2 and/or O2; a dilute gas of He, Ar, and/or N2; at a power of approximately 10 W to approximately 4000 W; at a pressure of approximately 1 mTorr to approximately 800 mTorr; and with a gas Flow of approximately 20 sccm to approximately 3000 sccm.
In some aspects, the techniques described herein relate to a method, wherein forming a sacrificial gate stack on channel regions of the fins includes forming a sacrificial gate stack on channel regions of the fins with a sacrificial gate residue that does not extend beyond 3 nanometers (nm) horizontally in an x-direction or a y-direction.
In some aspects, the techniques described herein relate to a method, wherein forming the gate spacer and forming the inner spacer include forming the gate spacer and the inner spacer with a gap between the gate spacer and the inner spacer that is small enough to prevent a short circuit between the metal gate and a metal drain in the source/drain region.
In some aspects, the techniques described herein relate to a method, wherein forming the gate spacer and forming the inner spacer include forming the gate spacer and the inner spacer with a critical dimension stop layer formed by the gate spacer and the inner spacer that is large enough to prevent a short circuit between the metal gate and a metal drain in the source/drain region.
In some aspects, the techniques described herein relate to a method, wherein forming the gate spacer and forming the inner spacer include forming the gate spacer and the inner spacer with a curvature angle defined around a border between the gate spacer and the inner spacer that is: approximately 100° to approximately 120° for a bottom nanosheet position; and approximately 130° to approximately 160° for a middle nanosheet position.
In some aspects, the techniques described herein relate to a method of forming a semiconductor device, including: forming, on a substrate, an epitaxial stack including a plurality of sacrificial epitaxial layers and a plurality of channel epitaxial layers; forming a plurality of fins in the epitaxial stack; forming isolation features between the plurality of fins while adjusting temperatures used during heat treatment to form the isolation features to prevent a width of the sacrificial epitaxial layers expanding beyond a width of the channel epitaxial layers during isolation features formation; forming a sacrificial gate stack on channel regions of the fins; forming gate sidewall spacers on sidewalls of the sacrificial gate stack; forming inner spacers around the sacrificial epitaxial layers and the channel epitaxial layers in the fins; forming source/drain features; removing the sacrificial gate stack and sacrificial epitaxial layers in the fins; and forming a metal gate to replace the sacrificial gate stack and sacrificial epitaxial layers, wherein the metal gate is shielded from the source/drain features by the gate sidewall spacers and the inner spacers.
In some aspects, the techniques described herein relate to a method, wherein forming a sacrificial gate stack on channel regions of the fins includes forming a sacrificial gate stack on channel regions of the fins with a sacrificial gate residue that does not extend beyond 3 nanometers (nm) horizontally in an x-direction or a y-direction.
In some aspects, the techniques described herein relate to a method, wherein forming the gate spacer and forming the inner spacer include forming the gate spacer and the inner spacer with a gap between the gate spacer and the inner spacer.
In some aspects, the techniques described herein relate to a method, wherein forming the gate spacer and forming the inner spacer include forming the gate spacer and the inner spacer with a critical dimension stop layer formed by the gate spacer and the inner spacer.
In some aspects, the techniques described herein relate to a method, wherein forming the gate spacer and forming the inner spacer include forming the gate spacer and the inner spacer with a curvature angle defined around a border between the gate spacer and the inner spacer that is: approximately 100° to approximately 120° for a bottom nanosheet position; and approximately 130° to approximately 160° for a middle nanosheet position.
While at least one exemplary embodiment has been presented in the foregoing detailed description of the disclosure, it should be appreciated that a vast number of variations exist. It should also be appreciated that the exemplary embodiment or exemplary embodiments are only examples, and are not intended to limit the scope, applicability, or configuration of the disclosure in any way. Rather, the foregoing detailed description will provide those skilled in the art with a convenient road map for implementing an exemplary embodiment of the disclosure. It being understood that various changes may be made in the function and arrangement of elements described in an exemplary embodiment without departing from the scope of the disclosure as set forth in the appended claims.
