Patent Application
20130181288
This application is based upon and claims the benefit of priority of the prior Japanese Patent Application No. 2012-7286, filed on Jan. 17, 2012, the entire contents of which are incorporated herein by reference.
The embodiments discussed herein are related to a semiconductor device and a method for manufacturing a semiconductor device.
Recently, portable telephones and terminal devices, etc. of wireless communication, etc. are required to be further integrated and downsized, and to lower costs.
For this, a semiconductor device having a core unit, an input/output circuit and a high withstand voltage circuit mounted on one and the same semiconductor substrate is noted.
Transistors of the core unit and the input/output circuit unit can be formed by a general CMOS process.
On the other hand, it is preferable that the transistors used in the high withstand voltage circuit ensures high withstand voltage.
Related references are as follows:
Japanese Laid-open Patent Publication No. 2007-49039;
Japanese Laid-open Patent Publication No. Hei 7-161987; and
Japanese Laid-open Patent Publication No. 2011-199153.
According to an aspect of embodiments, a semiconductor device including a first gate electrode formed over a first region of a semiconductor substrate of a first conduction type, where a first transistor is to be formed, with a first gate insulation film formed therebetween; a first source region of the first conduction type formed in the semiconductor substrate on one side of the first gate electrode; a first drain region of the first conduction type formed in the semiconductor substrate on the other side of the first gate electrode; a first channel dope layer of a second conduction type formed in at least a region on a side of the first source region of a first channel region between the first source region and the first drain region, the first channel dope layer having, at a part of the first channel dope layer on a side of the first drain region, a concentration gradient of a concentration of a dopant impurity of the second conduction type, which decrease toward the first drain region; a first well of the second conduction type formed in a region of the first region except a region where the first drain region is to be formed, the first well having, at a part of the first well on a side of the first drain region, a concentration gradient of a concentration of a dopant impurity of the second conduction type, which decrease toward the first drain region; and a second well of the second conduction type formed in the first region, connected to the first well and positioned below the first well.
According to another aspect of embodiments, a method for manufacturing a semiconductor device including: forming a first channel dope layer of a second conduction type in a first region of a semiconductor substrate of a first conduction type, where a first transistor is to be formed, the first channel dope layer being formed in a region except a first prescribed region where a dopant impurity for forming a first drain region of the first transistor is to be implanted so that the first channel dope layer is spaced from the first prescribed region; forming a first well of the second conduction type in a region of the first region except the first prescribed region so that the first well is spaced from the first prescribed region; forming a second well of the second conduction type to be connected to the first well in the first region so that the second well is positioned below the first well; forming a first gate electrode of the first transistor over the semiconductor substrate in the first region with a first gate insulation film formed therebetween; and forming a first source region of the first conduction type of the first transistor in the semiconductor substrate on one side of the first gate electrode, and forming the first drain region of the first conduction type in the first prescribed region of the semiconductor substrate on the other side of the first gate electrode.
The object and advantages of the embodiments will be realized and attained by means of the elements and combinations particularly pointed out in the claims.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are not restrictive of the embodiments, as claimed.
In a case that transistors whose withstand voltages are largely different from each other are mounted on one and the same semiconductor substrate, the increase in the number of processes may be caused.
A method for manufacturing a semiconductor device according to Reference will be described with reference to
On a semiconductor substrate 210, other than high withstand voltage transistor 240, transistor of the core unit, transistor of the input/output circuit, etc. are also formed but are not illustrated here.
First, as illustrated in
Next, as illustrated in
Next, as illustrated in
Then, as illustrated in
Next, a photoresist film 303 is formed on the entire surface by, e.g., spin coating.
Next, by photolithography, the photoresist film 303 is patterned. Thus, an opening 305 for forming a lightly doped drain region 228b of the high withstand voltage transistor 240 is formed in the photoresist film 303 (see
Then, by, e.g., ion implantation with the photoresist film 303 as the mask, an N-type dopant impurity is implanted into the semiconductor substrate 210 to form an N-type lightly doped region 228b. In forming the lightly doped drain region 228b, the lightly doped drain region 228b is so formed that the distance between the end of the lightly doped region 228b and the end of a heavily doped drain region 232b (see
Next, as illustrated in
Then, a gate insulation film 224 is formed on the surface of the semiconductor substrate 210 by thermal oxidation.
Next, a polysilicon film is formed by CVD (Chemical Vapor Deposition).
Next, the polysilicon film is patterned by photolithography to form gate electrodes 226 of polysilicon (see
Next, as illustrated in
Then, an insulation film is formed on the entire surface by CVD.
Next, as illustrated in
Next, as illustrated in
Then, as illustrated in
Next, anneal is made to activate the dopant impurities implanted into semiconductor substrate 210.
A silicide film 238 is formed on the source/drain diffused layers 234a, 234b, the gate electrodes 226 and the contact regions 242, 244.
Thus, the N-channel type high withstand voltage transistor 240 including the gate electrode 226, the source/drain diffused layers 234a, 234b are formed (see
As described above, in the method for manufacturing the semiconductor device according to Reference, the lightly doped drain region 228b of the high withstand voltage transistor 240 is formed by a process different from a process of forming the lightly doped drain regions 228a. (see
However, in the method for manufacturing a semiconductor device according to Reference, the process of forming the lightly doped drain region 228b is made independently of the process of forming the lightly doped drain regions 228a, which increases the manufacturing processes. The increase of the manufacturing processes is a barrier to lowering costs of semiconductor devices.
It is often preferable to form not an N-channel type high withstand voltage transistor but a P-channel type high withstand voltage transistor.
It is also often preferable to form both of the N-channel type high withstand voltage transistor and the P-channel type high withstand voltage transistor.
The inventors of the present application made earnest studies and has got the idea of a semiconductor device and a method for manufacturing the same to be described below.
The semiconductor device according to a first embodiment and its manufacturing method will be describe with reference to
First, the semiconductor device according to the present embodiment will be described with reference to
As illustrated in
In the semiconductor substrate 10 in the N-channel type high withstand voltage transistor-to-beformed-region 2N, a P-type well 14, for example, is formed. In a region other than the region where a lightly doped drain region 28b is to be formed, the P-type well 14 is formed, enclosing the region where the lightly doped drain region 28b is to be formed, and being spaced from the lightly doped drain region 28b. That is, in a region spaced from the region in which a dopant impurity forming the lightly doped drain region 28b is to be implanted, a dopant impurity forming the P-type well 14 is implanted. In other words, in the design data and on the reticle, the region where the lightly doped drain region 28b is to be formed and the region where the P-type well 14 is to be formed are spaced from each other.
The distance L1 (see
Near the border between the N-channel type high withstand voltage transistor-to-be-formed region 2N and the P-channel type high withstand voltage transistor-to-be-formed region 2P, the distance L3 between the edge of the P-type well 14 on the side of the drain 34b and the edge of the N-type well 18 on the side of the drain 34b is, e.g., about 1-1.5 μm. The distance L3 between the edge of the P-type well 14 on the side of the drain 34b and the edge of the N-type well 18 on the side of the drain 34b is set so large to thereby prevent the electrically connecting between the drain 34b and the N-type well 18 due to the thermal diffusion of the dopant impurity.
After dopant impurities forming the P-type well and the lightly doped drain region 28b have been implanted, heat processing for activating the dopant impurities is made. The P-type dopant impurity implanted to form the P-type well 14 is diffused by this heat processing. The N-type dopant impurity implanted to form the lightly doped drain region 28b is also diffused. Accordingly, in the portion of the P-type well 14 on the side of the lightly doped drain region 28b, a concentration gradient of the P-type dopant impurity, which decreases from the P-type well 14 to the lightly doped drain region 28b is present. In the lightly doped drain region 28b, a concentration gradient of the N-type dopant impurity, which decreases from the lightly doped drain region 28b to the P-type well 14 is present. Such diffusion of the dopant impurity might not space the P-type well 14 and the lightly doped drain region 28b from each other. However, with the dopant impurity diffused by such heat processing, blunt impurity profiles are still obtained between the lightly doped drain region 28b and the P-type well 14. Even with the P-type well 14 and the lightly doped drain region 28b not spaced from each other due to the dopant impurity diffusion, the concentration of the electric fields between the lightly doped drain region 28b and the P-type well 14 is sufficiently mitigated, and the withstand voltage can be sufficient. Thus, the P-type well 14 and the lightly doped drain region 28b may not be spaced from each other, and the concentration gradient of the N-type dopant impurity, which decreases from the lightly doped drain region 28b to the P-type well 14 may be present.
In the semiconductor substrate 10 in the high withstand voltage transistor-to-be-formed region 2, an N-type diffused layer 16 is formed, enclosing the side (the outer edge) of the P-type well 14.
In the semiconductor substrate 10 in the high withstand voltage transistor-to-be-formed region 2, an N-type buried diffused layer (Deep-N-type well) 18 is formed in a region deeper than the P-type well 14. The N-type diffused layer 16 and the N-type buried diffused layer 18 are connected to each other. The N-type diffused layer 16 and the N-type buried diffused layer 18 form an N-type well 20.
The edge of the N-type buried diffused layer 18 on the side of the drain diffused layer 34b is sufficiently spaced from the edge of the P-type well 14 on the side of the drain diffused layer 34b. The distance L4 (see
In the semiconductor substrate 10 in the N-channel type high withstand voltage transistor-to-be-formed region 2N, a channel dope layer is formed. In the N-channel type high withstand voltage transistor-to-be-formed region 2N, the channel dope layer 22 is formed, spaced from the region where the lightly doped drain region 28b is to be formed, in the region except the region where the lightly doped drain region 28b is to be formed. That is, the region spaced from the region where the dopant impurity forming the lightly doped drain region 28b is to be implanted, a dopant impurity forming the channel dope layer 22 is implanted. In other words, in the design data and on the reticle the region where the lightly doped drain region 28b is to be formed and the region where the channel dope layer 22 is to be formed are spaced from each other. The channel dope layer 22 is formed in that of the channel region between the source region 34a and the drain region 34b, which is at least on the side of the source region 34a. The distance L5 between the region where the lightly doped drain region 28b is to be formed and the channel dope layer 22 is about, e.g., 100-300 nm. The distance L5 between the region where the lightly doped drain region 28b is to be formed and the channel dope layer 22 is, e.g., about 180 nm.
The channel dope layer 22 is formed, spaced from the lightly doped drain region 28b so that blunt impurity profiles between the lightly doped drain region 28b and the channel dope layer 22 can be obtained. Thus, even when a high voltage is applied to the drain diffused layer 34b of the N-channel type high voltage transistor 40N, the concentration of the electric fields between the lightly doped drain region 28b and the channel dope layer can be sufficiently mitigated, and the withstand voltage can be sufficient.
After the channel dope layer 22 and the lightly doped drain region 28b have been formed, heat processing for activating the dopant impurities is made. This heat processing diffuses the P-type dopant impurity implanted for forming the channel dope layer 22. This heat processing also diffuses the N-type dopant impurity implanted for forming the lightly doped drain region 28b. In the portion of the channel dope layer 22 on the side of the lightly doped drain region 28b, a concentration gradient of the concentration of the P-type dopant impurity declining from the channel dope layer 22 to the lightly doped drain region 28b is present. A concentration gradient of the concentration of the N-type dopant impurity declining from the lightly doped drain region 28b to the channel dope layer 22 is also present. Such diffusion of the dopant impurities might not space the channel dope layer 22 and the lightly doped drain region 28b from each other. However, even with the dopant impurities diffused by such heat processing, the blunt impurity profiles are still present between the lightly doped drain region 28b and the channel dope layer 22. Thus, even when a high voltage is applied to the drain diffused layer 34b of the N-channel type high withstand voltage transistor 40N, the concentration of the electric fields can be sufficiently mitigated between the lightly doped drain region 28b and the channel doped payer 22, and the withstand voltage can be made sufficient. Accordingly, the channel dope layer 22 and the lightly doped drain region 28b may not be spaced from each other, and the concentration gradient of the concentration of the P-type dopant impurity, which decreases from the channel dope layer 22 to the lightly doped drain region 28b may be present.
On the semiconductor substrate 10 in the N-channel type high withstand voltage transistor-to-be-formed region 2N, a gate electrode 26a is formed with the gate insulation film 24 formed therebetween. As the material of the gate electrode 26a, polysilicon, for example, is used.
In the semiconductor substrate 10 on both sides of the gate electrode 26a, N-type lightly doped diffused layers (the extension regions) 28a, 28b are formed.
On the side wall of the gate electrode 26a, a sidewall insulation film (a spacer) 30 is formed.
In the semiconductor substrate 10 on both sides of the gate electrode 26a with the sidewall insulation film 30 formed on, N-type heavily doped diffused layers 32a, 32b are formed. The N-type lightly doped diffused layers 28a, 28b and the N-type heavily doped diffused layers 32a, 32b form the source/drain diffused layers 34a, 34b of the extension source/drain structure or the LDD structure.
Thus, the N-channel type high withstand voltage transistor 40N including the gate electrode 26a and the source/drain diffused layers 34a, 34b is formed.
In the N-channel type high withstand voltage transistor-to-be-formed region 2N, a P-type contact region 42 electrically connected to the P-type well 14 is formed.
In the semiconductor substrate 10 in the P-channel type high withstand voltage transistor-to-be-formed region 2P, an N-type well 16 is formed in the region except the region where the lightly doped drain region 29b is to be formed, enclosing the lightly doped drain region 29b and spaced from the lightly doped region 29b. That is, in the P-channel type high withstand voltage transistor-to-be-formed region 2P, a dopant impurity forming the N-type well 16 is implanted in the region spaced from the region in which a dopant impurity forming the lightly doped drain region 29b is to be implanted. In other words, in the design data and on the reticle, the region where the N-type well 16 of the P-channel type high withstand voltage transistor-to-be-formed region 2P, and the region where the lightly doped drain region 29b is to be formed are spaced from each other.
The above-described N-type diffused layer 16 formed, enclosing the side of the P-type well 16, and the N-type well 16 formed in the P-channel type high withstand voltage transistor-to-be-formed region 2P are integrally formed of one and the same N-type diffused layer.
The distance L6 (see
The N-type well 16 of the P-channel type high withstand voltage transistor-to-be-formed region 2P is formed, spaced from the region where the lightly doped drain region 29b is formed so that blunt impurity profiles can be obtained between the lightly doped drain region 29b and the N-type well 16. Thus, even when a high voltage is applied to the drain 35b of the P-channel type high withstand voltage transistor 40P, the concentration of an electric filed of the transistor 40P on the side of drain 35b can be sufficiently mitigated, and the withstand voltage can be sufficient.
After the dopant impurities forming the N-type well 16 and the lightly doped drain region 29b have been implanted, heat processing for activating the dopant impurities is made. The N-type dopant impurity implanted for forming the N-type well 16 is diffused by this heat processing. The P-type dopant impurity implanted for forming the lightly doped drain region 29b is also diffused. In the part of the N-type well 16 on the side of the lightly doped drain region 29b, a concentration gradient of the concentration of the N-type dopant impurity, which decreases from the the N-type well 16 to the lightly doped drain region 29b is present. The concentration gradient of the concentration of the P-type dopant impurity, which decreases from the lightly doped drain region 29b to the N-type well 16 is present. Such diffusion of the dopant impurity might not space the N-type well 16 and the lightly doped drain region 29b. However, even with the diffusion of the dopant impurity by the heat processing, the blunt impurity profile is still present between the lightly doped drain region 29b and the N-type well 16. Even with the N-type well 16 and the lightly doped drain region 29b not spaced from each other due to the diffusion of the dopant impurities, the concentration of the electric fields between the lightly doped drain region 29b and the N-type well 16 is sufficiently mitigated, and the withstand voltage can be sufficient. Thus, the N-type well 16 and the lightly doped drain region 29b may not be spaced from each other, and the concentration gradient of the concentration of the P-type dopant impurity, which decreases from the lightly doped drain region 29b to the N-type well 16 may be present.
In the semiconductor substrate 10 in the P-channel type high withstand voltage transistor-to-be-formed region 2P, the N-type buried diffused layer (Deep-N-type well) 18 is formed in a region deeper than the N-type well 16. The buried diffused layer 18 is formed, spaced from the lightly doped drain region 29b in the region below the region where the N-type well 16 is formed and also in the region below the lightly doped drain region 29b. The N-type well 16 and the N-type buried diffused layer 18 are connected to each other. The N-type well 16 and the N-type buried diffused layer 18 form the N-type well 20. The part of the semiconductor substrate 10 enclosed by the N-type well 16, and the drain diffused layer 35b of the P-channel type high withstand voltage transistor 40P are electrically isolated from the semiconductor substrate 10 by the N-type well 20. The drain diffused layer 35 is electrically isolated from the semiconductor substrate 10 by the N-type well 18, whereby the P-channel type high withstand voltage transistor 40P can normally operate.
In the semiconductor substrate 10 in the P-channel type high withstand voltage transistor-to-be-formed region 2P, a channel dope layer 23 is formed. In the region except the region where the lightly doped drain region 29b is to be formed, the channel dope layer 23 is formed, spaced from the region where the lightly doped drain region 29b is to be formed. That is, a dopant impurity forming the channel dope layer is implanted in the region spaced from the region where the dopant impurity forming the lightly doped drain region 29b is to be implanted. In other words, in the design data and on the reticle, the region where the lightly doped drain region 29b is to be formed and the region where the channel dope layer 23 is to be formed are spaced from each other. The channel dope layer 23 is formed in the region of the channel region between the source region 35a and the drain region 35b, which is on the side of at least the source region 35a. The distance L9 (see
The channel dope layer 23 is formed, spaced from the lightly doped drain region 29b so that blunt impurity profiles are obtained between the lightly doped drain region 29b and the channel dope layer 23. Thus, even when a high voltage is applied to the drain 35b of the P-channel type high withstand voltage transistor 40P, the concentration of the electric fields can be sufficiently mitigated between the lightly doped drain region 29b and the channel dope layer 23, and the withstand voltage can be made sufficient.
After the channel dope layer 23 and the lightly doped drain region 29b have been formed, heat processing for activating the dopant impurities is made. This heat processing diffuses the N-type dopant impurity implanted for forming the channel dope layer 23. This heat processing also diffuses the P-type dopant impurity implanted for forming the lightly doped drain region 29b. In the part of the channel dope layer 23 on the side of the lightly doped drain region 29b, a concentration gradient of the concentration of the N-type dopant impurity, which decreases from the channel dope layer 23 to the lightly doped drain region 29b is present. In the part of the lightly doped drain region 29b on the side of the channel dope layer 23, a concentration gradient of the concentration of the P-type dopant impurity, which decreases from the lightly doped drain region 29b to the channel dope layer 23 is present. Such diffusion of the dopant impurities might not space the channel dope layer 23 and the lightly doped drain region 29 from each other. However, even with the dopant impurities diffused by such heat processing, blunt impurity profiles can be obtained between the lightly doped drain region 29 and the channel dope layer 23. Thus, even when a high voltage is applied to the drain 35b of the P-channel type high withstand voltage transistor 40P, the concentration of the electric fields can be sufficiently mitigated between the lightly doped drain region 29b and the channel dope layer 23. Thus, the channel dope layer 23 and he lightly doped drain region 29b may not be spaced from each other, and a concentration gradient of the concentration of the N-type dopant impurity, which decreases from the channel dope layer 23 to the lightly doped drain region 29b may be present.
On the semiconductor substrate 10 in the P-channel type high withstand voltage transistor-to-be-formed region 2P, a gate electrode 26b is formed with the gate insulation film 24 formed therebetween. As the material of the gate electrode 26b, polysilicon or others, for example, is used.
In the semiconductor substrate 10 on both sides of the gate electrode 26b, P-type lightly doped diffused layers 29a, 29b are formed.
On the side wall of the gate electrode 26b, the sidewall insulation film 30 is formed.
In the semiconductor substrate 10 on both sides of the gate electrode 26b with the sidewall insulation film 30 formed on, P-type heavily doped diffused layers 33a, 33b are formed. The P-type lightly doped diffused layers 29a, 29b and the P-type heavily doped diffused layers 33a, 33b form the source/drain diffused layers 35a, 35b of the extension source/drain structure or the LDD structure.
Thus, the P-channel type high withstand voltage transistor 40P including the gate electrode 26b and the source/drain diffused layers 35a, 35b is formed.
Around the high withstand voltage transistor-to-be-formed region 2, an N-type contact region (a well tap region) 44 electrically connected to the N-type well 16 is formed. The N-type contact region is formed, enclosing the high withstand voltage transistor-to-be-formed region 2 (see
On the source/drain regions 34a, 34b, 35a, 35b, on the gate electrodes 26a, 26b and on the contact regions 42, 44, a silicide film 38 is formed. The silicide film 38 on the source/drain regions 34a, 34b, 35a, 35b functions as the source/drain electrodes.
On the semiconductor substrate 10 with the transistors 40N, 40P formed on, an inter-layer insulation film 46 of, e.g., an about 400 nm-film thickness silicon oxide film is formed. In the inter-layer insulation film 46, contact holes 48 are formed down to the silicide film 38. In the contact holes 48, conductor plugs 50 are buried. As the material of the conductor plugs 50, tungsten (W), for example, is used.
On the inter-layer insulation film 46 with the conductor plugs 50 buried in, an inter-layer insulation film 52 is formed. In the inter-layer insulation film 52, trenches 54 for interconnections 56 to be buried in are formed. In the trenches 54, interconnections 56 connected to the conductor plugs 50 are buried. As the material of the interconnections 56, copper (Cu), for example, is used.
On the inter-layer insulation film 52 with the interconnections 56 buried in, an inter-layer insulation film 58 is formed. On the inter-layer insulation film 58, an inter-layer insulation film 60 is formed. In the inter-layer insulation film 58, contact holes 62 are formed down to the interconnections 56. In the inter-layer insulation film 60, trenches 64 connected to the contact holes 62 are formed. In the contact holes 62, conductor plugs 66a are formed, and in the trenches 64, interconnection 66b are formed integral with the conductor plugs 66a. As the material of the conductor plugs 66a and the interconnection 66b, Cu, for example, is used.
On the inter-layer insulation film 60 with the interconnections 66b buried in, an inter-layer insulation film 68 is formed. On the inter-layer insulation film 68, an inter-layer insulation film 70 is formed. In the inter-layer insulation film 68, contact hole 72 reached to the interconnections 66b are formed. In the inter-layer insulation film 70, trenches 74 connected to the contact holes 72 are formed. In the contact holes 72, conductor plugs 76a are formed, and in the trenches 74, interconnections 76b are formed integral with the conductor plugs 76b. As the material of the conductor plugs 76a and the interconnections 76b, Cu, for example, is used.
On the inter-layer insulation film 70 with the interconnections 76b buried in, an inter-layer insulation film 78 is formed. On the inter-layer insulation film 78, an inter-layer insulation film 80 is formed. In the inter-layer insulation film 78, contact holes 82 are formed down to the interconnections 76b. In the inter-layer insulation film 80, trenches 84 connected to the contact holes 82 are formed. In the contact holes 82, conductor plugs 86a are formed, and in the trenches 84, interconnections 86b are formed integral with the conductor plugs 86a. As the material of the conductor plugs 86a and the interconnections 86b, Cu, for example, is used.
On the inter-layer insulation film 80 with the interconnections 86b buried in, an inter-layer insulation film 88 is formed. In the inter-layer insulation film 88, contact holes 90 are formed. In the contact holes 90, conductor plugs 92a are formed, and on the inter-layer insulation film 88, interconnections 92b1-92b6 connected to the conductor plugs 92a are formed. As the material of the conductor plugs 92a and the interconnections 92b1-92b6, aluminum (Al), for example, is used.
As illustrated in
The source 34a of the N-channel type high withstand voltage transistor 40N and the body (the P-type well) 14 are electrically connected to the interconnection 92b3 connected to the ground potential Vss.
The source 35aand the body (the N-type well) 20 of the P-channel type high withstand voltage transistor 40P is electrically connected to the interconnection 92b4 connected to the power supply potential Vdd.
The drain 34b of the N-channel type high withstand voltage transistor 40N and the drain 35b of the P-channel type high withstand voltage transistor 40P are electrically connected to the interconnection 92b5 of an output signal Vout.
The N-type well 20 is electrically connected to the interconnection 92b6 connected to the power supply potential Vdd via the contact layer 44.
Thus, the CMOS inverter circuit including the N-channel type high withstand voltage transistor 40N and the P-channel type high withstand voltage transistor 40P is constituted.
Thus, the semiconductor device according to the present embodiment is constituted.
Next, the evaluation result of the semiconductor device according to the present embodiment will be described.
The plots in
The ▪ plots in
The ▴ plots in
The ♦ plots in
In making the measurement of
A illustrated in
As described above, according to the present embodiment, transistors of sufficiently high withstand voltage can be provided.
As in Control 3, in a case that the N-type well 18 is positioned in the region below the drain diffused layer 34b, the drain diffused layer 34b and the N-type well 18 are electrically shorted at the position enclosed by the broken line in
On the other hand, in the present embodiment, in which the N-type well 18 is not positioned in the region below the drain diffused layer 34b, the drain diffused layer 34b and the N-type well 18 are not electrically shorted at the position along the B-C line (see
The drain diffused layer 34b and the N-type well are sufficiently spaced from each other, whereby as illustrated in
At the position enclosed by the broken line in
However, in the present embodiment, the P-type well 14 is present between the drain diffused layer 34b and the N-type well 18, whereby the drain diffused layer 34b and the N-type well 18 are not shorted.
Control 3 in
In Control 3, since blunt impurity profiles are not obtained between the drain diffused layer 34b and the P-type well 14, and accordingly it is difficult that the N-channel type transistor can be of sufficiently high withstand voltage.
Thus, it is preferable to space the edge of the P-type well 14 on the side of the drain diffused layer 34b by some extent from the region where the lightly doped drain region 32b is to be formed.
Between the drain diffused layer 35b and the N-type well 18, a part in which no dopant impurity is implanted, i.e., a part of the semiconductor substrate 10 is present, whereby the drain diffused layer 35b and the N-type well 18 are not electrically shorted.
According to the present embodiment, as illustrated in
In making the measurement of
In
As illustrated in
Thus, for making the leak current sufficiently low, it is preferable that the distances L3, L4 between the edge of the P-type well 14 on the side of the drain diffused layer 34b and the edge of the N-type well 18 on the side of the drain diffused layer 34b is 1 μm or above.
As described above, in the present embodiment, the channel dope layer 23 and the N-type well 16 are formed in the region spaced from the region where the lightly doped drain region 29b is to be formed. Thus, in the present embodiment, blunt impurity profiles can be obtained between the channel dope layer 23 and the lightly doped drain region 29b and between the lightly doped drain region 29b and the N-type well 16. Consequently, according to the present embodiment, even when a high voltage is applied to the drain diffused layer 35b, the concentration of an electric filed can be sufficiently mitigated, and the withstand voltage can be made sufficient. Because of the N-type well 18 buried in the region below the drain region 35b, the drain region 35b can be electrically isolated from the semiconductor substrate 10, and the P-channel type transistor 40P can be obtained. Furthermore, according to the present embodiment, the lightly doped drain region 29b and the lightly doped source region 29a are formed in the same process. The lightly doped drain region 29b is not formed in a process different from a process of forming the lightly doped source region 29a, which can suppress the number of processes. Thus, according to the present embodiment, the semiconductor device can include required conduction type high withstand voltage transistors while suppressing the number of manufacturing processes.
In the present embodiment, the channel dope layer 23 is formed in the region spaced from the region where the lightly doped drain region 29b is to be formed, whereby the high withstand voltage transistor 40P whose on resistance is low can be obtained. Thus, according to the present embodiment, the semiconductor device can include high withstand voltage transistors of good electric characteristics.
Next, the method for manufacturing the semiconductor device according to the present embodiment will be described with reference to
First, as illustrated in
Next, on the entire surface, a photoresist film 94 is formed by, e.g., spin coating.
Then, the photoresist film 94 is patterned by photolithography. Thus, the openings 96 for forming the P-type well 14 are formed in the photoresist film 94 (see
Then, by, e.g., ion implantation with the photoresist film 94 as the mask, a P-type dopant impurity is implanted into the semiconductor substrate 10 to form the P-type well 14. When the P-type dopant impurity is implanted, the P-type dopant impurity is so implanted that the edge of the device isolation region 12 on the side of the drain diffused layer 34b (see
Then, the photoresist film 94 is released by, e.g., asking.
Next, on the entire surface, a photoresist film 98 is formed by, e.g., spin coating.
Then, the photoresist film 98 is patterned by photolithography. Thus, openings 100 for forming the N-type diffused layer (the N-type well) 16 are formed in the photoresist film 98 (see
Next, by, e.g., ion implantation with the photoresist film 98 as the mask, an N-type dopant impurity is implanted into the semiconductor substrate 10 to form the N-type diffused layer (the N-type well) 16. When the N-type dopant impurity is implanted, the N-type dopant impurity is so implanted that the distance L7 between the edge of the device isolation region 12 contacting the drain diffused layer 35b (see
Then, the photoresist film 98 is released by, e.g., asking.
Next, a photoresist film 102 is formed on the entire surface by, e.g., spin coating.
Next, the photoresist film 102 is patterned by photolithography. Thus, an opening 104 for forming the channel dope layer 22 is formed in the photoresist film 102 (see
Then, by, e.g., ion implantation with the photoresist film 102 as the mask, a P-type dopant impurity is implanted into the semiconductor substrate 10 to form the channel dope layer 22. As the P-type dopant impurity, B, for example, is used. The acceleration energy is, e.g., 20-40 keV. The dose is about 2×1012-5×1012 cm−2. Thus, the channel dope layer 22 is formed. The channel dope layer 22 in the N-channel type high withstand voltage transistor to-be-formed region 40N is formed, spaced from the region where the lightly doped drain region 28b is to be formed. That is, the channel dope layer 22 is formed, spaced from the region where the dopant impurity for forming the lightly doped drain region 28b is to be implanted.
Then, the photoresist film 102 is released by, e.g., asking.
Next, a photoresist film 106 is formed on the entire surface by, e.g., spin coating.
Next, the photoresist film 106 is patterned by photolithography. Thus, an opening 108 for forming the channel dope layer 23 is formed in the photoresist film 106 (see
Then, by, e.g., ion implantation with the photoresist film 106 as the mask, an N-type dopant impurity is implanted into the semiconductor substrate 10 to form the channel dope layer 23. As the N-type dopant impurity, arsenic (As), for example, is used. The acceleration energy is, e.g., about 100-200 keV. The dose is about 1×1013-5×1013 cm−2. Thus, the channel dope layer 23 is formed. The channel dope layer 23 of the P-channel type high withstand voltage transistor-to-be-formed region 40P is formed, spaced from the lightly doped drain region 29b (see
Then, the photoresist film 106 is released by, e.g., asking.
Next, a photoresist film 110 is formed on the entire surface by, e.g., spin coating.
Next, the photoresist film 110 is patterned by photolithography. Thus, openings 112 for forming the N-type buried diffused layers 18 are formed in the photoresist film 110 (see
Then, by, e.g., ion implantation with the photoresist film 110 as the mask, an N-type dopant impurity is implanted into the semiconductor substrate 10 to form the N-type buried diffused layer 18. When the N-type dopant impurity is implanted, the N-type dopant impurity is so implanted that the distances L3, L4 between the edge of the P-type well 14 on the side of the drain 34b and between the edge of the N-type well 18 on the side of the drain 34b is, e.g., about 1-1.5 μm. As the N-type dopant impurity, P, for example, is used. The acceleration energy is, e.g., about 700-900 keV. The dose is about 1×1013-5×1013 cm−2. Thus, the N-type buried layer 18 is formed. The N-type buried layer 18 is positioned below the N-type diffused layer 16. The N-type buried diffused layer 18 and the N-type diffused layer 16 are connected to each other. The N-type diffused layer 16 and the N-type buried diffused layer 18 form the N-type well 20. In the N-channel type high withstand voltage transistor-to-be-formed region 2N, the N-type buried diffused layer 18 is formed so that the edge of the N-type buried diffused layer 18 on the side of the drain diffused layer 34b is spaced from the edge of the P-type well 14 on eh side of the drain diffused layer 34b. In the P-channel type high withstand voltage transistor-to-be-formed region 2P, the part of the semiconductor substrate 10, which is enclosed by the N-type diffused layer 16 is electrically isolated from the semiconductor substrate 10 by the N-type well 20.
Then, the photoresist film 110 is released by, e.g., ashing.
Next, the gate insulation film 24 of, e.g., a 6 nm-film thickness silicon oxide film is formed on the surface of the semiconductor substrate 10 by, e.g., thermal oxidation.
Next, a polysilicon film of, e.g., a 100-150 nm film thickness is formed by, e.g., CVD.
Then, the polysilicon film is patterned by photolithography to form the gate electrodes 26a, 26b of polysilicon (see
Next, a photoresist film 114 is formed on the entire surface by, e.g., spin coating.
Next, the photoresist film 114 is patterned by photolithography. Thus, an opening 116 for exposing the N-channel type high withstand voltage transistor-to-be-formed region 2N is formed in the photoresist film 14 (see
Next, by, e.g., ion implantation with the photoresist film 114 as the mask, an N-type dopant impurity is implanted into the semiconductor substrate 10 to form the N-type lightly doped diffused layers (the extension regions) 28a, 28b. As the N-type dopant impurity, P, for example, is used. The acceleration energy is, e.g., about 20-40 keV. The dose is 2×1013-5×1013 cm−2. Thus, the N-type lightly doped diffused layers 28a, 28b are formed.
Then, the photoresist film 114 is released by, e.g., ashing.
Then, a photoresist film 118 is formed on the entire surface by, e.g., spin coating.
Next, the photoresist film 118 is patterned by photolithography. Thus, an opening 120 for exposing the P-channel type high withstand voltage transistor-to-be-formed region 2P is formed in the photoresist film 118 (see
Next, by, e.g., ion implantation with the photoresist film 118 as the mask, a P-type dopant impurity is implanted into the semiconductor substrate 10 to form the P-type lightly doped diffused layers (the extension regions) 29a, 29b. As the P-type dopant impurity, boron fluoride, for example, is used. The acceleration energy is, e.g., about 10-30 keV. The dose is about 2×1013-5×1013 cm−2. Thus, the P-type lightly doped diffused layers 29a, 29b are formed.
Then, the photoresist film 118 is released by, e.g., asking.
Next, a silicon oxide film of, e.g., a 100 nm-film thickness is formed on the entire surface by, e.g., CVD.
Then, the silicon oxide film is anisotropically etched to form the sidewall insulation film 30 of the silicon oxide film on the side walls of the gate electrodes 26a, 26b (see
Next, a photoresist film 122 is formed on the entire surface by, e.g., spin coating.
Then, the photoresist film 122 is patterned by photolithography. Thus, openings 124 for respectively exposing the N-channel type high withstand voltage transistor-to-be-formed region 2N and the region where the N-type contact region 44 is to be formed are formed in the photoresist film 122 (see
Next, by, e.g., ion implantation with the photoresist film 122 as the mask, an N-type dopant impurity is implanted into the semiconductor substrate 10 to from the N-type heavily doped diffused layers 32a, 32b and the N-type contact region 44. As the N-type dopant impurity, P, for example, is used. The acceleration energy is, e.g., about 8-10 keV. The dose is about 5×1015-8×1015 cm−2. Thus, the N-type heavily doped diffused layers 32a, 32b and the N-type contact region 44 are formed. The lightly doped diffused layers 28a, 28b and the heavily doped diffused layers 32a, 32b form the source/drain diffused layers 34a, 34b of the extension source/drain structure or the LDD structure.
Then, the photoresist film 122 is released by, e.g., ashing.
Next, a photoresist film 126 is formed on the entire surface by, e.g., spin coating.
Next, the photoresist film 126 is patterned by photolithography. Thus, openings 128 for respectively exposing the P-channel type high withstand voltage transistor-to-be-formed region 2P and a P-type contact region 42 are formed in the photoresist film 126 (see
Then, by, e.g., ion implantation with the photoresist film 126 as the mask, a P-type dopant impurity is implanted into the semiconductor substrate 10 to form the P-type heavily doped diffused layers 33a, 33b and the P-type contact region 42. As the P-type dopant impurity, B (boron), for example, is used. The acceleration energy is, e.g., about 4-10 keV. The dose is about 4×1015-6×1015 cm−2. Thus, the P-type heavily doped diffused layers 33a, 33b and the N-type contact region 42 are formed. The lightly doped diffused layers 29a, 29b and the heavily doped diffused layers 33a, 33b form the source/drain diffused layers 35a, 35b of the extension source/drain structure or the LDD structure.
Then, the photoresist film 120 is released by, e.g., ashing.
Next, anneal (heat processing) for activating the dopant impurities implanted into the semiconductor substrate 10 is made. The heat processing temperature is, e.g., about 1000° C. The heat processing period of time is, e.g., about 1 second.
Next, a refractory metal film of, e.g., a 20-50 nm-film thickness cobalt film or nickel film is formed on the entire surface.
Then, heat processing is made to react the silicon atoms in the semiconductor substrate 10 and the metal atoms in the refractory metal film with each other while reacting the silicon atoms in the gate electrodes 26a, 26b and the metal atoms in the refractory metal film with each other. Then, the unreacted refractory metal film is removed. Thus, the silicide film 38 of, e.g., cobalt silicide or nickel silicide is formed on the source/drain diffused layers 34a, 34b, 35a, 35b, on the gate electrodes 26a, 26b and on the contact regions 42, (see
Next, the inter-layer insulation film 46 of, e.g., a 400 nm-film thickness silicon oxide film is formed on the entire surface by, e.g., CVD (see
Next, by photolithography, the contact holes 48 are formed in the inter-layer insulation film 46 respectively down to the silicide film 38.
Next, a 10-20 nm-film thickness Ti film and a 10-20 nm-film thickness TiN film are sequentially stacked on the entire surface by, e.g., sputtering to form the barrier film (not illustrated).
Next, a tungsten film of, e.g., a 300 nm-film thickness is formed by, e.g., CVD.
Next, the tungsten film is polished by, e.g., CMP (Chemical Mechanical Polishing) until the surface of the inter-layer insulation film 46 is exposed. Thus, the conductor plugs 50 of, e.g. tungsten are buried in the contact holes 48.
Then, the inter-layer insulation film 52 of, e.g., a 600 nm-film thickness silicon oxide film is formed on the entire surface by, e.g., CVD.
Next, the trenches 54 for the interconnections 56 to be buried are formed in the inter-layer insulation film 52 by photolithography.
Next, a Cu film, for example, is formed by, e.g., electroplating.
Then, the Cu film is polished by, e.g., CMP until the surface of the inter-layer insulation film 52 is exposed. Thus, the interconnections 56 of Cu are buried in the trenches 54.
Then, the inter-layer insulation film 58 is formed on the entire surface by, e.g., CVD.
Next, the inter-layer insulation film 60 is formed on the entire surface by, e.g., CVD.
Next, the contact holes 62 are formed in the inter-layer insulation film 58 down to the interconnections 56 by photolithography while the trenches 64 are formed in the inter-layer insulation film 60, connected to the contact holes 62.
Next, a Cu film, for example, is formed by, e.g., electroplating.
Then, the Cu film is polished by, e.g., CMP until the surface of the inter-layer insulation film 60 is exposed. Thus, the conductor plugs 66a of Cu are buried in the contact holes 62 while the interconnections 66b of Cu are buried in the trenches 64.
Next, the inter-layer insulation film 68 is formed on the entire surface by, e.g., CVD.
Next, the inter-layer insulation film 70 is formed on the entire surface by, e.g., CVD.
Then, by photolithography, the contact holes 72 down to the interconnections 66b are formed in the inter-layer insulation film 68 while the trenches 74 connected to the contact holes 72 are formed in the inter-layer insulation film 70.
Next, a Cu film for example, is formed by, e.g., electroplating.
Then, the Cu film is polished by, e.g., CMP until the surface of the inter-layer insulation film 70 is exposed. Thus, the conductor plugs 76a of Cu are buried in the contact holes 72 while the interconnections 76b of Cu are buried in the trenches 74.
Next, the inter-layer insulation film 78 is formed on the entire surface by, e.g., CVD.
Next, the inter-layer insulation film 80 is formed on the entire surface by, e.g., CVD.
Next, by photolithography, the contact holes 82 down to the interconnections 76b are formed in the inter-layer insulation film 78 while the trenches 84 connected to the contact holes 82 are formed in the inter-layer insulation film 80.
Next, a Cu film, for example, is formed by, e.g., electroplating.
Then, the Cu film is polished by, e.g., CMP until the surface of the inter-layer insulation film 80 is exposed. Thus, the conductor plugs 86a of Cu are buried in the contact holes 82 while the interconnections 86b of Cu are buried in the trenches 84 (see
Next, the inter-layer insulation film 88 of, e.g., an 800 nm-film thickness silicon oxide film is formed on the entire surface by, e.g., CVD.
Next, by photolithography, the contact holes 90 down to the interconnections 86b are formed in the inter-layer insulation film 88.
Next, an Al film, for example, is formed by, e.g., sputtering.
Then, the Al film is patterned by photolithography. Thus, the conductor plugs 92a of Al are buried in the contact holes 90 while the interconnections 92b1-92b6 of Al connected to the conductor plugs 92a are formed.
Thus, the semiconductor device according to the present embodiment is manufactured (see
As described above, in the present embodiment, the channel dope layers 22, 23 are formed, spaced from the regions where the dopant impurity for forming the lightly doped drain regions 28b, 29b is to be implanted, whereby the impurity profiles on the sides of the drains 34, 35 are blunt. Accordingly, in the present embodiment, the discrete processes of forming the lightly doped source regions 28a, 29a and forming the lightly doped drain regions 28b, 29b are not necessary. That is, the discrete photoresist films for forming the lightly doped drain regions 28b, 29b and forming the lightly doped source regions 28a, 29a are not necessary. Thus, according to the present embodiment, the high withstand voltage transistors 40N, 40P can be formed with the manufacturing processes simplified.
Next, the semiconductor device according to a modification of the present embodiment will be described with reference to
The semiconductor device according to the present modification comprises an ESD (Electro-Static Discharge) protection circuit including an N-channel type high withstand voltage transistor 40N and the P-channel type high withstand voltage transistor 40P.
As illustrated in
The gate electrode 26p of the P-channel type high withstand voltage transistor 40P, the source 35aof the P-channel type high withstand voltage transistor 40P and the body (the N-type well) 20 are electrically connected to the interconnection 92b9 which is to be connected to the power supply potential Vdd.
The gate electrode 26a of the N-channel type high withstand voltage transistor 40N, the source 34a of the N-channel type high withstand voltage transistor 40N and the body (the P-type well) 14 are electrically connected to the interconnection 92b8 which is to be connected to the ground potential Vss.
The drain 34b of the N-channel type high withstand voltage transistor 40N and the drain 35b of the P-channel type high withstand voltage transistor 40P are connected to an internal circuit 4.
Thus, the ESD protection circuit including the N-channel type high withstand voltage transistor 40N and the P-channel type high withstand voltage transistor 40P is constituted.
Thus, the semiconductor device according to the present embodiment is constituted.
As described above, the ESD protection circuit may be formed by using the N-channel type high withstand voltage transistor 40N and the P-channel type high withstand voltage transistor 40P.
The semiconductor device according to a second embodiment and its manufacturing method will be described with reference to
First, the semiconductor device according to the present embodiment will be described with reference to
In the present embodiment according to the present embodiment, the distances L10, L11 between the gate electrodes 26a, 26b and the heavily doped drain regions 32b, 33b are set sufficiently large.
As illustrated in
On the side wall of the gate electrode 26a on the side of the source diffused layer (the source region) 34a, the sidewall insulation film (the spacer) 30 is formed. On the other hand, on the part containing the side wall of the gate electrode 26a on the side of the drain diffused layer (the drain region) 34b, a spacer 30a is formed. The spacer 30a is formed, covering the side wall of the gate electrode 26a and also a part of the lightly doped drain region 28b. The spacer 30a functions as the mask (the implantation block) to prevent the implantation of a dopant impurity when the heavily doped drain region 32b is formed. When the silicide film 38 is formed, the spacer 30a functions as the mask (the silicide block) for preventing the silicidation.
In the semiconductor substrate 10 on both sides of the gate electrode 26a with the sidewall insulation film 30 and the spacer 30a formed on, the N-type heavily doped diffused layers 32a, 32b are formed. The distance L10 between the gate electrode 26a and the N-type heavily doped diffused drain region 32b is, e.g., about 180 nm. The N-type lightly doped diffused layers 28a, 28b and the N-type heavily doped diffused layers 32a, 32b form the source/drain diffused layers 34a, 34b of the extension source/drain structure or the LDD structure. In the present embodiment, the distance L10 between the gate electrode 26a and the heavily doped drain region 32b is set longer than the distance between the gate electrode 26a and the heavily doped source region 32a. The distance L10 between the gate electrode 26a and the heavily doped drain region 32b is set relatively large so that the impurity profile on the side of the drain 34b can be sufficiently blunt, and the withstand voltage can be sufficient.
Thus, the N-channel type high withstand voltage transistor 40a including the gate electrode 26a and the source/drain diffused layers 34a, 34b is constituted.
In the semiconductor substrate 10 on both sides of the gate electrode 26b, the P-type lightly doped diffused layers 29a, 29b are formed.
On the side wall of the gate electrode 26b on the side of the source diffused layer 35a, the sidewall insulation film 30 is formed. On the other hand, on the part containing the side wall of the gate electrode 26b on the side of the drain diffused layer 35b, the spacer 30a is formed. The spacer 30a is formed, covering the side wall of the gate electrode 26b and also a part of the lightly doped drain region 29b.
In the semiconductor substrate 10 on both sides of the gate electrode 26b with the sidewall insulation film 30 and the spacer 30a formed on, the P-type heavily doped diffused layers 33a, 33b are formed. The distance L11 between the gate electrode 26b and the P-type heavily doled drain region 33b is, e.g., about 180 nm. The P-type lightly doped diffused layers 29a, 29b and the P-type heavily doped diffused layers 33a, 33b form the source/drain diffused layers 35a, 35b of the extension source/drain structure or the LDD structure. In the present embodiment, the distance L11 between the gate electrode 26b and the heavily doped drain region 33b is set larger than the distance between the gate electrode 26b and the heavily doped drain region 33b. The distance L11 between the gate electrode 26b and the heavily doped drain region 33b is set relatively large so that the impurity profile on the side of the drain 35b can be blunt, and the withstand voltage can be sufficient.
Thus, the P-channel type high withstand voltage transistor 40b including the gate electrode 26b and the source/drain diffused layers 35a, 35b are constituted.
Next, the evaluation result of the semiconductor device according to the present embodiment will be described with reference to
The 0 plots in
The Δ plots in
As illustrated in
Thus, according to the present embodiment, the semiconductor device can include channel high withstand voltage transistors of higher withstand voltage.
As described above, the distance L10, L11 between the gate electrodes 26a 26b and the heavily doped drain regions 32b, 33b may be set sufficiently large. According to the present embodiment, the impurity profiles on the sides of the drains 34b, 35b can be made blunt, and consequently, the withstand voltage can be higher.
Next, the method for manufacturing the semiconductor device according to the present embodiment will be described with reference to
First, the step of forming the device isolation regions to the step of forming the lightly doped diffused layers 29a, 29b are the same as those of the method for manufacturing the semiconductor device according to the first embodiment described above with reference to
Next, a silicon oxide film of, e.g., a 100 nm-film thickness is formed on the entire surface by, e.g., CVD.
Next, a photoresist film 130 is formed on the entire surface by, e.g., spin coating.
Then, the photoresist film 130 is patterned by photolithography. Thus, the photoresist film 130 for forming the spacer 30a is formed (see
Then, with the photoresist film 130 as the mask, the silicon oxide film is etched. Thus, the sidewall insulation film 30 of silicon oxide film is formed on the side walls of the gate electrodes 26a, 26b on the side of the lightly doped source regions 28a, 29a. The spacer 30a of silicon oxide film is formed on the parts containing the side walls of the gate electrodes 26a, 26b on the side of the lightly doped drain regions 28b, 29b. The spacer 30a functions as the mask (the implantation block) for preventing the implantation of dopant impurities. The spacer 30a functions as the mask (the silicide block) for preventing the silcidation when the silicide film 38 is formed. Accordingly, the spacer 30a is formed on the side walls of the gate electrodes 26a, 26b and also parts of the lightly doped drain regions 28b, 29b. The distances L10, L11 between the gate electrodes 26a, 26b and the edges of the spacer 30a are, e.g., about 180 nm.
Next, a photoresist film 132 is formed on the entire surface by, e.g., spin coating.
Then, the photoresist film 132 is patterned by photolithography. Thus, the openings 134 for respectively exposing the N-channel type high withstand voltage transistor-to-be-formed region 2N and the region where the N-type contact regions (the well tap regions) 44 is to be formed are formed in the photoresist film 132 (see
Then, by, e.g., ion implantation with the photoresist film 132, the gate electrode 26a, the sidewall insulation film 30 and the spacer 30a as the mask, an N-type dopant impurity is implanted into the semiconductor substrate 10. Thus, the N-type heavily doped diffused layers 32a, 32b and the N-type contact regions 44 are formed. The N-type drain region 32b is formed, sufficiently spaced from the gate electrode 26a. The distance L10 between the gate electrode 26a and the heavily doped drain region 32b is set larger than the distance between the gate electrode 26a and the heavily doped source region 32a. The lightly doped diffused layers 28a, 28b and the heavily doped diffused layers 32a, 32b form the source/drain diffused layers 34a, 34b of the extension source/drain structure or the LDD structure.
Then, the photoresist film 132 is released by, e.g., asking.
Next, a photoresist film 136 is formed on the entire surface by, e.g., spin coating.
Next, the photoresist film 136 is patterned by photolithography. Thus, the openings 138 for respectively exposing the P-channel type high withstand voltage transistor-to-be-formed region 2P and the region where the P-type contact region (the well tap region) 42 is to be formed is formed in the photoresist film 136 (see
Next, by, e.g., ion implantation with the photoresist film 136, the gate electrode 26b, the sidewall insulation film 30 and the spacer 30a as a mask, a P-type dopant impurity is implanted into the semiconductor substrate 10. Thus, the P-type heavily doped diffused layers 33a, 33b and the P-type contact region 42 are formed. The P-type drain region 33b is formed, sufficiently spaced from the gate electrode 26b. The distance L11 between the gate electrode 26b and the heavily doped drain region 33b is set larger than the distance between the gate electrode 26b and the heavily doped source region 33a. The lightly doped diffused layers 29a, 29b and the heavily doped diffused layers 33a, 33b form the source/drain diffused layers 35a, 35b of the extension source/drain structure or the LDD structure.
Then, the photoresist film 136 is released by, e.g., asking.
The following steps of the method for manufacturing the semiconductor device are the same as those of the method for manufacturing the semiconductor device according to the first embodiment illustrated in
Thus, the semiconductor device according to the present embodiment is manufactured (see
The present invention is not limited to the above-described embodiments and can cover other various modifications.
For example, in the above-described embodiments, the semiconductor substrate 10 is a P-type semiconductor substrate, and the conduction type of the semiconductor substrate 10 is not limited to P-type. For example, an N-type semiconductor substrate may be used. When an N-type semiconductor substrate is used, the conduction types of the respective constituent members described above are reversed.
The second embodiment is described above by means of the CMOS inverter using the N-channel type high withstand voltage transistor 40N and the P-channel type high withstand voltage transistor 40P, but this is not essential. For example, an ESD protection circuit may comprise the N-channel type high withstand voltage transistor 40N and the P-channel type high withstand voltage transistor 40P (refer to the modification of the first embodiment).
All examples and conditional language recited herein are intended for pedagogical purposes to aid the reader in understanding the invention and the concepts contributed by the inventor to furthering the art, and are to be construed as being without limitation to such specifically recited examples and conditions, nor does the organization of such examples in the specification relate to a showing of the superiority and inferiority of the invention. Although the embodiments of the present invention have been described in detail, it should be understood that the various changes, substitutions, and alterations could be made hereto without departing from the spirit and scope of the invention.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2012-007286 | Jan 2012 | JP | national |
