Patent Application
20120248628
This application is based upon and claims the benefit of priority from prior Japanese Patent Application No. 2011-080242, filed on Mar. 31, 2011, the entire contents of which are incorporated herein by reference.
Embodiments of the invention relate to a semiconductor device and a method of fabricating the same.
In recent years, various development efforts have been underway on a semiconductor device including multiple semiconductor chips, contained in a single package. For the purpose of reducing the size of the package, a structure in which the multiple semiconductor chips are stacked one on another with an adhesive interposed between each two neighboring semiconductor chips is used for the semiconductor device.
One method of fabricating the semiconductor device having the stacked structure is that a semiconductor chip having an adhesion layer on the lowermost surface is stacked on a control element which is smaller in size than the semiconductor chip.
In this case, the adhesion layer between the control element and the semiconductor chip deforms the semiconductor chip provided above the control element. For this reason, the deformation adversely affects the reliability of the operation of the semiconductor chip, and the reliability of the joint between the semiconductor chip and the adhesion layer. This has been pointed out as a problem.
According to one embodiment, a semiconductor device includes a control element provided above a main surface of a substrate through a first adhesion layer, a second adhesion layer provided to cover the control element a first semiconductor chip provided on the second adhesion layer, a bottom surface area of the first semiconductor chip being larger than a top surface area of the control element, and at least one side of an outer edge of the control element projecting to an outside of an outer edge of the first semiconductor chip.
Descriptions will be hereinbelow provided for the embodiments while referring to the drawings.
Through the descriptions for the following embodiments, the same portions shown throughout the drawings will be denoted by the same reference numerals, and detailed descriptions for such portions will be omitted whenever deemed possible. On the other hand, descriptions will be provided for different portions, depending on the necessity. In addition, words indicating directions, such as upper, lower, left and right, which are used to describe the embodiments, denote relative directions on the assumption that a surface on which the below-described solder balls 11 are provided is located lower than any other portions, except for the solder balls. For this reason, the relative direction may be different from the directions with respect to the direction of the acceleration of gravity.
A semiconductor chip 9 is a NAND flash memory, for example. Control elements 4 are memory controllers, for example, and control the operation of the semiconductor chip 9.
As shown in
Each control element 4 is mounted on the top surface of the substrate 2 with an adhesion layer 3, which is provided on the back surface of the control element 4. Namely, the adhesion layer 3 is interposed between the control element and the substrate 2. A thermosetting epoxy resin, for example, is used for the adhesion layer 3. The adhesion layer 3 is approximately 10 μm, for example, in the film thickness, while the control element 4 is approximately 30 μm, for example, in the chip thickness. Electrode pads 5 are provided on each control element 4. The electrode pads 5 are electrically connected to connection terminals 6, which are provided on the top surface of the substrate 2, through metal wires 7, respectively.
The adhesion layer 8 is provided in a way that makes the adhesion layer 8 cover the control elements 4. The adhesion layer 8 may cover a portion of each control element 4, for example, a portion of the top surface of the control element 4, or portions of the top and side surfaces of the control element 4. Otherwise, the adhesion layer 8 may cover the entire top and side surfaces of each control element 4.
A portion of the adhesion layer 8 may be provided outside the outer edge of the semiconductor chip 9 in a way that the volume of the portion is equal to the sum of the volumes of portions of the adhesion layers 3 and the volumes of portions of the control elements 4, which are situated inside the outer edge of the semiconductor chip 9. In this case, a portion of the adhesion layer 8 which is situated inside the outer edge of the semiconductor chip 9 is discharged to the outside of the outer edge of the semiconductor chip 9. This leads to a decrease in the stress applied from the adhesion layer 8 to the semiconductor chip 9, and accordingly inhibits the deformation of the semiconductor chip 9.
As the adhesion layer 8, a DAF (Die Attach Film), for example, is attached to the back surface of the semiconductor chip 9, and the resultant DAF is compression-bonded to the control elements 4. The adhesion layer 8 contains an epoxy resin, for example. The viscosity of the adhesion layer 8 is 100 to 10000 Pa·S at a temperature in a range of 80 to 160° C., for example. The film thickness of the adhesion layer 8 is 40 to 150 μm, for example.
The semiconductor chip 9 is provided on the adhesion layer 8. The area of the bottom surface of the semiconductor chip 9 is larger than the sum of the areas of the top surfaces of the control elements 4. In addition, as shown in
Other electrode pads 5 provided on the semiconductor chip 9 are connected to the connection terminals 6 provided on the top surface of the substrate 2 by use of the respective metal wires 7.
Semiconductor chips 13 may be provided above the semiconductor chip 9 with an adhesion layer 12 interposed between each two neighboring semiconductors, as shown in
In addition, an encapsulation resin 10 is provided in a way that makes the encapsulation resin 10 cover the semiconductor chip 9 and the control elements 4. Thereby, the semiconductor chip 9 and the control elements 4 are encapsulated in a way that the semiconductor chip 9 and the control elements 4 are not exposed to the outside.
The semiconductor device 1 of the first embodiment is provided with the foregoing configuration.
Next, descriptions will be hereinbelow provided for a method of fabricating the semiconductor device 1 of the first embodiment while referring to
First of all, as shown in
As shown in
As shown in
The adhesion layer 8 is provided by attaching a DAF to the back surface of a semiconductor wafer on which the semiconductor chip 9 is provided, for example. Otherwise, the adhesion layer 8 may be provided by applying an adhesive, which contains a thermosetting resin, to the back surface of a semiconductor wafer, and subsequently by drying the adhesive.
A thermosetting epoxy resin, for example, with a low viscosity is used for the adhesion layer 8. The viscosity of the adhesion layer 8 should be 100 to 10000 Pa·S, for example, before the adhesion layer 8 is caused to set. The coefficient of elasticity of the adhesion layer 8 should be 1 to 1000 MPa, for example, after the adhesion layer 8 is caused to set. The use of the resin with the low viscosity for the adhesion layer 8 makes it possible to prevent the deformation of the metal wires 7. After that, the adhesion layer 8 is caused to set by heating the substrate 2. Thereby, the semiconductor chip 9 is fixed to the top surfaces of the control elements 4.
As shown in
The adhesion layers 12 provided on the back surfaces of the semiconductor chips 13 are caused to set by heating the substrate 2. Thereby, the semiconductor chips 13 stacked stepwise are fixed together, and to the semiconductor chip 9. Metal wires 7 are provided to connect the electrode pads 5 provided on the semiconductor chip 9 to the connection terminals 6, respectively.
As shown in
The semiconductor device 1 of the first embodiment shown in
In the first embodiment, at least one side of the outer edge of each control element 4 projects to the outside of the outer edge of the semiconductor chip 9 when viewed in the plan view. Accordingly, a portion of the adhesion layer is discharged to the outside of the outer edge of the semiconductor chip 9. This reduces the stress applied from the adhesion layer 8 to the semiconductor chip 9, and accordingly inhibits the deformation of the semiconductor chip 9.
Furthermore, in a case where two sides of the outer edge of each control element 4 projects to the outside of the outer edge of the semiconductor chip 9 when viewed in the plan view, a portion of the adhesion layer 8 is easily discharged to the outside of the outer edged of the semiconductor chip 9. Therefore, it is possible to further inhibit the deformation of the semiconductor chip 9.
Descriptions will be provided for a semiconductor device 1 of a second embodiment by use of
What makes the second embodiment different from the first embodiment is that a semiconductor chip 15 is provided above a substrate 2 with an adhesion layer 14 interposed in between, and that control elements 4 are provided above the semiconductor chip 15 with an adhesive layer 3 interposed in between. Two control elements 4 may be provided above the semiconductor chip 15, as shown in
Descriptions will be provided for a method of fabricating the semiconductor device 1 according to the second embodiment while referring to
As shown in
As shown in
As shown in
A thermosetting epoxy resin, for example, with a low viscosity is used for the adhesion layer 8. The viscosity of the adhesion layer 8 should be 100 to 10000 Pa·S, for example, before the adhesion layer 8 is caused to set. The coefficient of elasticity of the adhesion layer 8 should be 1 to 1000 MPa, for example, after the adhesion layer 8 is caused to set. A portion of the adhesion layer 8 is discharged to the outside of the outer edge of the semiconductor chip 9 in a way that the volume of the discharged portion is corresponded to the sum of the volumes of portions of the adhesion layers 3 and the volumes of portions of the control elements 4, which are situated inside the outer edge of the semiconductor chip 9 when viewed in the plan view. This reduces the stress applied from the adhesion layer 8 to the semiconductor chip 9, and accordingly inhibits the deformation of the semiconductor chip 9. The adhesion layer 8 is caused to set by heating the substrate 2. Thereby, the semiconductor chip 9 is fixed to the top surfaces of the control elements 4.
As shown in
The adhesion layers 12 provided on the back surfaces of the semiconductor chips 13 are caused to set by heating the substrate 2. Thereby, the semiconductor chips 13 stacked stepwise are fixed together, and to the semiconductor chip 9. Metal wires 7 are provided to connect the electrode pads 5 provided on the semiconductor chip 9 and the semiconductor chips 13 to the connection terminals 6, respectively.
As shown in
The semiconductor device 1 of the second embodiment is provided with the foregoing configuration.
It should be noted that the metal wires 7 to connect the connection terminals 6 provided on the substrate 2, the control elements 4, and the electrode pads 5 provided on the semiconductor chip 9 may be provided at the same time after the semiconductor chip 15, the semiconductor chip 9 and the semiconductor chips 13 are stacked above the substrate 2.
Two or more semiconductor chips 15 may be provided, although the foregoing descriptions have been provided for the embodiment on the assumption that the single semiconductor chip 15 exists between the substrate 2 and the control elements 4.
As described above, in the second embodiment, at least one side of the outer edge of each control element 4 projects to the outside of the outer edge of the semiconductor chip 9 when viewed in the plan view. Accordingly, a portion of the adhesion layer 8 is discharged to the outside of the outer edge of the semiconductor chip 9. This reduces the stress applied from the adhesion layer 8 to the semiconductor chip 9, and accordingly inhibits the deformation of the semiconductor chip 9.
Furthermore, in a case where two sides of the outer edge of each control element 4 projects to the outside of the outer edge of the semiconductor chip 9 when viewed in the plan view, a portion of the adhesion layer 8 is easily discharged to the outside of the outer edged of the semiconductor chip 9. Therefore, it is possible to further inhibit the deformation of the semiconductor chip 9.
The semiconductor device 1 of the first embodiment and the semiconductor device 1 of the second embodiment have been described on the assumption that the multiple semiconductor chips 13 are stacked. Instead, however, the semiconductor device may be that in which only one semiconductor chip 13 is provided on the control elements 4.
While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel embodiments described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2011-080242 | Mar 2011 | JP | national |
