This application claims the priority benefit of Taiwan application no. 106132526, filed on Sep. 22, 2017. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification.
The invention relates to an integrated circuit and a method of manufacturing the same. More particularly, the invention relates a semiconductor device and a method of manufacturing the same.
In recent years, III-V group compound semiconductor-based high electron mobility transistor (HEMT) devices, as having a high breakdown voltage, a larger bandgap and excellent carrier mobility, can exhibit preferable low impedance conductance through a two-dimensional electron gas (2DEG) generated by polarization, such that a III-V group compound semiconductor material may be widely applied in high-frequency devices and power devices. A metal-insulator-semiconductor HEMT (MIS-HEMT) device is one kind of the HEMT devices. The MIS-HEMT device has a gate dielectric layer capable of reinforcing device performance at an interface between a metal and a semiconductor, such as a high breakdown voltage, a low gate leakage current, a low device impedance and a wide gate operation range.
However, the structure of the gate dielectric layer may easily cause additional interface trapping and so causes issues, such as pinch-off voltage shift, current collapse, reliability failure and so on, which may affect electricity of the MIS-HEMT device. The above-mentioned electricity issues incur limitations to the application of the MIS-HEMT device. Thus, how to prevent the MIS-HEMT device from generating the interface trapping has been an important subject.
The invention provides a semiconductor device capable of connecting a metal-insulator-semiconductor high electron mobility transistor (MIS-HEMT) device with a diode in parallel to prevent interface trapping, so as to enhance device performance.
The invention provides a method of manufacturing a semiconductor device which is capable of integrating an MIS-HEMT device and a diode in one chip by using a single-chip integration technique to significantly reduce a use area of the chip, so as to meet requirements for miniaturization of electronic devices.
According to an embodiment of the invention, a semiconductor device including a substrate, a diode, a channel layer, a barrier layer, a first dielectric layer, a source, a drain, a gate, and a two-dimensional electron gas (2DEG) is provided. The diode is disposed over a substrate or in the substrate. The diode includes a first region with a first conductive type and a second region with a second conductive type, and the first conductive type is different from the second conductive type. The channel layer is disposed over the diode. The barrier layer is disposed over the channel layer. The first dielectric layer is disposed over the barrier layer. The source is electrically connected to the first region of the diode by a first conductive via through the first dielectric layer, the barrier layer, and the channel layer. The drain is electrically connected to the second region of the diode by a second conductive via through the first dielectric layer, the barrier layer, and the channel layer. The gate is disposed over the channel layer between the source and the drain. The 2DEG is disposed in the channel layer between the source and the drain.
According to an embodiment of the invention, a semiconductor device including a substrate, a channel layer, a barrier layer, a dielectric layer, a source, a drain, a gate, an anode, a cathode, and a two-dimensional electron gas (2DEG). The channel layer is disposed over a substrate. The barrier layer is disposed over the channel layer. The dielectric layer is disposed over the barrier layer. The source passes through the dielectric layer and the barrier layer and is electrically connected with the channel layer. The drain passes through the dielectric layer and the barrier layer and is electrically connected with the channel layer. The gate is disposed over the dielectric layer between the source and the drain. The anode passes through the dielectric layer and is electrically connected with the barrier layer and electrically connected with the source by a first interconnect. The anode and the barrier layer form a Schottky diode. The cathode passes through the dielectric layer and the barrier layer and is electrically connected with the channel layer and electrically connected with the drain by a second interconnect. The 2DEG is disposed in the channel layer between the source and the drain and disposed in the channel layer between the source and the cathode.
According to an embodiment of the invention a method of manufacturing a semiconductor device is provided, which includes the following steps. A channel layer, a barrier layer and a dielectric layer is sequentially formed over a front surface of a substrate. A first region with a first conductive type and a second region with a second conductive type are respectively formed in the substrate, wherein the first conductive type is different from the second conductive type. A first conductive via is formed in the dielectric layer, the barrier layer and the channel layer, such that a source is electrically connected with the first region by the first conductive via. A second conductive via is formed in the dielectric layer, the barrier layer and the channel layer, such that a drain is electrically connected with the second region by the second conductive via. A gate is formed on the dielectric layer between the source and the drain. A two-dimensional electron gas (2DEG) is formed in the channel layer between the source and the drain.
Based on the above, in the invention, the MIS-HEMT device and the diode can be connected in parallel and integrated with each other on the same chip by utilizing the single-chip integration technique, which can not only significantly reduce the use area of the chip, but also prevent the interface trapping, so as to enhance the device performance.
In order to make the aforementioned and other features and advantages of the invention more comprehensible, several embodiments accompanied with figures are described in detail below.
The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
The invention is illustrated more comprehensively with reference to the following drawings which show embodiments of the present invention. However, the invention can further be implemented in various manners and should not be limited to the embodiments set forth hereinafter. Thicknesses of layer and areas in the drawings are exaggerated for the sake of clarity. The same or similar referral numerals are used to represent the same or the like parts and thus, will not be repeatedly described.
Referring to
Then, a buffer layer 102, a channel layer 104, a barrier layer 106 and a dielectric layer 108 are sequentially formed on the front surface S1 of the substrate 100. In an embodiment, a method of forming the buffer layer 102, the channel layer 104, the barrier layer 106 and the dielectric layer 108 may be an epitaxial growth method, such as a metal-organic chemical vapor deposition (MOCVD) method or a molecular beam epitaxy (MBE) method.
Specifically, the buffer layer 102 may be disposed between the substrate 100 and the channel layer 104 to reduce a difference of lattice constant and a difference of coefficients of thermal expansion (CTE) between the substrate 100 and the channel layer 104. In an embodiment, a material of the buffer layer 102 includes a III group nitride, e.g., a III-V group compound semiconductor material, and the buffer layer 102 may have a single-layer structure or a multi-layer structure. In an alternative embodiment, the material of the buffer layer 102 includes AlN, GaN, AlGaN, InGaN, AlInN, AlGaInN or a combination thereof.
The channel layer 104 may be disposed between the buffer layer 102 and the barrier layer 106. In the presence of a heterojunction formed between the channel layer 104 and the barrier layer 106, a two-dimensional electron gas (2DEG) 105 with a high electron mobility is formed in a region of the channel layer 104 which is adjacent to the barrier layer 106. In an embodiment, a material of the channel layer 104 includes a III group nitride, e.g., a III-V group compound semiconductor material, which may be undoped or unintentionally doped GaN, for example. However, the invention is not limited thereto, and in other embodiments, as long as a bandgap of a material of the channel layer 104 is different from a bandgap of a material the barrier layer 106, the material of the channel layer 104 falls within the scope of the invention.
The barrier layer 106 may be disposed between channel layer 104 (or the 2DEG 105) and the dielectric layer 108. In an embodiment, a material of the barrier layer 106 includes a III group nitride, e.g., a III-V group compound semiconductor material, and the barrier layer 106 may have a single-layer or a multi-layer structure. In an embodiment, the barrier layer 106 includes AlGaN, AlInN, AlN, AlGaInN or a combination thereof. In an embodiment, the barrier layer 106 may also be a doped or undoped layer.
The dielectric layer 108 may be disposed on the barrier layer 106. In an embodiment, a material of the dielectric layer 108 includes a dielectric material, and the dielectric layer 108 may have a single-layer structure or a multi-layer structure. In an embodiment, the material of the dielectric layer 108 includes Al2O3, SiN, SiO, AlN or a combination thereof.
Referring to
Specifically, the step of respectively forming the first region 100a and the second region 100b in the substrate 100 will be set forth as follows. With the back surface S2 of the substrate 100 facing upwards, a first mask pattern (which is not shown) is formed on the back surface S2 of the substrate 100 to cover the second region 100b and expose the first region 100a. A first ion implantation process is performed on the first region 100a, such that a conductive type of the substrate 100 in the first region 100a is changed to the P-type. In an embodiment, a dopant implanted into the first region 100a may be, for example, boron, and a doping concentration thereof may be, for example, 1×1018/cm3 to 1×102° /cm3.
After the first mask pattern is removed, a second mask pattern (which is not shown) is formed on the back surface S2 of the substrate 100 to cover the first region 100a and expose the second region 100b. A second ion implantation process is performed on the second region 100b, such that a conductive type of the substrate 100 in the second region 100b is changed to the N-type. In an embodiment, a dopant implanted into the second region 100b may be, for example, phosphorous or arsenic, and a doping concentration thereof may be, for example, 1×1018/cm3 to 1×1020/cm3.
In the present embodiment, the first region 100a is formed before the second region 100b is formed, but the invention is not limited thereto. In other embodiments, the second region 100b may be formed before the first region 100a is formed. In an alternative embodiment, a lithography and ion implantation process may be performed by using a P-type substrate to form an N-type doped region in the P-type substrate.
It should be noted that as shown in
Referring to
To be specific, a step of forming the first conductive via 110 and the second conductive via 120 may include forming a third mask pattern (which is not shown) on the dielectric layer 108 to define positions of the first conductive via 110 and the second conductive via 120. Then, by using the third mask pattern as an etching mask, a part of the dielectric layer 108, a part of the barrier layer 106, a part of the channel layer 104 and a part of the buffer layer 102 are removed, so as to form a first opening 112 and a second opening 122. The first opening 112 exposes a part of the surface of the first region 100a of the substrate 100, and the second opening 122 exposes a part of the surface of the second region 100b of the substrate 100. Thereafter, the conductive material is filled in the first opening 112 and the second opening 122 by an electroplating method or a vapor deposition method to form the first conductive via 110 in the first opening 112, form the source S on the first conductive via 110, form the second conductive via 120 in the second opening 122 and form the drain D on the second conductive via 120. In an embodiment, the conductive material may include a metal (e.g., Ta, Ti, W, Pd, Ni, Au, Al or a combination thereof), a metal nitride (e.g., TaN, TiN, WN or a combination thereof), a metal silicide (e.g., WSix) or a combination thereof.
Referring to
Referring to
Referring to
It should be noted that in the present embodiment, the P-N junction diode 20a formed by the P-type first region I00a and the N-type second region 100b may be connected in parallel and integrated with an MIS-HEMT device 10a on the same chip, which may not only significantly reduce the use area of the chip, but also prevent the interface trapping, thereby enhancing the device performance.
Referring to
In the present embodiment, the PIN junction diode 20b may be connected in parallel and integrated with the MIS-HEMT device 10a on the same chip, which may not only significantly reduce the use area of the chip, but also prevent the interface trapping, thereby enhancing the device performance. By being compared with the P-N junction diode, the PIN junction diode 20b is capable of withstanding a greater operating voltage (e.g., 10 V to 3000 V).
Referring to
In the present embodiment, the RTD 20c may be connected in parallel and integrated with the MIS-HEMT device 10a on the same chip, which may not only significantly reduce the use area of the chip, but also prevent the interface trapping, thereby enhancing the device performance. The RTD 20c may contribute to increasing a bandgap width, thereby, suppressing a leakage current.
Referring to
In the present embodiment, the PIN junction diode 20d may be connected in parallel and integrated with the MIS-HEMT device 10b on the same chip, which may not only significantly reduce the use area of the chip, but also prevent the interface trapping, thereby enhancing the device performance.
Referring to
In the present embodiment, the P-N junction diode 20e may be connected in parallel and integrated with the MIS-HEMT device 10a on the same chip, which may not only significantly reduce the use area of the chip, but also prevent the interface trapping, thereby enhancing the device performance.
In an embodiment, the semiconductor devices 1, 2, 3, 4 and 5 may be depletion mode (D-mode) HEM transistor devices. Namely, in a scenario that a gate voltage is not applied, the 2DEG (or a carrier channel) 105 in the channel layer 104 may be, for example, in a normally-on state, and in a scenario that the gate voltage is applied, the 2DEG (or the carrier channel) 105 in the channel layer 104 of the D-mode HEM transistor devices may be turned off.
Referring to
In addition, the dielectric layer 118 not only conformally covers the surface of the third opening 132, but also is extended to cover a top surface of the dielectric layer 108. In an embodiment, the dielectric layer 118 may be considered as a gate dielectric layer, which is capable of reducing a leakage current of the gate G and adjusting a threshold voltage (Vth) by changing a thickness of the dielectric layer 118. A material of the dielectric layer 118 includes Al2O3, SiN, SiO, AlN or a combination thereof, and a method of forming the dielectric layer 118 may be an epitaxial growth method, e.g., a MOCVD method of an MBE method.
In addition, as shown in
In an embodiment, the semiconductor device 6 may be an enhancement mode (E-mode) HEMT device. Namely, in a scenario that a gate voltage is not applied, the 2DEG (or the carrier channel) 105 in the channel layer 104 may be in a normally-off state, and in a scenario that the gate voltage is applied, the 2DEG (or the carrier channel) 105 in the channel layer 104 of such E-mode HEM transistor may be turned on. Additionally, in the present embodiment, the P-N junction diode 20a may be connected in parallel and integrated with an MIS-HEMT device 10c on the same chip, which may not only significantly reduce the use area of the chip, but also prevent the interface trapping, thereby enhancing the device performance.
The present embodiment provides a semiconductor device 7 including the substrate 100, the channel layer 104, the barrier layer 106, the dielectric layer 108, an interlayer dielectric layer 116, the source S, the drain D, the gate G, an anode A and a cathode C. The channel layer 104 (which has the 2DEG 105 in the region adjacent to the barrier layer 106), the barrier layer 106, the dielectric layer 108 and the interlayer dielectric layer 116 are sequentially disposed on the substrate 100.
In an embodiment, the source S may be a conductive via type passing through the interlayer dielectric layer 116, the dielectric layer 108 and the barrier layer 106 and be electrically connected with the channel layer 104. In an alternative embodiment, as shown in
In an embodiment, the drain D may be a conductive via type passing through the interlayer dielectric layer 116, the dielectric layer 108 and the second conductive via 120 of the barrier layer 106 and be electrically connected with the channel layer 104. In an alternative embodiment, as shown in
In an embodiment, the gate G may be a conductive via type passing through the interlayer dielectric layer 116 and disposed on the dielectric layer 108 between the source S and the drain D. In an embodiment, the anode A may be a conductive via type passing through the interlayer dielectric layer 116 and the dielectric layer 108, electrically connected with the barrier layer 106 and electrically connected with the source S by the first interconnect 150. In an embodiment, the cathode C may be a conductive via type passing through the interlayer dielectric layer 116, the dielectric layer 108 and the barrier layer 106, electrically connected with the channel layer 104 and electrically connected with the drain D by the second interconnect 160. In an alternative embodiment, as shown in
In an embodiment, the anode A and the barrier layer 106 may form a Schottky diode 20f. The cathode C and the channel layer 104 may form an ohmic contact. Thus, the MIS-HEMT device 10d may be connected in parallel and integrated with the Schottky diode 20f on the same chip by the first interconnect 150 and the second interconnect 160. Namely, in the invention, different devices (which are not limited to the MIS-HEMT device) may be connected in parallel and integrated with various diodes on the same chip by means of interconnects, so as to reduce the use area of the chip.
In some embodiments, the 2DEG 105 is disposed in the channel layer 104 between the source S and the drain D and disposed in the channel layer 104 between the source S and the cathode C. In some alternative embodiments, as shown in
In other embodiments, the semiconductor device 7 may also include a buffer layer (which is not shown) disposed between the substrate 100 and the channel layer 104 to reduce a difference of lattice constant and a difference of CTE between the substrate 100 and the channel layer 104.
In light of the foregoing, in the invention, the MIS-HEMT device and the diode can be connected in parallel and integrated with each other on the same chip by the single-chip integration technique, which can not only significantly reduce the use area of the chip, but also prevent the interface trapping, thereby enhancing the device performance.
Although the invention has been described with reference to the above embodiments, it will be apparent to one of the ordinary skill in the art that modifications to the described embodiment may be made without departing from the spirit of the invention. Accordingly, the scope of the invention will be defined by the attached claims not by the above detailed descriptions.
Number | Date | Country | Kind |
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106132526 | Sep 2017 | TW | national |