SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

Abstract

It is made possible to reduce the interface resistance at the interface between the nickel silicide film and the silicon. A semiconductor manufacturing method includes: forming an impurity region on a silicon substrate, with impurities being introduced into the impurity region; depositing a Ni layer so as to cover the impurity region; changing the surface of the impurity region into a NiSi2 layer through annealing; forming a Ni layer on the NiSi2 layer; and silicidating the NiSi2 layer through annealing.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a flowchart showing a method of manufacturing a semiconductor device according to a first embodiment of the present invention;

FIGS. 2( a) to 2(e) are cross-sectional views illustrating the steps in the manufacturing method according to the first embodiment;

FIG. 3 is a flowchart showing a method of manufacturing a semiconductor device according to a second embodiment of the present invention;

FIGS. 4( a) to 4(f) are cross-sectional views illustrating the steps in the manufacturing method according to the second embodiment;

FIG. 5 is a cross-sectional view illustrating a step for manufacturing a semiconductor device of Example 1;

FIG. 6 is a cross-sectional view illustrating a step for manufacturing a semiconductor device of Example 1;

FIG. 7 is a cross-sectional view illustrating a step for manufacturing a semiconductor device of Example 1;

FIG. 8 is a cross-sectional view illustrating a step for manufacturing a semiconductor device of Example 1;

FIG. 9 is a cross-sectional view illustrating a step for manufacturing a semiconductor device of Example 1;

FIG. 10 is a cross-sectional view illustrating a step for manufacturing a semiconductor device of Example 1;

FIG. 11 is a diagram for explaining the method of evaluating the Schottky barrier height at the interface between the nickel silicide laminated film and the silicon film of each of the Schottky diodes of Example 1 and Example 2;

FIG. 12 is a cross-sectional view illustrating a step for manufacturing a MIS transistor of Example 5;

FIG. 13 is a cross-sectional view illustrating a step for manufacturing a MIS transistor of Example 5;

FIG. 14 is a cross-sectional view illustrating a step for manufacturing a MIS transistor of Example 5;

FIG. 15 is a cross-sectional view illustrating a step for manufacturing a MIS transistor of Example 5;

FIG. 16 is a cross-sectional view illustrating a step for manufacturing a MIS transistor of Example 5;

FIG. 17 is a cross-sectional view illustrating a step for manufacturing a MIS transistor of Example 5;

FIG. 18 is a diagram showing the dependence of the drain current on the gate voltage in each of the MIS transistors of Example 5 and Comparative Example 3;

FIG. 19 is a cross-sectional view illustrating a step for manufacturing a MIS transistor of Example 6;

FIG. 20 is a cross-sectional view illustrating a step for manufacturing a MIS transistor of Example 6;

FIG. 21 is a cross-sectional view illustrating a step for manufacturing a MIS transistor of Example 6;

FIG. 22 is a cross-sectional view showing a CMOS device of Example 9;

FIGS. 23A and 23B are a plan view and a front view showing a Fin channel transistor of Example 10;

FIG. 24 is a cross-sectional view showing a Schottky transistor of Example 11;

FIG. 25 is a flowchart showing a conventional nickel silicide process;

FIGS. 26A and 26B are diagrams showing the results of measurement carried out through back-side SIMS on the arsenic and boron distribution in the vicinity of the interface between the NiSi film and the silicon film formed by the conventional nickel silicide process;

FIGS. 27( a), 27(b) and 27(c) are diagrams schematically showing the impurity distribution in the vicinity of the interface between the NiSi film and the silicon formed by the conventional nickel silicide process;

FIG. 28 is a diagram explaining the results of measurement carried out through back-side SIMS on the boron distribution in the vicinity of the interface between the NiSi film and the silicon film formed by the conventional nickel silicide process;

FIG. 29 is a diagram showing the characteristics of a surface phase of nickel silicide;

FIG. 30 is a diagram showing the formation energy in a case where B and As are introduced into each phase of nickel silicide and silicon film; and

FIG. 31 is a diagram showing the difference in bending of the conduction band between silicon films due to the difference in dopant amount between the silicon films (silicon substrates).

Claims

1. A method of manufacturing a semiconductor device, comprising: forming an impurity region on a silicon substrate, with impurities being introduced into the impurity region;depositing a Ni layer so as to cover the impurity region;changing the surface of the impurity region into a NiSi2 layer through annealing;forming a Ni layer on the NiSi2 layer; andsilicidating the NiSi2 layer through annealing.

2. The method of manufacturing a semiconductor device as claimed in claim 1, wherein a film thickness of the Ni layer deposited on the NiSi2 layer is smaller than a film thickness of the NiSi2 layer.

3. The method of manufacturing a semiconductor device as claimed in claim 1, wherein the silicidation of the NiSi2 layer includes forming a silicide laminated film including a NiSi2 layer and a NiSi layer.

4. The method of manufacturing a semiconductor device as claimed in claim 1, wherein the silicidation of the NiSi2 layer includes performing annealing at a temperature of 500° C. or lower.

5. The method of manufacturing a semiconductor device as claimed in claim 4, wherein the silicidation of the NiSi2 layer includes performing annealing at a temperature of 400° C. or lower.

6. The method of manufacturing a semiconductor device as claimed in claim 1, wherein the changing of the surface of the impurity region into a NiSi2 layer comprising: changing the surface of the impurity region into a Ni2Si layer through annealing;changing the Ni2Si layer into a NiSi layer through annealing; andchanging the NiSi layer into a NiSi2 layer through annealing.

7. A semiconductor device comprising a MIS transistor which includes: a gate insulating film that is provided on a semiconductor region of a first conductivity type formed on a semiconductor substrate;a gate electrode that is provided on the gate insulating film;gate sidewalls that are provided on side portions of the gate electrode and are made of an insulating material; anda silicide laminated film that is provided on the opposite side of the semiconductor region from the gate electrode when seen from the gate sidewalls, the silicide laminated film including a NiSi2 layer and a NiSi layer.

8. The semiconductor device as claimed in claim 7, wherein: the NiSi layer of the silicide laminated film is provided on the semiconductor region; andthe NiSi2 layer is provided on the NiSi layer.

9. The semiconductor device as claimed in claim 7, wherein: the NiSi2 layer of the silicide laminated film is provided on the semiconductor region; andthe NiSi layer is provided on the NiSi2 layer.

10. The semiconductor device as claimed in claim 7, further comprising: an impurity region of a second conductivity type that is provided on the opposite side of the semiconductor region from the gate electrode when seen from the gate sidewalls, the second conductivity type being different from the first conductivity type,wherein the silicide laminated film is provided on the impurity region.

11. The semiconductor device as claimed in claim 10, wherein the amount of impurities contained in a range of 20 nm from an interface between the silicide laminated film and the impurity region is larger on the side of the silicide laminated film than on the side of the impurity region.

12. The semiconductor device as claimed in claim 11, wherein the impurity region contains boron.

13. The semiconductor device as claimed in claim 10, wherein the MIS transistor is a Fin channel transistor.

14. A semiconductor device comprising: a p-type MIS transistor that comprises: a first gate insulating film that is provided on an n-type first semiconductor region formed on a semiconductor substrate; a first gate electrode that is provided on the first gate insulating film; first gate sidewalls that are provided on side portions of the first gate electrode and are made of an insulating material; a p-type impurity region that is provided on the opposite side of the first semiconductor region from the first gate electrode to the first gate sidewalls; and a first silicide laminated film that is provided on the p-type impurity region and includes a first NiSi2 layer and a first NiSi layer; andan n-type MIS transistor that comprises: a second gate insulating film that is provided on a p-type second semiconductor region formed on the semiconductor substrate;a second gate electrode that is provided on the second gate insulating film; second gate sidewalls that are provided on side portions of the second gate electrode and are made of an insulating material; an n-type impurity region that is provided on the opposite side of the second semiconductor region from the second gate electrode to the second gate sidewalls; and a second silicide laminated film that is provided on the n-type impurity region and includes a second NiSi2 layer and a second NiSi layer.

15. The semiconductor device as claimed in claim 14, wherein: the first NiSi layer of the first silicide laminated film is provided on the first semiconductor region, while the first NiSi2 layer is formed on the first NiSi layer; andthe second NiSi layer of the second silicide laminated film is provided on the second semiconductor region, while the second NiSi2 layer is provided on the second NiSi layer.

16. The semiconductor device as claimed in claim 14, wherein: the first NiSi2 layer of the first silicide laminated film is provided on the first semiconductor region, while the first NiSi layer is formed on the first NiSi2 layer; andthe second NiSi2 layer of the second silicide laminated film is provided on the second semiconductor region, while the second NiSi layer is provided on the second NiSi2 layer.