The present disclosure relates to a technique for suppressing damage when a process of forming a via and a trench for embedding a wire is performed on a porous low dielectric constant film which is formed on a substrate for manufacturing a semiconductor device.
In the manufacturing process of a multilayered semiconductor device, a porous low dielectric constant film is used as a method for reducing the parasitic capacitance of an interlayer insulating film in order to improve an operation speed. This kind of film may include, for example, an SiOC film containing, for example, silicon, carbon, oxygen and hydrogen, and having Si—C bond. Etching is performed on the SiOC film by plasma of, for example, CF4 gas as a CF-based gas, using a resist mask and an underlying mask in order to embed, for example, copper as a wiring material. Subsequently, ashing is performed on the resist mask by plasma of an oxygen gas.
Incidentally, when a plasma-based process such as etching or ashing is performed on the SiOC film, for example, the Si—C bond is cut by the plasma on an exposed surface of the SiOC film exposed to plasma, namely side walls and a bottom surface of a recess, so that C is desorbed from the film. Since Si having an unsaturated dangling bond produced by the desorption of C is unstable in that state, the Si is bonded with, for example, moisture in the atmosphere, to become Si—OH.
As described above, an etching gas or the like is diffused into a hole portion of the porous SiOC film by the plasma process, so that the SiOC film is damaged by the etching gas. Since the content of carbon is lowered in such a damaged layer, the dielectric constant is reduced. The miniaturization of the line width of a wiring pattern and thinning of a wiring layer, an insulating film, and the like have been progressed, which increases the influence of the surface portion of the SiOC film over a whole wafer. Thus, the reduction in the dielectric constant of the SiOC film may be one of the factors that cause the characteristics of a semiconductor device to deviate from a design value.
For example, there has been known a technology which includes embedding PMMA (acrylic resin) in advance in pores of a porous low dielectric constant film formed on a substrate, performing a process such as etching on the low dielectric constant film, heating the substrate, supplying a solvent, supplying microwaves, and removing the PMMA. However, in order to remove the PMMA, it is necessary to spend as much time as about 20 minutes by plasma. In addition, since the substrate has to be heated to a temperature of 400 degrees C. or more, there is a high possibility of adversely affecting an element portion already formed on the substrate.
In a concept of thermal decomposition of a resin, as the removal temperature of the resin decreases, the heat resistant temperature of the resin also decreases. In this concept, it is disclosed that only PMMA can be thermally unstuffed at 400 degrees C., which is an allowable temperature in a wiring process, but the thermal stability of PMMA drops to 250 degrees C. This means that a temperature of 250 degrees C. or higher is applied to PMMA during the protection process by PMMA, which deteriorates the PMMA film. Thus, the PMMA cannot be used as a protective film.
Therefore, in the prior art, even when a thermal process is performed in the state where the removal temperature of the protective film exceeds the allowable temperature, the PMMA film does not function as a protective film.
Some embodiments of the present disclosure provide a technique capable of suppressing damage of an interlayer insulating film when forming a wiring recess in the interlayer insulating film, which is a porous low dielectric constant layer, in manufacturing a semiconductor device.
According to one embodiment of the present disclosure, there is provided a semiconductor device manufacturing method of forming a trench and a via in a porous low dielectric constant film formed on a substrate as an interlayer insulating film, the method including: embedding a polymer having a urea bond in pores of the porous low dielectric constant film by supplying a raw material for polymerization to the porous low dielectric constant film; forming the via by etching the porous low dielectric constant film; subsequently, embedding a protective filling material made of an organic substance in the via; subsequently, forming the trench by etching the porous low dielectric constant film; subsequently, removing the protective filling material; and after the forming a trench, removing the polymer from the pores of the porous low dielectric constant film by heating the substrate to depolymerize the polymer, wherein the embedding a polymer having a urea bond in pores is performed before the forming a trench.
According to another embodiment of the present disclosure, there is provided a semiconductor device manufacturing method of forming a trench and a via in a porous low dielectric constant film formed on a substrate as an interlayer insulating film, the method including: embedding a polymer having a urea bond in pores of the porous low dielectric constant film by supplying a raw material for polymerization to the porous low dielectric constant film; forming a trench mask on a surface of the porous low dielectric constant film; forming the trench by etching the porous low dielectric constant film using the trench mask; subsequently, forming a via mask in the trench; subsequently, forming the via by etching a bottom of the trench using the via mask; subsequently, removing the via mask; and after the forming a trench, removing the polymer from the pores of the porous low dielectric constant film by heating the substrate to depolymerize the polymer.
The accompanying drawings, which are incorporated in and constitute some steps of the specification, illustrate embodiments of the present disclosure, and together with the general description given above and the detailed description of the embodiments given below, serve to explain the principles of the present disclosure.
Reference will now be made in detail to various embodiments, examples of which are illustrated in the accompanying drawings. In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the present disclosure. However, it will be apparent to one of ordinary skill in the art that the present disclosure may be practiced without these specific details. In other instances, well-known methods, procedures, systems, and components have not been described in detail so as not to unnecessarily obscure aspects of the various embodiments.
In a case where a plurality of layers, on each of which an integrated circuit is formed, is stacked in a semiconductor device, it is necessary to form a via (a via hole), in which a wire for connecting an underlying circuit and an upper-lying circuit is embedded, and a trench (groove), in which a wire constituting a portion of the integrated circuit of each layer is embedded, in an interlayer insulating film.
In forming a via and a trench, there are a method of forming the via followed by the trench in an interlayer insulating film, and a method of forming the trench followed by the via the interlayer insulating film. Herein, the method of initially forming the via will be referred to as a “via-first method”, and a method of initially forming the trench will be referred to as a “trench-first method”.
In the via-first method which has been generally performed, a via 201 is formed and then a trench 202 is formed. In the embodiment of the present disclosure, after forming the via 201 and before forming the trench 202, a protective filling material 100 is embedded in the via 201, as an intermediate process indicated by an arrow. The via 201 indicates a hole extending downward of the bottom of the trench. For the sake of convenience in illustration herein, a hole portion defined above a via as a projection area to which the via is projected will also be referred to as a “via”. This via is also indicated by reference numeral 201.
In the trench-first method, a trench 202 is formed and then a via-formation etching mask 101 is formed in the trench 202. Subsequently, the bottom of the low dielectric constant film 20 is etched with the mask 101 to form the via 201. Thereafter, the mask 101 in the trench 202 is removed by etching or ashing.
A first embodiment of the present disclosure is a method applied to the via-first method.
The low dielectric constant film 20 as an interlayer insulating film is formed on the etching stopper film 13. In this embodiment, an SiOC film is used for the low dielectric constant film 20. The SiOC film is formed by a CVD method by, for example, plasmarizing DEMS (diethoxymethylsilane). The low dielectric constant film 20 is porous. In the figures, pores 21 formed in the low dielectric constant film 20 are shown with emphasis. An SiOC film is also used for the underlying interlayer insulating film 11.
In the method of the present embodiment, processing is initiated from the state in which the underlying circuit portion is formed on a surface of a semiconductor wafer (hereinafter referred to as a “wafer”) as a substrate, and the low dielectric constant film 20 is formed on the underlying circuit portion, as illustrated in
Subsequently, as illustrated in
Thereafter, the silicon oxide film 31 is etched by, for example, a gas obtained by activating (plasmarizing) CH3F gas (
For example, the polyurea film can be produced by copolymerization using an isocyanate and an amine as illustrated in
As the isocyanate, for example, an alicyclic compound, an aliphatic compound, an aromatic compound or the like may be used. As the alicyclic compound, for example, as illustrated in
A CVD apparatus for forming (vapor deposition polymerization) polyurea by reacting a raw material monomers with each other in a gaseous state is shown in
As a method of embedding polyurea in the pores 21 of the low dielectric constant film 20, it may be possible to adopt a method of alternately supplying isocyanate vapor and amine vapor to a semiconductor wafer W (hereinafter, simply referred to as “wafer W”), which includes the aforementioned circuit portion. In this case, it may be possible to use a method of stopping the supply of the isocyanate vapor, followed by purging the interior of the vacuum container 70 with a nitrogen gas, followed by supplying the amine vapor, followed by stopping the supply of the amine vapor, followed by purging the interior of the vacuum container 70 with the nitrogen gas, followed by starting the supply of the isocyanate vapor. Alternatively, it may be possible to use a method of stopping the supply of one of the isocyanate vapor and the amine vapor, followed by supplying the other vapor while bypassing the purging process, followed by stopping the supply of the other vapor, followed by supplying the one vapor while bypassing the purging process. In some embodiments, it may be possible to use a method of simultaneously supplying the isocyanate vapor and the amine vapor to the wafer W.
Of the aforementioned two methods that alternately supply the isocyanate vapor and the amine vapor, in the former method (i.e., the method which performs the purging process between the supply of one of the isocyanate vapor and the amine vapor and the supply of the other), polyurea is not deposited on the surface of the low dielectric constant film 20, but is embedded in the pores 21. In the latter method (the method which bypasses the purging process between the supply of one of the isocyanate vapor and the amine vapor and the supply of the other), polyurea is embedded in the pores 21, but is also deposited on the surface of the wafer W other than the low dielectric constant film 20 (on the hard mask 32). This phenomenon is described in an Evaluation test to be described later. It is considered that the phenomenon occurs when parameter values such as the number of supply cycles are selected. In the case of adopting the latter method, a state illustrated in
Therefore, by selecting the temperature and the period of time, it is possible to leave polyurea only in the low dielectric constant film 20.
In the method using the isocyanate vapor and the amine vapor, the temperature of the wafer W is set within a temperature range from room temperature to a temperature slightly lower than the temperature at which polyurea is depolymerized. For example, the polymerization reaction is promoted, for example, in a temperature range of 20 degrees C. to 200 degrees C.
Further, as illustrated in
Furthermore, as illustrated in
In addition, a raw material monomer having a urea bond may be polymerized to obtain a polyurea film.
After the polyurea is embedded in the pores 21 of the low dielectric constant film 20 in this way, a pattern mask for via 33 made of Spin-On-Carbon (SOC), in which a portion corresponding to the via 201 is opened (
The method of etching the low dielectric constant film 20 (in this embodiment, an SiOC film) can be performed using plasma obtained by plasmarizing C6F6 gas. In this case, a trace amount of oxygen gas may be added.
Subsequently, a protective filling material 34 made of an organic substance (in this embodiment, polyurea) is embedded in the via 201. The process of embedding the protective filling material 34 (polyurea) is carried out by alternately supplying, for example, the isocyanate vapor and the amine vapor to the wafer having the circuit portion formed thereon in a vacuum atmosphere as described above. As a result, the polyurea is embedded in the via 201 so that the protective filling material 34 is formed. The polyurea is also deposited on a surface of the pattern mask 33 other than the via 201 (
Subsequently, the pattern mask 33 made of SOC is removed by ashing (etching) with plasma obtained by plasmarizing, for example, an oxygen gas (
The low dielectric constant film 20 is etched using the silicon oxide film 31 and the hard mask 32 used as a mask for trench to form the trench 202 (
Subsequently, when the wafer is heated to the temperature at which polyurea is depolymerized, for example 350 degrees C., the amine is depolymerized and evaporized. As a result, the protective filling material 34 made of polyurea is removed as illustrated in
As illustrated in
A heating mechanism of heating the wafer is not limited to the infrared lamp 54, and may be a heater provided on the mounting table 52.
After removing the protective filling material 34, the etching stopper film 13 existing on the bottom of the via 201 is etched and removed (
Thereafter, a barrier layer 35 for preventing copper used as a conductive path (to be described later) from diffusing into the low dielectric constant film 20 as an interlayer insulating film, is formed on inner surfaces of the via 201 and the trench 202 (
The process of removing the polyurea embedded in the pores 21 of the low dielectric constant film 20 is not limited to this embodiment. As an example, the removing process may be performed after removing a portion of the etching stopper film 13 by etching (
According to the first embodiment, a raw material for polymerization is supplied to the low dielectric constant film 20, a polyurea having a urea bond is embedded in the pores 21 of the low dielectric constant film 20, the low dielectric constant film 20 is etched and subsequently, the wafer is heated to depolymerize the polyurea. Therefore, when etching the low dielectric constant film 20, the low dielectric constant film 20 is protected by the polyurea (polymer). Since the via 201 is embedded with a filling material made of polyurea after the formation of the via 201 and before the formation of the trench 202, an inner circumferential surface of the via 201 is protected from the etching gas used when forming the trench 202. Therefore, since the low dielectric constant film is protected from the etching gas in addition to embedding the polymer in the pores 21, the occurrence of damage to the low dielectric constant film is suppressed.
Hereinafter, modifications of the first embodiment will be described.
A modification illustrated in
Subsequently, the silicon oxide film 31 is etched by plasma obtained by plasmarizing a CH3F gas into plasma, and then the low dielectric constant film 20 is etched by plasma obtained by plasmarizing a C6F6 gas (
In the first embodiment, when the silicon oxide film 31 on the low dielectric constant film 20 is etched, the surface of the low dielectric constant film 20 is exposed to the etching gas. However, in the method of
A modification illustrated in
In this case, in the ashing step of exposing an upper surface of the filling material 34 on the surface of the low dielectric constant film 20, since the film to be removed is only the SOC, it can be expected that there is no possibility of the generation of residual polyurea.
As another modification, a material other than polyurea, for example, SOC, may be embedded as a filling material to be embedded in the via 201. An example of such a method may include a method of forming SOC on the surface of the wafer after the state of
A modification illustrated in
A second embodiment of the present disclosure is a method applied to the trench-first method.
Then, the low dielectric constant film 20 is etched using the laminated body as a mask so as to form a trench 202 (
The patterning mask may be formed by etching the antireflection film 37 with plasma obtained by plasmarizing an oxygen (O2) gas, a carbon dioxide (CO2) gas, an ammonia (NH3) gas, or a mixed gas of a nitrogen (N2) gas and a hydrogen (H2) gas.
Subsequently, the SOC film 33 and the polyurea film 41 are ashed (etched) with plasma obtained by plasmarizing, for example, the oxygen gas, through the use of the above-described patterning mask. Thus, an opening is formed in a portion corresponding to the via 201 (
Subsequently, the low dielectric constant film 20 is etched using plasma obtained by plasmarizing, for example, the C6F6 gas as an etching gas as described above, thus forming the via 201 (
As described above, the polyurea film 41 is depolymerized by heating the wafer to a temperature equal to or higher than the temperature at which polyurea is depolymerized and adjusting the heating temperature and the heating time. At this time, in the low dielectric constant film 20, the polyurea escapes from the pores 21 in a portion near the inner peripheral surface of the via 201. Subsequent steps are performed in the same manner as in the first embodiment.
According to the second embodiment, as in the first embodiment, a raw material for polymerization is supplied to the low dielectric constant film 20, polyurea is embedded in the pores 21 of the low dielectric constant film 20, the low dielectric constant film 20 is etched, and subsequently, the wafer is heated so as to depolymerize the polyurea. Therefore, when etching the low dielectric constant film 20, the low dielectric constant film 20 is protected by polymer. That is to say, even with the second embodiment, the same effects as in the first embodiment can be obtained. After forming the trench 202, a mask for forming the via 201 inside the trench 202 is formed by the polyurea film 41. Thus, the removal of the mask from the inside of the trench 202 may be performed by depolymerization of the polyurea film 41 using heating. Therefore, it is possible to suppress damage to the inner wall of the trench 202.
Modifications of the second embodiment will be described below.
Thereafter, the wafer is heated to remove the polyurea film 41 by depolymerization, and the heating is continued to remove the polyurea embedded in the pores 21 of the low dielectric constant film 20 by depolymerization (
Further, in this modification, the mask for etching the via 201 is formed by the polyurea film 41, but may be formed by an SOG film instead of the polyurea film 41. In this case, the polyurea film 41 described with reference to
A modification illustrated in
Subsequently, a polyurea film 41 is formed on the wafer so as to embed the polyurea film 41 in the trench 202 (
Subsequently, the low dielectric constant film 20 is etched using the polyurea film 41 and the pattern mask 33 so as to form the via 201 (
In the modification illustrated in
In a modification illustrated in
A film-forming process was performed which includes alternately supplying H6XDI as isocyanate and H6XDA as amine in a gaseous state to a substrate having a porous low dielectric constant film made of SiOC for 3 seconds each time, and performing a nitrogen gas-based purging process for 12 seconds after one of the supply of H6XDI and the supply of H6XDA is terminated and before the other is initiated. This procedure was performed 100 cycles. Composition in the surface of the substrate before and after the film-forming process was examined by X-ray Photoelectron Spectroscopy (XPS). The results are shown in
As can be seen from
A film-forming process was performed which includes alternately supplying H6XDI and H6XDA in a gaseous state to a substrate having a porous low dielectric constant film made of SiOC for 3 seconds each time, and after the completion of one of the supply of H6XDI and the supply of H6XDA, immediately performing the supply of the other while bypassing a purging process. This procedure was performed 100 cycles. Composition in the surface of the substrate after the film-forming process was examined by XPS. The results are shown in FIG. 26.
As can be seen from
A film-forming process was performed which includes simultaneously supplying H6XDI and H6XDA to a substrate having a porous low dielectric constant film made of SiOC. Composition in the surface of the substrate after the film-forming process was examined by XPS. The results are shown in
In the above Evaluation Experiment 1, the substrate after the film-forming process was heated at 280 degrees C. for 5 minutes in a nitrogen gas atmosphere. The results of examining the absorptivity of a substrate before and after the film-forming process are shown in
Therefore, it is ensured that polyurea is not left in the low dielectric constant film at all by embedding polyurea in the pores of the low dielectric constant film by the above-described film-forming process, and by performing the removal process of the polyurea.
From the above results, it can be seen that, depending on a method of supplying raw material gases, it is possible to perform only the embedding of polyurea in pores of a low dielectric constant film, or form a polyurea film in addition to the embedding of the pores.
According to the present disclosure in some embodiments, a raw material for polymerization is supplied to a low dielectric constant film so as to embed a polymer (polyurea) having a urea bond in pores of the low dielectric constant film. After the low dielectric constant film is etched, the substrate is heated so as to depolymerize the polymer. Therefore, when etching the low dielectric constant film, the low electric constant film is protected by the polymer. After forming a via and before forming a trench, a filling material made of an organic substance is embedded in the via. Accordingly, since the low dielectric constant film is protected against active species during etching, occurrence of damage is suppressed.
Further, according to the present disclosure, a raw material for polymerization is supplied to a low dielectric constant film so as to embed a polymer (polyurea) having a urea bond in pores of a low dielectric constant film. After the low dielectric constant film is etched, the substrate is heated so as to depolymerize the polymer. Therefore, when etching the low dielectric constant film, the low electric constant film is protected by the polymer. A via is formed after a trench is formed. After forming the via, a mask formed inside the trench, which is used to form the via, is removed. At this time, since polyurea has been embedded in the low dielectric constant film, damage caused by plasma for removing the mask is suppressed.
While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the disclosures. Indeed, the embodiments described herein may be embodied in a variety of other forms. Furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the disclosures. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the disclosures.
Number | Date | Country | Kind |
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JP2017-239021 | Dec 2017 | JP | national |
This is a Divisional Application of U.S. patent application Ser. No. 16/213,119, filed Dec. 7, 2018, an application claiming benefit from Japanese Patent Application No. 2017-239021, filed on Dec. 13, 2017, in the Japan Patent Office, the disclosure of each of which is incorporated herein in its entirety by reference.
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Number | Date | Country | |
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Parent | 16213119 | Dec 2018 | US |
Child | 17137945 | US |