Semiconductor device packaging methods

Description

BACKGROUND
Field

Embodiments of the present disclosure generally relate to semiconductor device packages and methods of forming the same. More specifically, embodiments described herein relate to structures of thin-form-factor semiconductor device packages and methods of forming the same.

Description of the Related Art

Ongoing trends in the development of semiconductor device technology have led to semiconductor components having reduced sizes and increased circuit densities. In accordance with demands for continued scaling of semiconductor devices while improving performance capabilities, these components and circuits are integrated into complex 3D semiconductor device packages that facilitate a significant reduction in device footprint and enable shorter and faster connections between components. Such packages may integrate, for example, semiconductor chips and a plurality of other electronic components for mounting onto a circuit board of an electronic device.

Conventionally, semiconductor device packages have been fabricated on organic package substrates due to the ease in forming features and connections therein, as well as the relatively low package manufacturing costs associated with organic composites. However, as circuit densities are increased and semiconductor devices are further miniaturized, the utilization of organic package substrates becomes impractical due to limitations with material structuring resolution to sustain device scaling and associated performance requirements.

More recently, 2.5D and/or 3D packages have been fabricated utilizing passive silicon interposers as redistribution layers to compensate for some of the limitations associated with organic package substrates. Silicon interposer utilization is driven by the potential for high-bandwidth density, lower-power chip-to-chip communication, and heterogeneous integration requirements in advanced packaging applications. Yet, the formation of features in silicon interposers, such as through-silicon vias (TSVs), is still difficult and costly. In particular, high costs are imposed by high-aspect-ratio silicon via etching, chemical mechanical planarization, and semiconductor back end of line (BEOL) interconnection.

Therefore, what is needed in the art are improved semiconductor device package structures for advanced packaging applications and methods of forming the same.

SUMMARY

Embodiments of the present disclosure relate to structures for thin-form-factor semiconductor device packages and methods of forming the same.

In certain embodiments, a method of forming a semiconductor device package is provided. The method includes patterning one or more features into a silicon substrate, the one or more features comprising at least a first via; placing the substrate onto a first pre-structured insulating film, the first pre-structured insulating film comprising a second via, the second via aligned with the first via upon placement of the substrate; placing a second pre-structured insulating film over the substrate, the second pre-structured insulating film comprising a third via, the third via aligned with the first via upon placement of the second pre-structured insulating film; laminating the first pre-structured insulating film and the second pre-structured insulating film onto the substrate; curing the first pre-structured insulating film and the second pre-structured insulating film; and forming a conductive layer extending through at least the first via, the second via, and the third via.

In certain embodiments, a method of forming a semiconductor device package is provided. The method includes patterning one or more features into a silicon substrate, the one or more features comprising at least a first via; placing the substrate onto a first pre-structured insulating film, the first pre-structured insulating film comprising a second via, the second via aligned with the first via upon placement of the substrate; exposing the first pre-structured insulating film and the substrate to a first lamination process; placing a second pre-structured insulating film over the substrate, the second pre-structured insulating film comprising a third via, the third via aligned with the first via upon placement of the second pre-structured insulating film; exposing the first pre-structured insulating film, the substrate, and the second pre-structured insulating film to a second lamination process; curing the first pre-structured insulating film and the second pre-structured insulating film; and forming a conductive layer extending through at least the first via, the second via, and the third via.

BRIEF DESCRIPTION OF THE DRAWINGS

So that the manner in which the above recited features of the present disclosure can be understood in detail, a more particular description of the disclosure, briefly summarized above, may be had by reference to embodiments, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only exemplary embodiments and are therefore not to be considered limiting of its scope, and may admit to other equally effective embodiments.

FIG. 1 illustrates a flow diagram of a process for forming a semiconductor device package, according to embodiments described herein.

FIG. 2 illustrates a flow diagram of a process for substrate structuring for forming a semiconductor device package, according to embodiments described herein.

FIGS. 3A-3D schematically illustrate cross-sectional views of a substrate at different stages of the substrate structuring process depicted in FIG. 2, according to embodiments described herein.

FIGS. 4A-4F schematically illustrate cross-sectional views of a substrate at different stages of feature formation and subsequent damage removal, according to embodiments described herein.

FIGS. 5A-5F schematically illustrate cross-sectional views of a substrate at different stages of feature formation and subsequent damage removal, according to embodiments described herein.

FIGS. 6A-6E schematically illustrate cross-sectional views of a substrate at different stages of feature formation and subsequent damage removal, according to embodiments described herein.

FIGS. 7A-7D schematically illustrate cross-sectional views of a substrate at different stages of feature formation and subsequent damage removal, according to embodiments described herein.

FIG. 8 illustrates a schematic top view of a substrate structured with the processes depicted in FIGS. 2, 3A-3D, 4A-4F, 5A-5F, 6A-6E, and 7A-7D according to embodiments described herein.

FIG. 9 illustrates a flow diagram of a process for forming an embedded die assembly having through-assembly vias and contact holes, according to embodiments described herein.

FIGS. 10A-10K schematically illustrate cross-sectional views of the embedded die assembly at different stages of the process depicted in FIG. 9, according to embodiments described herein.

FIG. 11 illustrates a flow diagram of a process for forming an embedded die assembly having through-assembly vias and contact holes, according to embodiments described herein.

FIGS. 12A-12G schematically illustrate cross-sectional views of the embedded die assembly at different stages of the process depicted in FIG. 11, according to embodiments described herein.

FIG. 13 illustrates a flow diagram of a process for forming interconnections in an embedded die assembly, according to embodiments described herein.

FIGS. 14A-14H schematically illustrate cross-sectional views of the embedded die assembly at different stages of the interconnection formation process depicted in FIG. 13, according to embodiments described herein.

FIG. 15 illustrates a flow diagram of a process for forming a redistribution layer on an embedded die assembly followed by package singulation, according to embodiments described herein.

FIGS. 16A-16L schematically illustrate cross-sectional views of an embedded die assembly at different stages of forming a redistribution layer followed by package singulation, as depicted in FIG. 15, according to embodiments described herein.

FIG. 17 illustrates a flow diagram of another process for forming a redistribution layer on an embedded die assembly followed by singulation, according to embodiments described herein.

FIGS. 18A-18C schematically illustrate cross-sectional views of an embedded die assembly at different stages of forming a redistribution layer followed by package singulation, as depicted in FIG. 17, according to embodiments described herein.

FIG. 19 illustrates a flow diagram of a process for pre-structuring an insulating film separate from the substrate of the semiconductor device package, according to embodiments described herein.

FIGS. 20A-20C schematically illustrate cross-sectional views of an insulating film at different stages of the structuring process depicted in FIG. 19, according to embodiments described herein.

FIGS. 21A-21B schematically illustrate an exemplary apparatus for utilization with the process of FIG. 19 and FIGS. 20A-20C, according to embodiments described herein.

FIG. 22 illustrates a flow diagram of a process for forming an insulation layer over a substrate, according to embodiments described herein.

FIGS. 23A-23G schematically illustrate cross-sectional views of the embedded die assembly at different stages of the process depicted in FIG. 22, according to embodiments described herein.

FIGS. 24A and 24B schematically illustrate cross-sectional views of dynamic random access memory (DRAM) stacks including a plurality of semiconductor device packages formed utilizing the processes depicted in FIGS. 1-23G, according to embodiments described herein.

To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements and features of one embodiment may be beneficially incorporated in other embodiments without further recitation.

DETAILED DESCRIPTION

The present disclosure relates to methods and apparatus for forming a thin-form-factor semiconductor device package. In certain embodiments, a substrate is structured, or shaped, by micro-blasting to enable formation of interconnections therethrough. In another embodiment, a substrate is structured by direct laser patterning. The substrate is thereafter utilized as a package frame for forming one or more semiconductor device packages with dies disposed therein. In still other embodiments, the substrate is utilized as a frame for a semiconductor device stack, such as a dynamic random-access memory (DRAM) stack.

The methods and apparatus disclosed herein further include novel thin-form-factor semiconductor device packages intended to replace more conventional package structures utilizing glass fiber-filled epoxy frames and silicon interposers as redistribution layers. Generally, the scalability of current packages is limited by the rigidity and planarity of the materials utilized to form the various package structures (e.g., epoxy molding compound, FR-4 and FR-5 grade woven fiberglass cloth with epoxy resin binders, and the like). The intrinsic properties of these materials cause difficulty in patterning fine (e.g., less than 50 μm) features therein. Furthermore, as a result of the thermal properties of current package materials, coefficient of thermal expansion (CTE) mismatch may occur between the packaging substrate, the molding compound, and any semiconductor dies integrated therein and thus, current package structures necessitate larger solder bumps with greater spacing to mitigate any warpage caused by the CTE mismatch. Accordingly, conventional packages are characterized by low die-to-package area ratios and low through-package bandwidths, resulting in decreased overall power efficiency. The methods and apparatus disclosed herein provide semiconductor device packages that overcome many of the disadvantages associated with conventional package architectures described above.

FIG. 1 illustrates a flow diagram of a representative method 100 of forming a thin-form-factor semiconductor device package. The method 100 has multiple operations 110, 120, 130, and 140. Each operation is described in greater detail with reference to FIGS. 2-16L. The method may include one or more additional operations which are carried out before any of the defined operations, between two of the defined operations, or after all of the defined operations (except where the context excludes the possibility).

In general, the method 100 includes structuring a substrate to be used as a package frame at operation 110, further described in greater detail with reference to FIGS. 2, 3A-3D, 4A-4F, 5A-5F, 6A-6E, 7A-7D, and 8. At operation 120, an embedded die assembly having one or more embedded dies and an insulating layer is formed, which is described in greater detail with reference to FIGS. 9 and 10A-10K, FIGS. 11 and 12A-12G, and FIGS. 22 and 23A-23G. At operation 130, one or more interconnections are formed in and/or through the embedded die assembly for interconnection of embedded die-frame sets, which is described in greater detail with reference to FIGS. 13 and 14A-14H. At operation 140, a first redistribution layer is formed on the embedded die assembly to relocate contact points of the interconnections to desired lateral locations on the embedded die assembly surface. In some embodiments, one or more additional redistribution layers may be formed in addition to the first redistribution layer before individual packages are singulated from the embedded die assembly, which is described in greater detail with reference to FIGS. 15 and 16A-16L, and FIGS. 1 and 18A-18C.

FIG. 2 illustrates a flow diagram of a representative method 200 for structuring a substrate to be utilized as a frame during the formation of a semiconductor device package. FIGS. 3A-3D schematically illustrate cross-sectional views of a substrate 302 at different stages of the substrate structuring process 200 represented in FIG. 2. Therefore, FIG. 2 and FIGS. 3A-3D are herein described together for clarity.

The method 200 begins at operation 210 and corresponding FIG. 3A. The substrate 302 is formed of any suitable frame material including but not limited to a III-V compound semiconductor material, silicon, crystalline silicon (e.g., Si<100> or Si<111>), silicon oxide, silicon germanium, doped or undoped silicon, doped or undoped polysilicon, silicon nitride, quartz, borosilicate glass, glass, sapphire, alumina, and ceramic. In certain embodiments, the substrate 302 is a monocrystalline p-type or n-type silicon substrate. In certain embodiments, the substrate 302 is a polycrystalline p-type or n-type silicon substrate. In another embodiment, the substrate 302 is a p-type or n-type silicon solar substrate. The substrate 302 may further have a polygonal or circular shape. For example, the substrate 302 may include a substantially square silicon substrate having lateral dimensions between about 120 mm and about 180 mm, with or without chamfered edges. In another example, the substrate 302 may include a circular silicon-containing wafer having a diameter between about 20 mm and about 700 mm, such as between about 100 mm and about 500 mm, for example about 300 mm.

Unless otherwise noted, embodiments and examples described herein are conducted on substrates having a thickness between about 50 μm and about 1000 μm, such as between about 90 μm and about 780 μm. For example, the substrate 302 has a thickness between about 100 μm and about 300 μm, such as a thickness between about 110 μm and about 200 μm. In another example, the substrate 302 has a thickness between about 60 μm and about 160 μm, such as a thickness between about 80 μm and about 120 μm.

Prior to operation 210, the substrate 302 may be sliced and separated from a bulk material by wire sawing, scribing and breaking, mechanical abrasive sawing, or laser cutting. Slicing typically causes mechanical defects or deformities in substrate surfaces formed therefrom, such as scratches, micro-cracking, chipping, and other mechanical defects. Thus, the substrate 302 is exposed to a first damage removal process at operation 210 to smoothen and planarize surfaces thereof and remove any mechanical defects in preparation for later structuring and packaging operations. In some embodiments, the substrate 302 may further be thinned by adjusting the process parameters of the first damage removal process. For example, a thickness of the substrate 302 may be decreased with increased exposure to the first damage removal process.

The damage removal process at operation 210 includes exposing the substrate 302 to a substrate polishing process and/or an etch process followed by rinsing and drying processes. In some embodiments, operation 210 includes a chemical mechanical polishing (CMP) process. In certain embodiments, the etch process is a wet etch process including a buffered etch process that is selective for the removal of desired materials (e.g., contaminants and other undesirable compounds). In other embodiments, the etch process is a wet etch process utilizing an isotropic aqueous etch process. Any suitable wet etchant or combination of wet etchants may be used for the wet etch process. In certain embodiments, the substrate 302 is immersed in an aqueous HF etching solution for etching. In another embodiment, the substrate 302 is immersed in an aqueous KOH etching solution for etching.

In some embodiments, the etching solution is heated to a temperature between about 30° C. and about 100° C. during the etch process, such as between about 40° C. and about 90° C. For example, the etching solution is heated to a temperature of about 70° C. In still other embodiments, the etch process at operation 210 is a dry etch process. An example of a dry etch process includes a plasma-based dry etch process. The thickness of the substrate 302 is modulated by controlling the time of exposure of the substrate 302 to the etchants (e.g., the etching solution) used during the etch process. For example, a final thickness of the substrate 302 is reduced with increased exposure to the etchants. Alternatively, the substrate 302 may have a greater final thickness with decreased exposure to the etchants.

At operations 220 and 230, the now planarized and substantially defect-free substrate 302 has one or more features, such as vias 303 and cavities 305, patterned therein and smoothened (one cavity 305 and four vias 303 are depicted in the lower cross-section of the substrate 302 in FIG. 3B). The vias 303 are utilized to form direct contact electrical interconnections through the substrate 302 and the cavities 305 are utilized to receive and enclose (i.e., embed) one or more semiconductor dies therein. FIGS. 4A-4C, 5A-5C, 6A-6C, and 7A-7B illustrate cross-sectional views of the substrate 302 at different stages of the feature formation and damage or defect removal (e.g., smoothening) processes according to embodiments described herein. Thus, operations 220 and 230 will now be described in greater detail with reference to FIGS. 4A-4C, 5A-5C, 6A-6C, and 7A-7B.

In embodiments where the substrate 302 has a thickness less than about 200 μm, such as a thickness of about 100 μm, or a thickness of about 50 μm, the substrate 302 may first be coupled to an optional carrier plate 406 as depicted in FIGS. 4A and 5A. The carrier plate 406 provides mechanical support for the substrate 302 during the substrate structuring process 200 and prevents the substrate 302 from breaking. The carrier plate 406 is formed of any suitable chemically and thermally stable rigid material including but not limited to glass, ceramic, metal, or the like. The carrier plate 406 has a thickness between about 1 mm and about 10 mm, such as between about 2 mm and about 5 mm. In certain embodiments, the carrier plate 406 has a textured surface. In other embodiments, the carrier plate 406 has a polished or smoothened surface.

The substrate 302 may be coupled to the carrier plate 406 via an adhesive layer 408. The adhesive layer 408 is formed of any suitable temporary bonding material, including but not limited to wax, glue, or similar bonding material. The adhesive layer 408 is applied onto the carrier plate 406 by mechanical rolling, pressing, lamination, spin coating, or doctor-blading. In certain embodiments, the adhesive layer 408 is a water-soluble or solvent-soluble adhesive layer. In other embodiments, the adhesive layer 408 is a UV release adhesive layer. In still other embodiments, the adhesive layer 408 is a thermal release adhesive layer. In such embodiments, the bonding properties of the adhesive layer 408 degrade upon exposure to heat treatment, for example, by exposing the adhesive layer 408 to temperatures above 110° C., such as above 150° C. The adhesive layer 408 may further include one or more layers of additional films (not shown), such as a liner, a base film, a pressure-sensitive film, and other suitable layers.

In some embodiments, after bonding of the substrate 302 to the carrier plate 406, a resist film is applied to the substrate 302 to form a resist layer 404, depicted in FIGS. 4A and 5A. In embodiments where the substrate 302 has a thickness of greater than about 200 μm, such as a thickness of about 250 μm, the resist layer 404 is formed on the substrate 302 without first coupling the substrate 302 to the carrier plate 406. The resist layer 404 is used to transfer a desired pattern to the substrate 302 upon which the resist layer 404 is formed during subsequent processing operations. After being patterned, the resist layer 404 protects selected regions of the underlying substrate 302 during later structuring operations.

The substrate 302 generally has a substantially planar surface upon which the resist layer 404 is formed. In some embodiments, such as those illustrated in FIG. 5A, the resist layer 404 is bonded to the substrate 302 via a resist adhesive layer 409. The resist adhesive layer 409 is formed of any suitable temporary bonding material, including but not limited to polyvinyl alcohol, triester with 2-ethyl-2-(hydroxymethyl)-1,3-propanediol, and other water- or solvent-soluble materials. In certain embodiments, the resist adhesive layer 409 is formed of a different material than the adhesive layer 408. In certain embodiments, the resist adhesive layer 409 is substantially similar in composition to the adhesive layer 408. The resist adhesive layer 409 is applied onto the substrate 302 by mechanical rolling, pressing, lamination, spin coating, or doctor-blading. In other embodiments, the resist layer 404 is formed of a temporary bonding material such as polyvinyl alcohol, thus enabling the resist layer 404 to be directly applied and bonded to the surface of the substrate 302. The resist layer 404 may include one or more layers, for example, a first resist layer and a second resist layer (not shown).

In certain embodiments, such as the embodiment illustrated in FIG. 4A, the resist layer 404 is a photosensitive layer (e.g., photoresist). The resist layer 404 may include a solvent, a photoresist resin, and a photoacid generator. The photoresist resin may be any positive photoresist resin or any negative photoresist resin. Representative photoresist resins include acrylates, novolak resins, poly(methylmethacrylates), and poly(olefin sulfones). Other photoresist resins may also be used. Upon exposure to electromagnetic radiation, the photoacid generator generates charged species, such as acid cations and anions. The photoacid generator may also generate polarized species. The photoacid generator sensitizes the resin to electromagnetic radiation. Representative photoacid generators include sulfonate compounds, such as, for example, sulfonated salts, sulfonated esters, and sulfonyloxy ketones. Other suitable photoacid generators include onium salts, such as aryl-diazonium salts, halonium salts, aromatic sulfonium salts and sulfoxonium salts or selenium salts. Other representative photoacid generators include nitrobenzyl esters, s-triazine derivatives, ionic iodonium sulfonates, perfluoroalkanesulfonates, aryl triflates and derivatives and analogs thereof, pyrogallol derivatives, and alkyl disulfones. Other photoacid generators may also be used. In certain embodiments, such as the embodiment illustrated in FIG. 5A, the resist layer 404 is a laser-sensitive resist.

After formation of the resist layer 404, the substrate 302 having the resist layer 404 formed thereon is exposed to electromagnetic radiation to pattern the resist layer 404, depicted in FIGS. 4B and 5B. In the embodiment illustrated by FIG. 4B, the substrate 302 having the resist layer 404 formed thereon is exposed to electromagnetic radiation in the ultraviolet (UV) range. Portions of the resist layer 404 are selectively exposed and portions of the resist layer 404 are selectively unexposed to the UV radiation. Upon exposure to the UV radiation, the selectively exposed portions of the resist layer 404 are structurally weakened (illustrated by hatching) while the selectively unexposed portions maintain their structural integrity. In certain embodiments, a mask 412 having a desired pattern is formed on or adjacent to the photosensitive resist layer 404 prior to UV radiation exposure. In other embodiments, the mask 412 is a reticle positioned between the resist layer 404 and the UV radiation source. The mask 412 is configured to transfer a desired pattern of UV radiation to the resist layer 404. The mask 412 is formed of any suitable polymeric material, including but not limited to PTFE, PVDF, FFP, polyimide, or the like.

In the embodiment illustrated by FIG. 5B, the substrate 302 having the laser-sensitive resist layer 404 formed thereon is exposed to electromagnetic radiation generated by a laser source 307 instead of a UV radiation source. As such, patterning is accomplished by targeted laser ablation, without the use of a mask. The laser source 307 may be any suitable type of laser for patterning of the resist layer 404. In some examples, the laser source 307 is a femtosecond green laser. In other examples, the laser source 307 is a femtosecond UV laser. The laser source 307 generates a continuous or pulsed laser beam 310 for patterning of the resist layer 404. For example, the laser source 307 may generate a pulsed laser beam 310 having a frequency between 100 kHz and 1200 kHz, such as between about 200 kHz and about 1000 kHz. The laser source 307 is generally configured to form any desired pattern in the resist layer 404. It is further contemplated that the electromagnetic radiation at operation may alternatively include an electron beam or an ion beam instead of a laser beam.

The resist layer 404 may be formed of any material having a suitable hardness after the resist layer 404 has been patterned, such as, for example, after exposing a negative photoresist to electromagnetic radiation to cause cross-linking of the material in the resist. In general, the resist layer 404 needs to have one or more desirable mechanical properties after the resist layer 404 has been patterned (e.g., deposited, exposed and developed). In certain embodiments, the resist layer 404 is formed of a material having a Shore A scale hardness value of between 40 and 90, such as between 60 and 70 after patterning. For example, the resist layer 404 is formed of a material having a Shore A scale hardness value of about 65 after patterning. In certain embodiments, the resist layer 404 is formed of a material having a tensile strength of between about 0.5 MPa and about 10 MPa, such as between about 1 MPa and about 8 MPa after patterning. For example, the resist layer 404 may be formed of a material having a tensile strength of about 7 MPa after patterning. In certain embodiments, the resist layer 404 is formed of a polydimethylsiloxane material. In other embodiments, the resist layer 404 is formed of polyvinyl alcohol, triester with 2-ethyl-2-(hydroxymethyl)-1,3-propanediol, or the like.

Following patterning of the resist layer 404, the substrate 302 having the resist layer 404 formed thereon is micro-blasted to form a desired pattern in the substrate 302 as depicted in FIGS. 4C and 5C. During the micro-blasting process, a stream of powder particles 309 is propelled toward the substrate 302 by use of a high-pressure carrier gas to dislodge exposed portions of the substrate 302 and/or layers formed thereon. The micro-blasting process is performed using any suitable substrate abrading system.

The micro-blasting process is determined by the material properties of the powder particles 309, the momentum of the powder particles that strike the exposed surface of the substrate 302 and the material properties of the substrate 302 along with, when applicable, the selectively-exposed portions of the resist layer 404. To achieve desired substrate patterning characteristics, adjustments are made to the type and size of the powder particles 309, the size and distance of the abrading system's applicator nozzle to the substrate 302, the pressure, which correlates to the velocity and flow rate, of the carrier gas utilized to propel the powder particles 309, and the density of the powder particles 309 in the fluid stream. For example, a desired fluid pressure of the carrier gas used for propelling the powder particles 309 toward the substrate 302 for a desired fixed micro-blasting device nozzle orifice size is determined based on the materials of the substrate 302 and the powder particles 309. In certain embodiments, the fluid pressure utilized to micro-blast the substrate 302 ranges from between about 50 psi and about 150 psi, such as between about 75 psi and about 125 psi, to achieve a carrier gas and particle velocity of between about 300 and about 1000 meters per second (m/s) and/or a flow rate of between about 0.001 and about 0.002 cubic meters per second (m³/s). For example, the fluid pressure of an inert gas (e.g., nitrogen (N₂), CDA, argon) that is utilized to propel the powder particles 309 during micro-blasting is about 95 psi to achieve a carrier gas and particle velocity of about 2350 m/s. In certain embodiments, the applicator nozzle utilized to micro-blast the substrate 302 has an inner diameter of between about 0.1 and about 2.5 millimeters (mm) that is disposed at a distance between about 1 mm and about 5 mm from the substrate 302, such as between about 2 mm and about 4 mm. For example, the applicator nozzle is disposed at a distance of about 3 mm from the substrate 302 during micro-blasting.

Generally, the micro-blasting process is performed with powder particles 309 having a sufficient hardness and high melting point to prevent particle adhesion upon contact with the substrate 302 and/or any layers formed thereon. For example, the micro-blasting process is performed utilizing powder particles 309 formed of a ceramic material. In certain embodiments, the powder particles 309 utilized in the micro-blasting process are formed of aluminum oxide (Al₂O₃). In another embodiment, the powder particles 309 are formed of silicon carbide (SiC). Other suitable materials for the powder particles 309 are also contemplated. The powder particles 309 generally range in size between about 15 μm and about 60 μm in diameter, such as between about 20 μm and about 40 μm in diameter. For example, the powder particles 309 are an average particle size of about 27.5 μm in diameter. In another example, the powder particles 309 have an average particle size of about 23 μm in diameter.

The effectiveness of the micro-blasting process at operation 220 and depicted in FIGS. 4C and 5C further depends on the material characteristics of the resist layer 404. Utilizing a material having too high of a Shore A Scale hardness may cause unwanted ricocheting of the powder particles 309 between sidewalls of the resist layer 404, thus reducing the velocity upon which the powder particles 309 bombard the substrate 302, and ultimately reducing the effectiveness of the powder particles 309 in eroding or dislodging exposed regions of the substrate 302. Conversely, utilizing a material having too low of a Shore A Scale hardness may cause unwanted adhesion of the powder particles 309 to the resist layer 404. It is contemplated that a Shore A Scale hardness value of between about 40 and about 90 is utilized for the resist layer 404 material, as described above.

In embodiments where the resist layer 404 is a photoresist, such as the embodiment depicted in FIG. 4C, the substrate 302 remains unexposed at the start of the micro-blasting process. Thus, the powder particles 309 first bombard a surface of the photoresist, causing material from the UV-exposed and structurally weakened portions of the photoresist to be dislodged and removed. The powder particles 309 eventually penetrate through and remove the brittle UV-exposed portions to form voids in the resist layer 404, thus exposing desired regions of the substrate 302 while other regions remain shielded by the UV-unexposed portions of the photoresist. Micro-blasting is then continued until the powder particles 309 dislodge and remove a desired amount or depth of material from the exposed regions of the substrate 302, thus forming a desired pattern in the substrate 302. In embodiments where the resist layer 404 is patterned by laser ablation, such as the embodiment depicted in FIG. 5C, desired regions of the substrate 302 are already exposed through voids in the resist layer 404 prior to the micro-blasting process. Thus, minimal to no removal of the resist layer 404 is contemplated during micro-blasting.

The processes described above for forming features in the substrate 302 at operation 220 may cause unwanted mechanical defects on the surfaces of the substrate 302, such as chipping and cracking. Therefore, after performing operation 220 to form desired features in the substrate 302, the substrate 302 is exposed to a second damage removal and cleaning process at operation 230 to smoothen the surfaces of the substrate 302 and remove unwanted debris, followed by a stripping of the resist layer 404 and optional debonding of the substrate 302 from the carrier plate 406. FIGS. 4D-4F and 5D-5F illustrate cross-sectional views of the substrate 302 at different stages of the second damage removal, cleaning, resist stripping, and substrate debonding processes according to embodiments described herein. Thus, operation 230 will now be described in greater detail with reference to FIGS. 4D-4F and 5D-5F.

The second damage removal process at operation 230 is substantially similar to the first damage removal process at operation 210 and includes exposing the substrate 302 to an etch process, followed by rinsing and drying. The etch process proceeds for a predetermined duration to smoothen the surfaces of the substrate 302, and in particular, the surfaces exposed to the micro-blasting process. In another aspect, the etch process is utilized to remove undesired debris remaining from the micro-blasting process. Leftover powder particles adhering to the substrate 302 may be removed during the etch process. FIGS. 4D and 5D illustrate the substrate 302 after removal of debris and surface smoothening.

In certain embodiments, the etch process is a wet etch process utilizing a buffered etch process preferentially etching the substrate surface versus the resist layer 404 material. For example, the buffered etch process is selective for polyvinyl alcohol. In other embodiments, the etch process is a wet etch process utilizing an aqueous etch process. Any suitable wet etchant or combination of wet etchants may be used for the wet etch process. In certain embodiments, the substrate 302 is immersed in an aqueous HF etching solution for etching. In another embodiment, the substrate 302 is immersed in an aqueous KOH etching solution for etching. The etching solution may further be heated to a temperature between about 40° C. and about 80° C. during the etch process, such as between about 50° C. and about 70° C. For example, the etching solution is heated to a temperature of about 60° C. The etch process may be isotropic or anisotropic. In still other embodiments, the etch process at operation 230 is a dry etch process. An example of a dry etch process includes a plasma-based dry etch process.

After debris has been removed and the substrate surfaces have been smoothed, the substrate 302 is exposed to a resist stripping process. The stripping process is utilized to de-bond the resist layer 404 from the substrate 302, as depicted in FIGS. 4E and 5E. In certain embodiments, a wet process is used to de-bond the resist layer 404 from the substrate 302 by dissolving/solubilizing the resist adhesive layer 409. Other types of etch process are also contemplated for releasing the resist adhesive layer 409. In certain embodiments, a mechanical rolling process is used to physically peel off the resist layer 404 or the resist adhesive layer 409 from the substrate 302. In certain embodiments, an ashing process is used to remove the resist layer 404 from the substrate 302 by use of, for example, an oxygen plasma assisted process.

After the resist stripping process, the substrate 302 is exposed to an optional carrier de-bonding process as depicted in FIGS. 4F and 5F. The utilization of the carrier de-bonding process is dependent on whether the substrate 302 is coupled to the carrier plate 406 and the type of bonding material utilized to couple the substrate 302 and the carrier plate 406. As described above and depicted in FIGS. 4A-4F and 5A-5F, in embodiments where the substrate 302 has a thickness of less than about 200 μm, the substrate 302 is coupled to the carrier plate 406 for mechanical support during the formation of features at operation 220. The substrate 302 is coupled to the carrier plate 406 via the adhesive layer 408. Thus, after micro-blasting and subsequent substrate etch and resist stripping, the substrate 302 coupled to the carrier plate 406 is exposed to the carrier de-bonding process to de-bond the substrate 302 from the carrier plate 406 by releasing the adhesive layer 408.

In certain embodiments, the adhesive layer 408 is released by exposing the substrate 302 to a bake process. The substrate 302 is exposed to temperatures of between about 50° C. and about 300° C., such as temperatures between about 100° C. and about 250° C. For example, the substrate 302 is exposed to a temperature of between about 150° C. and about 200° C., such as about 160° C. for a desired period of time in order to release the adhesive layer 408. In other embodiments, the adhesive layer 408 is released by exposing the substrate 302 to UV radiation.

FIGS. 4F and 5F illustrate the substrate 302 after completion of operations 210-230. The cross-sections of the substrate 302 in FIGS. 4F and 5F depict a single cavity 305 formed therethrough and surrounded on either lateral side by two vias 303. A schematic top view of the substrate 302 upon completion of the operations described with reference to FIGS. 4A-4F and 5A-5F is depicted in FIG. 8, described in further detail below.

FIGS. 6A-6E illustrate schematic, cross-sectional views of a substrate 302 during an alternative sequence for operations 220 and 230 similar to those described above. The alternative sequence depicted for operations 220 and 230 involves patterning the substrate 302 on two major opposing surfaces as compared to only one surface, thus enabling increased efficiency during structuring of the substrate 302. The embodiment depicted in FIGS. 6A-6E includes substantially all of the processes as described with reference to FIGS. 4A-4F and 5A-5F. For example, FIG. 6A corresponds with FIGS. 4A and 5A, FIG. 6B corresponds with FIGS. 4B and 5B, FIG. 6C corresponds with FIGS. 4C and 5C, FIG. 6D corresponds with FIGS. 4D and 5D, and FIG. 6E corresponds with FIGS. 4F and 5F. However, unlike the previous embodiments, the embodiment of operation 220 depicted in FIGS. 6A-6E includes a substrate 302 having two resist layers 404 formed on major opposing surfaces 606, 608 thereof, as opposed to one resist layer 404 formed on a single surface. Therefore, the processes performed during operations 210-230 will need to be performed at the same time (i.e., simultaneously) or one after the other (i.e., sequentially) on both sides of the substrate during each operation. While FIGS. 6A-6E only illustrate the formation of vias 303, the processes described herein can also be used to form cavities 305, or cavities 305 and vias 303.

Accordingly, after exposing the resist layer 404 on one side of the substrate 302 to electromagnetic radiation for patterning, such as the side including the surface 608, the substrate 302 may be optionally flipped so that the resist layer 404 on the opposing surface 606 is also exposed to the electromagnetic radiation for patterning, as depicted in FIG. 6B. Similarly, after performing the micro-blasting process on the surface 608 of the substrate 302, the substrate 302 may be optionally flipped so that micro-blasting may be performed against the opposing surface 606 as depicted in FIG. 6C. Thereafter, the substrate 302 is exposed to a second damage removal and cleaning process and a resist stripping process, depicted in FIGS. 6D-6E. By utilizing two resist layers 404 on major opposing surfaces 606, 608 of the substrate 302 and performing the micro-blasting process against both surfaces 606 and 608, potential tapering of the features formed therein by the micro-blasting process may be reduced or eliminated and efficiency of the process used to structure the substrate 302 can be increased.

FIGS. 7A-7D illustrate schematic, cross-sectional views of a substrate 302 during another alternative sequence for operations 220 and 230, wherein a desired pattern is formed in the substrate 302 by direct laser ablation. As depicted in FIG. 7A, the substrate 302, such as a solar substrate or even a semiconductor wafer, is placed on a stand 706 of a laser ablation system (not shown). The stand 706 may be any suitable rigid and planar or textured (e.g., structured) surface for providing mechanical support for the substrate 302 during laser ablation. In some embodiments, the stand 706 includes an electrostatic chuck for electrostatic chucking of the substrate 302 to the stand 706. In some embodiments, the stand 706 includes a vacuum chuck for vacuum chucking of the substrate 302 to the stand 706. After placing the substrate 302 on the stand 706, a desired pattern is formed in the substrate 302 by laser ablation, depicted in FIG. 7B.

The laser ablation system may include any suitable type of laser source 307 for patterning the substrate 302. In some examples, the laser source 307 is an infrared (IR) laser. In some examples the laser source 307 is a picosecond UV laser. In other examples, the laser source 307 is a femtosecond UV laser. In yet other examples, the laser source 307 is a femtosecond green laser. The laser source 307 generates a continuous or pulsed laser beam 310 for patterning of the substrate 302. For example, the laser source 307 may generate a pulsed laser beam 310 having a frequency between 5 kHz and 500 kHz, such as between 10 kHz and about 200 kHz. In one example, the laser source 307 is configured to deliver a pulsed laser beam at a wavelength of between about 200 nm and about 1200 nm and at a pulse duration between about 10 ns and about 5000 ns with an output power of between about 10 Watts and about 100 Watts. The laser source 307 is configured to form any desired pattern and features in the substrate 302, including the cavities 305 and the vias 303.

Similar to micro-blasting, the process of direct laser patterning of the substrate 302 may cause unwanted mechanical defects on the surfaces of the substrate 302, including chipping and cracking. Thus, after forming desired features in the substrate 302 by direct laser patterning, the substrate 302 is exposed to a second damage removal and cleaning process substantially similar to embodiments described above. FIGS. 7C-7D illustrate the structured substrate 302 before and after performing the second damage removal and cleaning process, resulting in a smoothened substrate 302 having a cavity 305 and four vias 303 formed therein.

Referring back now to FIG. 2 and FIG. 3D, after removal of mechanical defects in the substrate 302 at operation 230, in certain embodiments, the substrate 302 may be exposed to an oxidation process at operation 240 to grow or deposit an insulating oxide film (i.e. layer) 314 on desired surfaces thereof. For example, the oxide film 314 may be formed on all surfaces of the substrate 302 such that it surrounds the substrate 302. The insulating oxide film 314 acts as a passivating layer on the substrate 302 and provides a protective outer barrier against corrosion and other forms of damage. In certain embodiments, the oxidation process is a thermal oxidation process. The thermal oxidation process is performed at a temperature of between about 800° C. and about 1200° C., such as between about 850° C. and about 1150° C. For example, the thermal oxidation process is performed at a temperature of between about 900° C. and about 1100° C., such as a temperature of between about 950° C. and about 1050° C. In certain embodiments, the thermal oxidation process is a wet oxidation process utilizing water vapor as an oxidant. In certain embodiments, the thermal oxidation process is a dry process utilizing molecular oxygen as the oxidant. It is contemplated that the substrate 302 may be exposed to any suitable oxidation process at operation 240 to form the oxide film 314 thereon. The oxide film 314 generally has a thickness between about 100 nm and about 3 μm, such as between about 200 nm and about 2.5 μm. For example, the oxide film 314 has a thickness between about 300 nm and about 2 μm, such as about 1.5 μm.

In certain embodiments, the substrate 302 is exposed to a metallization process at operation 240 to form a metal cladding layer 316 on one or more surfaces thereof. In certain embodiments, the metal cladding layer 316 is formed on substantially all exterior surfaces of the substrate 302 such that the metal cladding layer 114 substantially surrounds the substrate 302. The metal cladding layer 316 acts as a reference layer (e.g., grounding layer or a voltage supply layer) and is disposed on the substrate 302 to protect subsequently formed interconnections from electromagnetic interference and also shield electric signals from the semiconductor material (Si) that is used to form the substrate 302. In certain embodiments, the metal cladding layer 316 includes a conductive metal layer that includes nickel, aluminum, gold, cobalt, silver, palladium, tin, or the like. In certain embodiments, the metal cladding layer 316 includes a metal layer that includes an alloy or pure metal that includes nickel, aluminum, gold, cobalt, silver, palladium, tin, or the like. The metal cladding layer 316 generally has thickness between about 50 nm and about 10 μm such as between about 100 nm and about 5 μm.

In certain examples, at least a portion of the metal cladding layer 316 includes a deposited nickel (Ni) layer formed by direct displacement or displacement plating on the surfaces of the substrate 302 (e.g., n-Si substrate or p-Si substrate). For example, the substrate 302 is exposed to a nickel displacement plating bath having a composition including 0.5 M NiSO₄and NH₄OH at a temperature between about 60° C. and about 95° C. and a pH of about 11, for a period of between about 2 and about 4 minutes. The exposure of the silicon substrate 302 to a nickel ion-loaded aqueous electrolyte in the absence of reducing agent causes a localized oxidation/reduction reaction at the surface of the substrate 302, thus leading to plating of metallic nickel thereon. Accordingly, nickel displacement plating enables selective formation of thin and pure nickel layers on the silicon material of substrate 400 utilizing stable solutions. Furthermore, the process is self-limiting and thus, once all surfaces of the substrate 302 are plated (e.g., there is no remaining silicon upon which nickel can form), the reaction stops. In certain embodiments, the nickel metal cladding layer 316 may be utilized as a seed layer for plating of additional metal layers, such as for plating of nickel or copper by electroless and/or electrolytic plating methods. In further embodiments, the substrate 302 is exposed to an SC-1 pre-cleaning solution and a HF oxide etching solution prior to a nickel displacement plating bath to promote adhesion of the nickel metal cladding layer 316 thereto.

In subsequent packaging operations, the metal cladding layer 316 may be coupled to one or more connection points, e.g., interconnections, formed within the resulting semiconductor device package for connecting the metal cladding layer 316 to a common ground. For example, interconnections may be formed on one side or opposing sides of the resulting semiconductor device package to connect the metal cladding layer 316 to ground. Alternatively, the metal cladding layer 316 may be connected to a reference voltage, such as a power voltage.

FIG. 8 illustrates a schematic top view of an exemplary structured substrate 302 according to one embodiment. The substrate 302 may be structured during operations 210-240 as described above with reference to FIGS. 2, 3A-3D, 4A-4F, 5A-5F, 6A-6E, and 7A-7D. The substrate 302 is illustrated as having two quadrilateral cavities 305, and each cavity 305 is surrounded by a plurality of vias 303. In certain embodiments, each cavity 305 is surrounded by two rows 801, 802 of vias 303 arranged along each edge 306a-d of the quadrilateral cavity 305. Although ten vias 303 are depicted in each row 801, 802, it is contemplated that any desired number of vias 303 may be formed in a row. Further, any desired number and arrangement of cavities 305 and vias 303 may be formed in the substrate 302 during operation 220. For example, the substrate 302 may have more or less than two cavities 305 formed therein. In another example, the substrate 302 may have more or less than two rows of vias 303 formed along each edge 306a-d of the cavities 305. In another example, the substrate 302 may have two or more rows of vias 303 wherein the vias 303 in each row are staggered and unaligned with vias 303 of another row.

In certain embodiments, the cavities 305 and vias 303 have a depth equal to the thickness of the substrate 302, thus forming holes on opposing surfaces of the substrate 302 (e.g., through the thickness of the substrate 302). For example, the cavities 305 and the vias 303 formed in the substrate 302 may have a depth of between about 50 μm and about 1 mm, such as between about 100 μm and about 200 μm, such as between about 110 μm and about 190 μm, depending on the thickness of the substrate 302. In other embodiments, the cavities 305 and/or the vias 303 may have a depth equal to or less than the thickness of the substrate 302, thus forming a hole in only one surface (e.g., side) of the substrate 302.

In certain embodiments, each cavity 305 has lateral dimensions ranging between about 3 mm and about 50 mm, such as between about 8 mm and about 12 mm, such as between about 9 mm and about 11 mm, depending on the size of one or more semiconductor dies 1026 (shown in FIG. 10B) to be embedded therein during package fabrication (described in greater detail below). Semiconductor dies generally include a plurality of integrated electronic circuits that are formed on and/or within a substrate material, such as a piece of semiconductor material. In certain embodiments, the cavities 305 are sized to have lateral dimensions substantially similar to that of the dies 1026 to be embedded therein. For example, each cavity 305 is formed having lateral dimensions exceeding those of the dies 1026 by less than about 150 μm, such as less than about 120 μm, such as less than 100 μm. Having a reduced variance in the size of the cavities 305 and the dies 1026 to be embedded therein reduces the amount of gap-fill material utilized thereafter.

In certain embodiments, each via 303 has a diameter ranging between about 50 μm and about 200 μm, such as between about 60 μm and about 130 μm, such as between about 80 μm and 110 μm. A minimum pitch 807 between the center of a via 303 in row 801 and a center of an adjacent via 303 in row 802 is between about 70 μm and about 200 μm, such as between about 85 μm and about 160 μm, such as between about 100 μm and 140 μm. Although embodiments are described with reference to FIG. 8, the substrate structuring processes described above with reference to operations 210-240 and FIGS. 2, 3A-3B, 4A-4C, 5A-5C, 6A-6C, and 7A-7B may be utilized to form patterned features in the substrate 302 having any desired depth, lateral dimensions, and morphologies.

After structuring of the substrate 302, one or more packages are formed around the substrate 302 by utilizing the substrate 302 as a frame. FIGS. 9 and 11 illustrate flow diagrams of representative methods 900 and 1100, respectively, for fabricating an intermediary embedded die assembly 1002 around the substrate 302 prior to final package formation. FIGS. 10A-10K schematically illustrate cross-sectional views of the substrate 302 at different stages of the method 900 depicted in FIG. 9, and FIGS. 12A-12G schematically illustrate cross-sectional views of the substrate 302 at different stages of the method 1100 depicted in FIG. 11. For clarity, FIG. 9 and FIGS. 10A-10K are herein described together and FIG. 11 and FIGS. 12A-12G are herein described together.

Generally, the method 900 begins at operation 902 and FIG. 10A wherein a first side 1075 (e.g., surface 606, which may have an oxide layer or metal cladding layer formed thereon) of the substrate 302, now having desired features formed therein, is placed on a first insulating film 1016a. In certain embodiments, the first insulating film 1016a includes one or more layers formed of polymer-based dielectric materials. For example, the first insulating film 1016a includes one or more layers formed of flowable build-up materials. In the embodiment depicted in FIG. 10A, the first insulating film 1016a includes a flowable layer 1018a. The flowable layer 1018a may be formed of a ceramic-filler-containing epoxy resin, such as an epoxy resin filled with (e.g., containing) silica (SiO₂) particles. Other examples of ceramic fillers or particles that may be utilized to form the flowable layer 1018a and other layers of the insulating film 1016a include aluminum nitride (AlN), aluminum oxide (Al₂O₃), silicon carbide (SiC), silicon nitride (Si₃N₄₎, Sr₂Ce₂Ti₅O₁₆, zirconium silicate (ZrSiO₄), wollastonite (CaSiO₃), beryllium oxide (BeO), cerium dioxide (CeO₂), boron nitride (BN), calcium copper titanium oxide (CaCu₃Ti₄O₁₂), magnesium oxide (MgO), titanium dioxide (TiO₂), zinc oxide (ZnO) and the like. In some examples, the ceramic fillers utilized to form the flowable layer 1018a have particles ranging in size between about 40 nm and about 1.5 μm, such as between about 80 nm and about 1 μm. For example, the ceramic fillers utilized to form the flowable layer 1018a have particles ranging in size between about 200 nm and about 800 nm, such as between about 300 nm and about 600 nm. In some embodiments, the ceramic fillers utilized to form the flowable layer 1018a include particles having a size less than about 25% of the desired feature (e.g., via, cavity, or through-assembly via) width or diameter, such as less than about 15% of the desired feature width or diameter.

The flowable layer 1018a typically has a thickness less than about 60 μm, such as between about 5 μm and about 50 μm. For example, the flowable layer 1018a has a thickness between about 10 μm and about 25 μm. In certain embodiments, the insulating film 1016a further includes one or more support layers. For example, the insulating film 1016a includes a polyethylene terephthalate (PET) or similar lightweight plastic support layer 1022a. However, any suitable combination of layers and insulating materials is contemplated for the insulating film 1016a. In some embodiments, the entire insulating film 1016a has a thickness less than about 120 μm, such as a thickness less than about 90 μm.

The substrate 302, which is coupled to the insulating film 1016a on the first side 1075 thereof, and specifically to the flowable layer 1018a of the insulating film 1016a, may further be optionally placed on a carrier 1024 for mechanical support during later processing operations. The carrier is formed of any suitable mechanically and thermally stable material. For example, the carrier 1024 is formed of polytetrafluoroethylene (PTFE). In another example, the carrier 1024 is formed of PET.

At operation 904 and depicted in FIG. 10B, one or more semiconductor dies 1026 are placed within the cavities 305 formed in the substrate 302, so that the semiconductor dies 1026 are now bound by the insulating film 1016a on one side (a single semiconductor die 1026 is depicted in FIG. 10B). In certain embodiments, the dies 1026 are multipurpose dies having integrated circuits formed on an active surface 1028 thereof. The dies 1026 are placed within the cavities 305 and positioned onto a surface of the insulating film 1016a exposed through the cavities 305. In certain embodiments, the dies 1026 are placed on an adhesive layer (not shown) disposed or formed on the insulating film 1016a.

After placement of the dies 1026 within the cavities 305, a first protective film 1060 is placed over a second side 1077 (e.g., surface 608) of the substrate 302 at operation 906 and FIG. 10C. The protective film 1060 is coupled to the second side 1077 of the substrate 302 and opposite of the first insulating film 1016a such that it contacts and covers the active surfaces 1028 of the dies 1026 disposed within the cavities 305. In certain embodiments, the protective film 1060 is formed of a similar material to that of the support layer 1022a. For example, the protective film 1060 is formed of PET, such as biaxial PET. However, the protective film 1060 may be formed of any suitable protective materials. In some embodiments, the protective film 1060 has a thickness between about 50 μm and about 150 μm.

The substrate 302, now affixed to the insulating film 1016a on the first side 1075 and the protective film 1060 on the second side 1077 and further having dies 1026 disposed therein, is exposed to a lamination process at operation 908. During the lamination process, the substrate 302 is exposed to elevated temperatures, causing the flowable layer 1018a of the insulating film 1016a to soften and flow into the open voids or volumes between the insulating film 1016a and the protective film 1060, such as into the vias 303 and gaps 1051 between the interior walls of the cavities 305 and the dies 1026. Accordingly, the semiconductor dies 1026 become at least partially embedded within the material of the insulating film 1016a and the substrate 302, as depicted in FIG. 10D.

In certain embodiments, the lamination process is a vacuum lamination process that may be performed in an autoclave or other suitable device. In certain embodiments, the lamination process is performed by use of a hot pressing process. In certain embodiments, the lamination process is performed at a temperature of between about 80° C. and about 140° C. and for a period between about 5 seconds and about 1.5 minutes, such as between about 30 seconds and about 1 minute. In some embodiments, the lamination process includes the application of a pressure of between about 1 psig and about 50 psig while a temperature of between about 80° C. and about 140° C. is applied to substrate 302 and insulating film 1016a for a period between about 5 seconds and about 1.5 minutes. For example, the lamination process is performed at a pressure of between about 5 psig and about 40 psig, a temperature of between about 100° C. and about 120° C. for a period between about 10 seconds and about 1 minute. For example, the lamination process is performed at a temperature of about 110° C. for a period of about 20 seconds.

At operation 910, the protective film 1060 is removed and the substrate 302, now having the laminated insulating material of the flowable layer 1018a at least partially surrounding the substrate 302 and the one or more dies 1026, is placed on a second protective film 1062. As depicted in FIG. 10E, the second protective film 1062 is coupled to the first side 1075 of the substrate 302 such that the second protective film 1062 is disposed against (e.g., adjacent) the support layer 1022a of the insulating film 1016a. In some embodiments, the substrate 302, now coupled to the protective film 1062, may be optionally placed on the carrier 1024 for additional mechanical support on the first side 1075. In some embodiments, the protective film 1062 is placed on the carrier 1024 prior to coupling the protective film 1062 with the substrate 302, now laminated with the insulating film 1016a. Generally, the protective film 1062 is substantially similar in composition to the protective film 1060. For example, the protective film 1062 may be formed of PET, such as biaxial PET. However, the protective film 1062 may be formed of any suitable protective materials. In some embodiments, the protective film 1062 has a thickness between about 50 μm and about 150 μm.

Upon coupling the substrate 302 to the second protective film 1062, a second insulating film 1016b substantially similar to the first insulating film 1016a is placed on the second side 1077 of the substrate 302 at operation 912 and FIG. 10F, thus replacing the protective film 1060. In certain embodiments, the second insulating film 1016b is positioned on the second side 1077 of the substrate 302 such that a flowable layer 1018b of the second insulating film 1016b contacts and covers the active surface 1028 of the dies 1026 within the cavities 305. In certain embodiments, the placement of the second insulating film 1016b on the substrate 302 may form one or more voids between the insulating film 1016b and the already-laminated insulating material of the flowable layer 1018a partially surrounding the one or more dies 1026. The second insulating film 1016b may include one or more layers formed of flowable, polymer-based dielectric materials. As depicted in FIG. 10F, the second insulating film 1016b includes a flowable layer 1018b which is similar to the flowable layer 1018a described above. The second insulating film 1016b may further include a support layer 1022b formed of similar materials to the support layer 1022a, such as PET or other lightweight plastic materials.

At operation 914, a third protective film 1064 is placed over the second insulating film 1016b, as depicted in FIG. 10G. Generally, the protective film 1064 is substantially similar in composition to the protective films 1060, 1062. For example, the protective film 1064 is formed of PET, such as biaxial PET. However, the protective film 1064 may be formed of any suitable protective materials. In some embodiments, the protective film 1064 has a thickness between about 50 μm and about 150 μm.

The substrate 302, now affixed to the insulating film 1016b and support layer 1064 on the second side 1077 and the protective film 1062 and optional carrier 1024 on the first side 1075, is exposed to a second lamination process at operation 916 and FIG. 10H. Similar to the lamination process at operation 908, the substrate 302 is exposed to elevated temperatures, causing the flowable layer 1018b of the insulating film 1016b to soften and flow into any open voids or volumes between the insulating film 1016b and the already-laminated insulating material of the flowable layer 1018a, thus integrating itself with the insulating material of the flowable layer 1018a. Accordingly, the cavities 305 and the vias 303 become filled (e.g. packed, sealed) with insulating material, and the semiconductor dies 1026 previously placed within the cavities 305 become entirely embedded within the insulating material of the flowable layers 1018a, 1018b.

In certain embodiments, the lamination process is a vacuum lamination process that may be performed in an autoclave or other suitable device. In certain embodiments, the lamination process is performed by use of a hot pressing process. In certain embodiments, the lamination process is performed at a temperature of between about 80° C. and about 140° C. and for a period between about 1 minute and about 30 minutes. In some embodiments, the lamination process includes the application of a pressure of between about 10 psig and about 150 psig while a temperature of between about 80° C. and about 140° C. is applied to substrate 302 and insulting film 1016b for a period between about 1 minute and about 30 minutes. For example, the lamination process is performed at a pressure of between about 20 psig and about 100 psig, a temperature of between about 100° C. and about 120° C. for a period between about 2 minutes and 10 minutes. For example, the lamination process is performed at a temperature of about 110° C. for a period of about 5 minutes.

After lamination, the substrate 302 is disengaged from the carrier 1024 and the protective films 1062, 1064 are removed at operation 918, resulting in a laminated embedded die assembly 1002. As depicted in FIG. 10I, the embedded die assembly 1002 includes the substrate 302 having one or more cavities 305 and/or vias 303 formed therein and filled with the insulating dielectric material of the flowable layers 1018a, 1018b, as well as the embedded dies 1026 within the cavities 305. The insulating dielectric material of the flowable layers 1018a, 1018b encases the substrate 302 such that the insulating material covers at least two surfaces or sides of the substrate 302, such as the two major surfaces 606, 608, and covers all sides of the embedded semiconductor dies 1026. In some examples, the support layers 1022a, 1022b are also removed from the embedded die assembly 1002 at operation 918. Generally, the support layers 1022a and 1022b, the carrier 1024, and the protective films 1062 and 1064 are removed from the embedded die assembly 1002 by any suitable mechanical processes, such as peeling therefrom.

Upon removal of the support layers 1022a, 1022b and the protective films 1062, 1064, the embedded die assembly 1002 is exposed to a cure process to fully cure (i.e. harden through chemical reactions and cross-linking) the insulating dielectric material of the flowable layers 1018a, 1018b, thus forming a cured insulating layer 1018. The insulating layer 1018 substantially surrounds the substrate 302 and the semiconductor dies 1026 embedded therein. For example, the insulating layer 1018 contacts or encapsulates at least the sides 1075, 1077 of the substrate 302 (including surfaces 606, 608) and at least six sides or surfaces of each semiconductor die 1026, which has a rectangular prism shape as illustrated in FIG. 10I (i.e., only four surfaces 1028 and 1029 shown in 2D view).

In certain embodiments, the cure process is performed at high temperatures to fully cure the embedded die assembly 1002. For example, the cure process is performed at a temperature of between about 140° C. and about 220° C. and for a period between about 15 minutes and about 45 minutes, such as a temperature of between about 160° C. and about 200° C. and for a period between about 25 minutes and about 35 minutes. For example, the cure process is performed at a temperature of about 180° C. for a period of about 30 minutes. In further embodiments, the cure process at operation 918 is performed at or near ambient (e.g. atmospheric) pressure conditions.

After curing, one or more through-assembly vias 1003 are drilled through the embedded die assembly 1002 at operation 920, forming channels through the entire thickness of the embedded die assembly 1002 for subsequent interconnection formation. In some embodiments, the embedded die assembly 1002 may be placed on a carrier, such as the carrier 1024, for mechanical support during the formation of the through-assembly vias 1003 and subsequent contact holes 1032. The through-assembly vias 1003 are drilled through the vias 303 that were formed in the substrate 302 and subsequently filled with the insulating layer 1018. Thus, the through-assembly vias 1003 may be circumferentially surrounded by the insulating layer 1018 filled within the vias 303. By having the ceramic-filler-containing epoxy resin material of the insulating layer 1018 line the walls of the vias 303, capacitive coupling between the conductive silicon-based substrate 302 and interconnections 1444 (described with reference to FIG. 13 and FIGS. 14E-14H), and thus capacitive coupling between adjacently positioned vias 303 and/or redistribution connections 1644 (described with reference to FIG. 15 and FIGS. 16H-16L), in the completed package 1602 (described with reference to FIG. 15 and FIGS. 16K and 16L) is significantly reduced as compared to other conventional interconnecting structures that utilize conventional via insulating liners or films. Furthermore, the flowable nature of the epoxy resin material enables more consistent and reliable encapsulation and insulation, thus enhancing electrical performance by minimizing leakage current of the completed package 1602.

In certain embodiments, the through-assembly vias 1003 have a diameter less than about 100 μm, such as less than about 75 μm. For example, the through-assembly vias 1003 have a diameter less than about 60 μm, such as less than about 50 μm. In certain embodiments, the through-assembly vias 1003 have a diameter of between about 25 μm and about 50 μm, such as a diameter of between about 35 μm and about 40 μm. In certain embodiments, the through assembly vias 1003 are formed using any suitable mechanical process. For example, the through-assembly vias 1003 are formed using a mechanical drilling process. In certain embodiments, through-assembly vias 1003 are formed through the embedded die assembly 1002 by laser ablation. For example, the through-assembly vias 1003 are formed using an ultraviolet laser. In certain embodiments, the laser source utilized for laser ablation has a frequency between about 5 kHz and about 500 kHz. In certain embodiments, the laser source is configured to deliver a pulsed laser beam at a pulse duration between about 10 ns and about 100 ns with a pulse energy of between about 50 microjoules (μJ) and about 500 μJ. Utilizing an epoxy resin material having small ceramic filler particles further promotes more precise and accurate laser patterning of small-diameter vias, such as the vias 1003, as the small ceramic filler particles therein exhibit reduced laser light reflection, scattering, diffraction and transmission of the laser light away from the area in which the via is to be formed during the laser ablation process.

At operation 922 and FIG. 10K, one or more contact holes 1032 are drilled through the insulating layer 1018 to expose one or more contacts 1030 formed on the active surface 1028 of each embedded die 1026. The contact holes 1032 are drilled through the insulating layer 1018 by laser ablation, leaving all external surfaces of the semiconductor dies 1026 covered and surrounded by the insulating layer 1018 and the contacts 1030 exposed. Thus, the contacts 1030 are exposed by the formation of the contact holes 1032. In certain embodiments, the laser source may generate a pulsed laser beam having a frequency between about 100 kHz and about 1000 kHz. In certain embodiments, the laser source is configured to deliver a pulsed laser beam at a wavelength of between about 100 nm and about 2000 nm, at a pulse duration between about 10 E−4 ns and about 10 E−2 ns, and with a pulse energy of between about 10 μJ and about 300 μJ. In certain embodiments, the contact holes 1032 are drilled using a CO₂, green, or UV laser. In certain embodiments, the contact holes 1032 have a diameter of between about 5 μm and about 60 μm, such as a diameter of between about 20 μm and about 50 μm.

After formation of the contact holes 1032, the embedded die assembly 1002 is exposed to a de-smear process at operation 922 to remove any unwanted residues and/or debris caused by laser ablation during the formation of the through-assembly vias 1003 and the contact holes 1032. The de-smear process thus cleans the through-assembly vias 1003 and contact holes 1032 and fully exposes the contacts 1030 on the active surfaces 1028 of the embedded die 1026 for subsequent metallization. In certain embodiments, the de-smear process is a wet de-smear process. Any suitable aqueous etchants, solvents, and/or combinations thereof may be utilized for the wet de-smear process. In one example, potassium permanganate (KMnO₄) solution may be utilized as an etchant. Depending on the residue thickness, exposure of the embedded die assembly 1002 to the wet de-smear process at operation 922 may be varied. In another embodiment, the de-smear process is a dry de-smear process. For example, the de-smear process may be a plasma de-smear process with an O₂:CF₄mixture gas. The plasma de-smear process may include generating a plasma by applying a power of about 700 W and flowing O₂:CF₄at a ratio of about 10:1 (e.g., 100:10 sccm) for a time period between about 60 seconds and about 120 seconds. In further embodiments, the de-smear process is a combination of wet and dry processes.

Following the de-smear process at operation 922, the embedded die assembly 1002 is ready for formation of interconnection paths therein, described below with reference to FIG. 13 and FIGS. 14A-14H.

As discussed above, FIG. 9 and FIGS. 10A-10K illustrate a representative method 900 for forming the intermediary embedded die assembly 1002. FIG. 11 and FIGS. 12A-12G illustrate an alternative method 1100 substantially similar to the method 900 but with fewer operations. The method 1100 generally includes seven operations 1110-1170. However, operations 1110, 1120, 1160, and 1170 of the method 1100 are substantially similar to the operations 902, 904, 920, and 922 of the method 900, respectively. Thus, only operations 1130, 1140, and 1150, depicted in FIGS. 12C, 12D, and 12E, respectively, are herein described for clarity.

After placement of the one or more semiconductor dies 1026 onto a surface of the insulating film 1016a exposed through the cavities 305, the second insulating film 1016b is positioned over the second side 1077 (e.g., surface 608) of the substrate 302 at operation 1130 and FIG. 12C, prior to lamination. In some embodiments, the second insulating film 1016b is positioned on the second side 1077 of the substrate 302 such that the flowable layer 1018b of the second insulating film 1016b contacts and covers the active surface 1028 of the dies 1026 within the cavities 305. In some embodiments, a second carrier 1025 is affixed to the support layer 1022b of the second insulating film 1016b for additional mechanical support during later processing operations. As depicted in FIG. 12C, one or more voids 1050 are formed between the insulating films 1016a and 1016b through the vias 303 and gaps 1051 between the semiconductor dies 1026 and interior walls of the cavities 305.

At operation 1140 and FIG. 12D, the substrate 302, now affixed to the insulating films 1016a and 1016b and having dies 1026 disposed therein, is exposed to a single lamination process. During the single lamination process, the substrate 302 is exposed to elevated temperatures, causing the flowable layers 1018a and 1018b of both insulating films 1016a, 1016b to soften and flow into the open voids or volumes between the insulating films 1016a, 1016b, such as into the vias 303 and gaps 1051 between the interior walls of the cavities 305 and the dies 1026. Accordingly, the semiconductor dies 1026 become embedded within the material of the insulating films 1016a, 1016b and the vias 303 filled therewith.

Similar to the lamination processes described with reference to FIG. 9 and FIGS. 10A-10K, the lamination process at operation 1140 may be a vacuum lamination process that may be performed in an autoclave or other suitable device. In another embodiment, the lamination process is performed by use of a hot pressing process. In certain embodiments, the lamination process is performed at a temperature of between about 80° C. and about 140° C. and for a period between about 1 minute and about 30 minutes. In some embodiments, the lamination process includes the application of a pressure of between about 1 psig and about 150 psig while a temperature of between about 80° C. and about 140° C. is applied to substrate 302 and insulating film 1016a, 1016b layers for a period between about 1 minute and about 30 minutes. For example, the lamination process is performed at a pressure of between about 10 psig and about 100 psig, a temperature of between about 100° C. and about 120° C. for a period between about 2 minutes and 10 minutes. For example, the lamination process is performed at a temperature of about 110° C. for a period of about 5 minutes.

At operation 1150, the one or more support layers of the insulating films 1016a and 1016b are removed from the substrate 302, resulting in the laminated embedded die assembly 1002. As depicted in FIG. 12E, the embedded die assembly 1002 includes the substrate 302 having one or more cavities 305 and/or vias 303 formed therein and filled with the insulating dielectric material of the flowable layers 1018a, 1018b, as well as the embedded dies 1026 within the cavities 305. The insulating material encases the substrate 302 such that the insulating material covers at least two surfaces or sides of the substrate 302, for example surfaces 606, 608. In one example, the support layers 1022a, 1022b are removed from the embedded die assembly 1002, and thus the embedded die assembly 1002 is disengaged from the carriers 1024, 1025. Generally, the support layers 1022a, 1022b and the carriers 1024, 1025 are removed by any suitable mechanical processes, such as peeling therefrom.

Upon removal of the support layers 1022a, 1022b, the embedded die assembly 1002 is exposed to a cure process to fully cure the insulating dielectric material of the flowable layers 1018a, 1018b. Curing of the insulating material results in the formation of the cured insulating layer 1018. As depicted in FIG. 12E and similar to operation 918 corresponding with FIG. 10I, the insulating layer 1018 substantially surrounds the substrate 302 and the semiconductor dies 1026 embedded therein.

In certain embodiments, the cure process is performed at high temperatures to fully cure the embedded die assembly 1002. For example, the cure process is performed at a temperature of between about 140° C. and about 220° C. and for a period between about 15 minutes and about 45 minutes, such as a temperature of between about 160° C. and about 200° C. and for a period between about 25 minutes and about 35 minutes. For example, the cure process is performed at a temperature of about 180° C. for a period of about 30 minutes. In further embodiments, the cure process at operation 1150 is performed at or near ambient (e.g. atmospheric) pressure conditions.

After curing at operation 1150, the method 1100 is substantially similar to operations 920 and 922 of the method 900. For example, the embedded die assembly 1002 has one or more through-assembly vias 1003 and one or more contact holes 1032 drilled through the insulating layer 1018. Subsequently, the embedded die assembly 1002 is exposed to a de-smear process, after which the embedded die assembly 1002 is ready for formation of interconnection paths therein, as described below.

FIG. 13 illustrates a flow diagram of a representative method 1300 of forming electrical interconnections through the embedded die assembly 1002. FIGS. 14A-14H schematically illustrate cross-sectional views of the embedded die assembly 1002 at different stages of the process of the method 1300 depicted in FIG. 13. Thus, FIG. 13 and FIGS. 14A-14H are herein described together for clarity.

In certain embodiments, the electrical interconnections formed through the embedded die assembly 1002 are formed of copper. Thus, the method 1300 may optionally begin at operation 1310 and FIG. 14A wherein the embedded die assembly 1002, having through-assembly vias 1003 and contact holes 1032 formed therein, has an adhesion layer 1440 and/or a seed layer 1442 formed thereon. An enlarged partial view of the adhesion layer 1440 and the seed layer 1442 formed on the embedded die assembly 1002 is depicted in FIG. 14H for reference. The adhesion layer 1440 may be formed on desired surfaces of the insulating layer 1018, such as major surfaces 1005, 1007 of the embedded die assembly 1002, as well as on the active surfaces 1028 of the contact holes 1032 on each die 1026 and interior walls of the through-assembly vias 1003, to assist in promoting adhesion and blocking diffusion of the subsequently formed seed layer 1442 and copper interconnections 1444. Thus, in certain embodiments, the adhesion layer 1440 acts as an adhesion layer; in another embodiment, the adhesion layer 1440 acts as a barrier layer. In both embodiments, however, the adhesion layer 1440 will be hereinafter described as an “adhesion layer.”

In certain embodiments, the optional adhesion layer 1440 is formed of titanium, titanium nitride, tantalum, tantalum nitride, manganese, manganese oxide, molybdenum, cobalt oxide, cobalt nitride, or any other suitable materials or combinations thereof. In certain embodiments, the adhesion layer 1440 has a thickness of between about 10 nm and about 300 nm, such as between about 50 nm and about 150 nm. For example, the adhesion layer 1440 has a thickness between about 75 nm and about 125 nm, such as about 100 nm. The adhesion layer 1440 is formed by any suitable deposition process, including but not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma enhanced CVD (PECVD), atomic layer deposition (ALD), or the like.

The optional seed layer 1442 may be formed on the adhesion layer 1440 or directly on the insulating layer 1018 (e.g., without the formation of the adhesion layer 1440). The seed layer 1442 is formed of a conductive material such as copper, tungsten, aluminum, silver, gold, or any other suitable materials or combinations thereof. In certain embodiments, the seed layer 1442 has a thickness between about 50 nm and about 500 nm, such as between about 100 nm and about 300 nm. For example, the seed layer 1442 has a thickness between about 150 nm and about 250 nm, such as about 200 nm. In certain embodiments, the seed layer 1442 has a thickness of between about 0.1 μm and about 1.5 μm. Similar to the adhesion layer 1440, the seed layer 1442 is formed by any suitable deposition process, such as CVD, PVD, PECVD, ALD dry processes, wet electroless plating processes, or the like. In certain embodiments, a molybdenum adhesion layer 1440 is formed on the embedded die assembly in combination with a copper seed layer 1442. The Mo—Cu adhesion and seed layer combination enables improved adhesion with the surfaces of the insulating layer 1018 and reduces undercut of conductive interconnect lines during a subsequent seed layer etch process at operation 1370.

At operations 1320 and 1330, corresponding to FIGS. 14B and 14C, respectively, a spin-on/spray-on or dry resist film 1450, such as a photoresist, is applied on both major surfaces 1005, 1007 of the embedded die assembly 1002 and is subsequently patterned. In certain embodiments, the resist film 1450 is patterned via selective exposure to UV radiation. In certain embodiments, an adhesion promoter (not shown) is applied to the embedded die assembly 1002 prior to formation of the resist film 1450. The adhesion promoter improves adhesion of the resist film 1450 to the embedded die assembly 1002 by producing an interfacial bonding layer for the resist film 1450 and by removing any moisture from the surface of the embedded die assembly 1002. In some embodiments, the adhesion promoter is formed of bis(trimethylsilyl)amine or hexamethyldisilazane (HMDS) and propylene glycol monomethyl ether acetate (PGMEA).

At operation 1340 and FIG. 14D, the embedded die assembly 1002 is exposed to a resist film development process. As depicted in FIG. 14D, development of the resist film 1450 results in exposure of the through-assembly vias 1003 and contact holes 1032, now having an adhesion layer 1440 and a seed layer 1442 formed thereon. In certain embodiments, the film development process is a wet process, such as a wet process that includes exposing the resist to a solvent. In certain embodiments, the film development process is a wet etch process utilizing an aqueous etch process. In other embodiments, the film development process is a wet etch process utilizing a buffered etch process selective for a desired material. Any suitable wet solvents or combination of wet etchants may be used for the resist film development process.

At operations 1350 and 1360, corresponding to FIGS. 14E and 14F respectively, interconnections 1444 are formed through the exposed through-assembly vias 1003 and contact holes 1032 and the resist film 1450 is thereafter removed. The interconnections 1444 are formed by any suitable methods including electroplating and electroless deposition. In certain embodiments, the resist film 1450 is removed via a wet process. As depicted in FIGS. 14E and 14F, the formed interconnections 1444 fill the through-assembly vias 1003 and contact holes 1032 and/or cover inner circumferential walls thereof and protrude from the surfaces 1005, 1007, and 1028 of the embedded die assembly 1002 upon removal of the resist film 1450. In certain embodiments, the interconnections 1444 are formed of copper. In other embodiments, the interconnections 1444 may be formed of any suitable conductive material including but not limited to aluminum, gold, nickel, silver, palladium, tin, or the like.

At operation 1370 and FIG. 14G, the embedded die assembly 1002 having interconnections 1444 formed therein is exposed to an adhesion and/or seed layer etch process to remove the adhesion layer 1440 and the seed layer 1442. In certain embodiments, the seed layer etch is a wet etch process including a rinse and drying of the embedded die assembly 1002. In certain embodiments, the seed layer etch process is a buffered etch process selective for a desired material such as copper, tungsten, aluminum, silver, or gold. In other embodiments, the etch process is an aqueous etch process. Any suitable wet etchant or combination of wet etchants may be used for the seed layer etch process.

Following the seed layer etch process at operation 1370, one or more electrically functioning packages may be singulated from the embedded die assembly 1002. Alternatively, the embedded die assembly 1002 may have one or more redistribution layers 1658 and/or 1660 (shown in FIGS. 16K-16L) formed thereon as needed to enable rerouting of contact points of the interconnections 1444 to desired locations on the surfaces of the embedded die assembly 1002. FIG. 15 illustrates a flow diagram of a representative method 1500 of forming a redistribution layer 1658 on the embedded die assembly 1002. FIGS. 16A-16L schematically illustrate cross-sectional views of the embedded die assembly 1002 at different stages of the method 1500 depicted in FIG. 15. Thus, FIG. 15 and FIGS. 16A-16L are herein described together for clarity.

The method 1500 is substantially similar to the methods 900, 1100, and 1300 described above. Generally, the method 1500 begins at operation 1502 and FIG. 16A, wherein an insulating film 1616 is placed on the embedded die assembly 1002 and thereafter laminated. The insulating film 1616 may be substantially similar to the insulating film 1016 and includes one or more layers formed of polymer-based flowable dielectric materials. In certain embodiments, as depicted in FIG. 16A, the insulating film 1616 includes a flowable layer 1618 and one or more support layers 1622. In certain embodiments, the insulating film 1616 may include a ceramic-filler-containing epoxy resin flowable layer 1618 and one or more support layers 1622. In another example, the insulating film 1616 may include a photodefinable polyimide flowable layer 1618 and one or more support layers 1622. The material properties of photodefinable polyimide enable the formation of smaller (e.g., narrower) vias through the resulting interconnect layer formed therefrom. However, any suitable combination of layers and insulating materials is contemplated for the insulating film 1616. For example, the insulating film 1616 may include a non-photosensitive polyimide, polybenzoxazole (PBO), silicon dioxide, and/or silicon nitride flowable layer 1618. Examples of suitable materials for the one or more support layers 1622 include PET and polypropylene (PP).

In some examples, the flowable layer 1618 includes a different polymer-based flowable dielectric material than the flowable layers 1018a, 1018b described above. For example, the flowable layer 1018 may include a ceramic-filler-containing epoxy resin and the flowable layer 1618 may include a photodefinable polyimide. In another example, the flowable layer 1618 is formed from a different inorganic dielectric material from the flowable layers 1018a, 1018b. For example, the flowable layers 1018a, 1018b may include a ceramic-filler-containing epoxy resin and the flowable layer 1618 may include a silicon dioxide layer.

The insulating film 1616 has a thickness of less than about 200 μm, such as a thickness between about 10 μm and about 180 μm. For example, the insulating film 1616 including the flowable layer 1618 and the PET support layer 1622 has a total thickness of between about 50 μm and about 100 μm. In certain embodiments, the flowable layer 1618 has a thickness of less than about 60 μm, such as a thickness between about 5 μm and about 50 μm, such as a thickness of about 20 μm. The insulating film 1616 is placed on a surface of the embedded die assembly 1002 having exposed interconnections 1444 that are coupled to the contacts 1030 on the active surface 1028 of dies 1026 and/or coupled to the metallized through-assembly vias 1003, such as the major surface 1005.

After placement of the insulating film 1616, the embedded die assembly 1002 is exposed to a lamination process substantially similar to the lamination process described with reference to operations 908, 916, and 1140. The embedded die assembly 1002 is exposed to elevated temperatures to soften the flowable layer 1618, which subsequently bonds to the insulating layer 1018 already formed on the embedded die assembly 1002. Thus, in certain embodiments, the flowable layer 1618 becomes integrated with the insulating layer 1018 and forms an extension thereof. The integration of the flowable layer 1618 and the insulating layer 1018 results in an expanded and integrated insulating layer 1018 covering the previously exposed interconnections 1444. Accordingly, the bonded flowable layer 1618 and the insulating layer 1018 will herein be jointly described as the insulating layer 1018. In other embodiments, however, the lamination and subsequent curing of the flowable 1618 forms a second insulating layer (not shown) on the insulating layer 1018. In some examples, the second insulating layer is formed of a different material layer than the insulating layer 1018.

In certain embodiments, the lamination process is a vacuum lamination process that may be performed in an autoclave or other suitable device. In certain embodiments, the lamination process is performed by use of a hot pressing process. In certain embodiments, the lamination process is performed at a temperature of between about 80° C. and about 140° C. and for a period between about 1 minute and about 30 minutes. In some embodiments, the lamination process includes the application of a pressure of between 10 psig and about 100 psig while a temperature of between about 80° C. and about 140° C. is applied to the substrate 302 and insulating film 1616 for a period between about 1 minute and about 30 minutes. For example, the lamination process is performed at a pressure of between about 30 psig and about 80 psig and a temperature of between about 100° C. and about 120° C. for a period between about 2 minutes and about 10 minutes. For example, the lamination process is performed at a temperature of about 110° C. for a period of about 5 minutes. In further examples, the lamination process is performed at a pressure between about 30 psig and about 70 psig, such as about 50 psig.

At operation 1504 and FIG. 16B, the support layer 1622 and the carrier 1624 are removed from the embedded die assembly 1002 by mechanical processes. After removal of the support layer 1622 and carrier 1624, the embedded die assembly 1002 is exposed to a cure process to fully cure the newly expanded insulating layer 1018. In certain embodiments, the cure process is substantially similar to the cure process described with reference to operations 918 and 1150. For example, the cure process is performed at a temperature of between about 140° C. and about 220° C. and for a period between about 15 minutes and about 45 minutes, such as a temperature of between about 160° C. and about 200° C. and for a period between about 25 minutes and about 35 minutes. For example, the cure process is performed at a temperature of about 180° C. for a period of about 30 minutes. In further embodiments, the cure process at operation 1504 is performed at or near ambient pressure conditions.

The embedded die assembly 1002 is then selectively patterned by laser ablation at operation 1506 and FIG. 16C. The laser ablation at operation 1506 forms redistribution vias 1603 through the newly expanded insulating layer 1018 and exposes desired interconnections 1444 for redistribution of contact points thereof. In certain embodiments, the redistribution vias 1603 have a diameter of between about 5 μm and about 60 μm, such as a diameter of between about 10 μm and about 50 μm, such as between about 20 μm and about 45 μm. In certain embodiments, the laser ablation process at operation 1506 is performed utilizing a CO₂laser. In certain embodiments, the laser ablation process at operation 1506 is performed utilizing a UV laser. In certain embodiments, the laser ablation process at operation 1506 is performed utilizing a green laser. For example, the laser source may generate a pulsed laser beam having a frequency between about 100 kHz and about 1000 kHz. In one example, the laser source is configured to deliver a pulsed laser beam at a wavelength of between about 100 nm and about 2000 nm, at a pulse duration between about 10 E−4 ns and about 10 E−2 ns, and with a pulse energy of between about 10 μJ and about 300 μJ.

Upon patterning of the embedded die assembly 1002, the embedded die assembly 1002 is exposed to a de-smear process substantially similar to the de-smear process at operation 922 and 1170. During the de-smear process at operation 1506, any unwanted residues and debris formed by laser ablation during the formation of the redistribution vias 1603 are removed from the redistribution vias 1603 to clear (e.g., clean) the surfaces thereof for subsequent metallization. In certain embodiments, the de-smear process is a wet process. Any suitable aqueous etchants, solvents, and/or combinations thereof may be utilized for the wet de-smear process. In one example, KMnO₄solution may be utilized as an etchant. In another embodiment, the de-smear process is a dry de-smear process. For example, the de-smear process may be a plasma de-smear process with an O₂/CF₄mixture gas. In further embodiments, the de-smear process is a combination of wet and dry processes.

At operation 1508 and FIG. 16D, an optional adhesion layer 1640 and/or seed layer 1642 are formed on the insulating layer 1018. In certain embodiments, the adhesion layer 1640 is formed from titanium, titanium nitride, tantalum, tantalum nitride, manganese, manganese oxide, molybdenum, cobalt oxide, cobalt nitride, or any other suitable materials or combinations thereof. In certain embodiments, the adhesion layer 1640 has a thickness of between about 10 nm and about 300 nm, such as between about 50 nm and about 150 nm. For example, the adhesion layer 1640 has a thickness between about 75 nm and about 125 nm, such as about 100 nm. The adhesion layer 1640 may be formed by any suitable deposition process, including but not limited to CVD, PVD, PECVD, ALD, or the like.

The optional seed layer 1642 is formed from a conductive material such as copper, tungsten, aluminum, silver, gold, or any other suitable materials or combinations thereof. In certain embodiments, the seed layer 1642 has a thickness between about 50 nm and about 500 nm, such as between about 100 nm and about 300 nm. For example, the seed layer 1642 has a thickness between about 150 nm and about 250 nm, such as about 200 nm. In certain embodiments, the seed layer 1642 has a thickness of between about 0.1 μm and about 1.5 μm. Similar to the adhesion layer 1640, the seed layer 1642 may be formed by any suitable deposition process, such as CVD, PVD, PECVD, ALD dry processes, wet electroless plating processes, or the like. In certain embodiments, a molybdenum adhesion layer 1640 and a copper seed layer 1642 are formed on the embedded die assembly 1002 to reduce undercut of conductive interconnect lines during a subsequent seed layer etch process at operation 1520.

At operations 1510, 1512, and 1514, corresponding to FIGS. 16E, 16F, and 16G respectively, a spin-on/spray-on or dry resist film 1650, such as a photoresist, is applied over the adhesion and/or seed surfaces of the embedded die assembly 1002 and subsequently patterned and developed. In certain embodiments, an adhesion promoter (not shown) is applied to the embedded die assembly 1002 prior to placement of the resist film 1650. The exposure and development of the resist film 1650 results in opening of the redistribution vias 1603. Thus, patterning of the resist film 1650 may be performed by selectively exposing portions of the resist film 1650 to UV radiation, and subsequent development of the resist film 1650 by a wet process, such as a wet etch process. In certain embodiments, the resist film development process is a wet etch process utilizing a buffered etch process selective for a desired material. In other embodiments, the resist film development process is a wet etch process utilizing an aqueous etch process. Any suitable wet etchant or combination of wet etchants may be used for the resist film development process.

At operations 1516 and 1518, corresponding to FIGS. 16H and 16I respectively, redistribution connections 1644 are formed through the exposed redistribution vias 1603 and the resist film 1650 is thereafter removed. The redistribution connections 1644 are formed by any suitable methods including electroplating and electroless deposition. In certain embodiments, the resist film 1650 is removed via a wet process. As depicted in FIGS. 16H and 16I, the redistribution connections 1644 fill the redistribution vias 1603 and protrude from the surfaces of the embedded die assembly 1002 upon removal of the resist film 1650. In certain embodiments, the redistribution connections 1644 are formed of copper. In other embodiments, the redistribution connections 1644 may be formed of any suitable conductive material including but not limited to aluminum, gold, nickel, silver, palladium, tin, or the like.

At operation 1520 and FIG. 16J, the embedded die assembly 1002 having the redistribution connections 1644 formed thereon is exposed to a seed layer etch process substantially similar to that of operation 1370. In certain embodiments, the seed layer etch is a wet etch process including a rinse and drying of the embedded die assembly 1002. In certain embodiments, the seed layer etch process is a wet etch process utilizing a buffered etch process selective for a desired material of the seed layer 1642. In other embodiments, the etch process is a wet etch process utilizing an aqueous etch process. Any suitable wet etchant or combination of wet etchants may be used for the seed layer etch process.

At operation 1522 and depicted in FIGS. 16K and 16L, one or more completed packages 1602 are singulated from the embedded die assembly 1002. Prior to operation 1522, however, additional redistribution layers may be formed on the embedded die assembly 1002 utilizing the sequences and processes described above, as depicted in FIG. 16L (FIG. 16K depicts the completed package 1602 having one additional redistribution layer 1658). For example, one or more additional redistribution layers 1660 may be formed on a side or surface of the embedded die assembly 1002 opposite of the first additional redistribution layer 1658, such as the major surface 1007. Alternatively, one or more additional redistribution layers 1660 may be formed on the same side or surface of the first additional redistribution layer 1658 (not shown), such as major surface 1005. The completed package 1602 may then be singulated from the embedded die assembly 1002 after all desired redistribution layers are formed.

FIG. 17 illustrates a flow diagram of an alternative method 1700 for placing and laminating an insulating layer on the embedded die assembly 1002 when forming a redistribution layer. FIGS. 18A-18C schematically illustrate cross-sectional views of the embedded die assembly 1002 at different stages of the method 1700. Thus, FIG. 17 and FIGS. 18A-18C are herein described together for clarity. Note that upon performing operations 1702-1706 of the method 1700, operations 1508-1522 of the method 1500 may be carried out to complete formation of the redistribution layer, e.g., depositing of an adhesion and/or seed layer, plating of redistribution connections, etc.

The method 1700 is substantially similar to one or more of the methods described above. Generally, the method 1700 begins at operation 1702 and FIG. 18A, wherein a pre-structured insulating film 1816 is aligned and placed on the embedded die assembly 1002. Similar to the insulating films 1616, 1016 described above, the insulating film 1816 may include one or more layers formed of polymer-based flowable dielectric materials. For example, in certain embodiments, the insulating film 1816 includes a flowable layer 1818 and one or more support layers 1822. In certain embodiments, the insulating film 1816 includes a ceramic-filler-containing epoxy resin flowable layer 1818 and one or more support layers 1822. In another example, the insulating film 1816 includes a photodefinable polyimide flowable layer 1818 and one or more support layers 1822. However, any suitable combination of layers and insulating materials is contemplated for the insulating film 1816, such as those described above with reference to insulating films 1616 and 1016. For example, in certain embodiments, the flowable layer 1818 may be formed of a non-photosensitive polyimide, polybenzoxazole (PBO), silicon dioxide, and/or silicon nitride. Examples of suitable materials for the one or more support layers 1822 include PET, PP, polyethylene (PE) polycarbonates, polystyrene, and the like.

In some examples, the flowable layer 1818 is formed from a different polymer-based flowable dielectric material than the flowable layers 1018a, 1018b. For example, the flowable layers 1018a, 1018b may include a ceramic-filler-containing epoxy resin layer, while the flowable layer 1818 may include a photodefinable polyimide layer, or vice versa. In another example, the flowable layer 1818 is formed from a different inorganic dielectric material from the flowable layers 1018a, 1018b. For example, the flowable layers 1018a, 1018b may include a ceramic-filler-containing epoxy resin layer and the flowable layer 1818 may include a silicon dioxide layer, or vice versa.

The flowable layer 1818 typically has a thickness less than about 120 μm, such as between about 10 μm and about 100 μm. For example, the flowable layer 1818 has a thickness between about 20 μm and about 80 μm. In certain embodiments, the entire insulating film 1816 has a thickness less than about 200 μm, such as a thickness less than about 160 μm.

Unlike previous examples of insulating films, however, the insulating film 1816 is pre-structured, i.e., structured prior to placement and lamination on the embedded die assembly 1002. For example, the insulating film 1816 has one or more vias 1803 formed therein for subsequent plating of redistribution connections, with sidewalls of the vias 1803 selectively cured. Pre-structuring of the insulating film 1816 is described in further detail with reference to FIG. 19, FIGS. 20A-20C, and FIGS. 21A-21B. Accordingly, during placement of the insulating film 1816 on the embedded die assembly 1002, the insulating film 1816 is aligned with the embedded die assembly 1002 such that the pre-structured vias 1803 are aligned with respect to contact points or pads of interconnections 1444, thus enabling connection of the interconnections 1444 with subsequently formed redistribution connections. In certain embodiments, the insulating film 1816 has one or more fiducial marks formed thereon to facilitate alignment with the embedded die assembly 1002, which may have one or more corresponding fiducial marks (e.g., etched regions or deposited material regions) formed on a mating surface thereof. However, any suitable alignment methods are contemplated.

At operation 1704 and FIG. 18B, after placement of the pre-structured insulating film 1816, the embedded die assembly 1002 is exposed to a lamination process substantially similar to the lamination process described above. The embedded die assembly 1002 is thus exposed to elevated temperatures to soften the flowable layer 1818, which subsequently bonds to the insulating layer 1018 already formed on the embedded die assembly 1002. Thus, in certain embodiments, the flowable layer 1818 becomes integrated with the insulating layer 1018 and forms an extension thereof. The integration of the flowable layer 1818 and the insulating layer 1018 results in an expanded and integrated insulating layer 1018 covering the previously exposed interconnections 1444. Accordingly, the bonded flowable layer 1818 and the insulating layer 1018 will herein be jointly described as the insulating layer 1018. In other embodiments, however, the lamination of the flowable layer 1818 forms a second insulating layer (not shown) on the insulating layer 1018. In some examples, the second insulating layer is formed of a different material than the insulating layer 1018. In some embodiments, the second insulating layer may have different structural-, electrical-, or compositional-related material properties from the insulating layer 1018. In other embodiments, the second insulating layer comprises the same material as the insulating layer 1018, but has different structural properties (e.g., thickness).

In certain embodiments, the lamination process is a vacuum lamination process that may be performed in an autoclave or other suitable device. In certain embodiments, the lamination process is performed by use of a hot pressing process. In certain embodiments, the lamination process is performed at a temperature of between about 80° C. and about 140° C. and for a period between about 1 minute and about 30 minutes. In some embodiments, the lamination process includes the application of a pressure of between 10 psig and about 100 psig while a temperature of between about 80° C. and about 140° C. is applied to the substrate 302 and insulating film 1616 for a period between about 1 minute and about 30 minutes. For example, the lamination process is performed at a pressure of between about 30 psig and about 80 psig and a temperature of between about 100° C. and about 120° C. for a period between about 2 minutes and about 10 minutes. For example, the lamination process is performed at a temperature of about 110° C. for a period of about 5 minutes. In further examples, the lamination process is performed at a pressure between about 30 psig and about 70 psig, such as about 50 psig.

At operation 1706 and FIG. 18C, the support layer 1822 is removed from the flowable layer 1818 laminated onto the embedded die assembly 1002 by mechanical processes. After removal of the support layer 1822, in certain embodiments, the embedded die assembly 1002 is exposed to a cure process to fully cure the newly expanded insulating layer 1018. In certain embodiments, the cure process is substantially similar to the cure processes described above with reference to operations 918 and 1150. For example, the cure process is performed at a temperature of between about 140° C. and about 220° C. and for a period between about 15 minutes and about 45 minutes, such as a temperature of between about 160° C. and about 200° C. and for a period between about 25 minutes and about 35 minutes. For example, the cure process is performed at a temperature of about 180° C. for a period of about 30 minutes. In further embodiments, the cure process at operation 1504 is performed at or near ambient pressure conditions.

Thereafter, operations 1508-1522 of the method 1500 may be carried out to complete formation of the redistribution layer, e.g., depositing of an adhesion and/or seed layer, plating of redistribution connections, etc., as described above.

FIG. 19 illustrates a flow diagram of a method 1900 for pre-structuring an insulating film prior to placement on, e.g., an embedded die assembly or other semiconductor device package structure, according to embodiments described herein. FIGS. 20A-20C schematically illustrate cross-sectional views of an insulating film at different stages of the pre-structuring method 1900 depicted in FIG. 19. Thus, FIG. 19 and FIGS. 20A-20C are herein described together for clarity.

The method 1900 beings at operation 1902 and corresponding FIG. 20A, wherein an insulating film, e.g., insulating film 1816, is patterned via laser ablation to form one or more features in the flowable layer thereof, such as vias 1803. However, in some embodiments, an insulating film is patterned by a lithographic and development process, or a mechanical stamping process, to form the one or more features therein. Unless otherwise noted, embodiments and examples described herein may be conducted on any insulating sheets or films comprising a 10-100 μm thick flowable layer sandwiched between two or more support or cover/protective layers. In the example shown in FIGS. 20A-20C, the insulating film 1816 includes the flowable layer 1818 attached to support layer 1822 as described above, in addition to a cover layer 1824 adhered to flowable layer 1818 on a side thereof opposite the support layer 1822. In certain embodiments, the cover layer 1824 is made of a similar material to that of support layer 1822. For example, the cover layer 1824 may be formed of a lightweight plastic material, such as PET, PP, PE, etc. The cover layer 1824 may be removed upon pre-structuring of the insulating film 1816 and prior to placement of the insulating film 1816 on, e.g., an embedded die assembly or other semiconductor device package structure.

Furthermore, embodiments and examples described herein may be conducted on bulk or previously-singulated insulating films. For example, pre-structuring may be conducted on a roll of insulating film, after which the insulating film may be optionally singulated (e.g., at operation 1906) for batch or single device placement and lamination.

As discussed above, patterning of the insulating film 1816 may be achieved using a laser ablation system having any suitable type of laser source 2007. In certain embodiments, the laser source 2007 is an infrared (IR) laser. In certain embodiments, the laser source 2007 is a UV laser, such as a 355 nm UV laser or 248 nm excimer UV laser. For example, the laser source 2007 may be a picosecond or femtosecond UV laser. In certain embodiments, the laser source 2007 is a femtosecond green laser. In still other embodiments, the laser source 2007 is a CO₂laser. The laser source 2007 may generate a continuous or pulsed laser beam 2010 for patterning of the insulating film 1816. For example, in certain embodiments, the laser source 2007 may generate a pulsed laser beam having a frequency between about 100 kHz and about 1000 kHz. In one example, the laser source is configured to deliver a pulsed laser beam at a wavelength of between about 100 nm and about 2000 nm, at a pulse duration between about 10 E−4 ns and about 10 E−2 ns, and with a pulse energy of between about 10 μJ and about 300 μJ.

The laser source 2007 is configured to form any desired pattern and/or features in the insulating film 1816, including the vias 1803, which may be utilized for plating of electrical connections through the flowable layer 1818. For example, the laser source 2007 may be utilized to form vias 1803 having a diameter of between about 5 μm and about 60 μm, such as a diameter of between about 10 μm and about 50 μm, such as between about 20 μm and about 45 μm. The vias 1803 may be disposed in any desired arrangement/location through the insulating film 1816 so as to enable contact/coupling between subsequently plated electrical connections in the vias 1803 and, e.g., interconnections and/or redistribution connections in the embedded die assembly, or other semiconductor device package structure, upon which the insulating film 1816 is laminated.

After patterning, the insulating film 1816 is exposed to a selective cure process at operation 1904 and FIG. 20B to selectively cure the sidewalls of any patterned features, thus enabling the patterned features to maintain their morphology during subsequent operations. For example, the cure process at operation 1904 may be utilized to harden sidewalls of the vias 1803 (hardened sidewalls shown as 2020 in FIG. 20B) such that the vias 1803 maintain their morphology and structural integrity during placement and lamination of the insulating film 1816 onto, e.g., the embedded die assembly 1002, as described with reference to method 1700. Accordingly, the selective cure process prevents any features patterned in the insulating film 1816 from collapsing during, e.g., placement and lamination.

Generally, the cure process may be performed at elevated temperatures, such as temperatures between about 140° C. and about 220° C., such as temperatures between about 160° C. and about 200° C., such as a temperature of about 180° C. In certain embodiments, the cure process is a plasma cure process, in which the patterned insulating film 1816 is exposed to a plasma comprising N₂, CH₄, H₂, CF₄, and/or O₂species. In certain other embodiments, the cure process is a UV cure process. The insulating film 1816 may be exposed to the cure process for a period of about 1 to about 60 seconds, such as a period of about 2 to about 30 seconds, such as a period of about 5 to about 20 seconds, such as a period of about 10 seconds.

At operation 1906 and FIG. 20C, the patterned and cured insulating film 1816 is optionally singulated for placement and lamination on a semiconductor device package. In certain embodiments, however, the insulating film 1816 is placed and laminated on a batch or bulk semiconductor device package structure, and the insulating film 1816 may be singulated along with the semiconductor device package structure into individual packages (after further processing), as described above. In still other embodiments, the insulating film 1816 is singulated prior to pre-structuring.

In certain embodiments wherein pre-structuring is carried out on a bulk insulating film, the method 1900 is performed using a roll-to-roll pre-structuring apparatus. FIGS. 21A and 21B schematically illustrate an exemplary roll-to-roll pre-structuring apparatus 2100 for use during the method 1900. The apparatus 2100 may include an unwinding module 2104, a winding module 2106, and one or more processing stations disposed therebetween. In the example of FIG. 21A, the apparatus 2100 is shown with three processing stations 2110, 2120, and 2130, which may each be utilized for performing a separate operation of method 1900. For example, processing station 2110 may be a laser ablation system for performing operation 1902, as shown in FIG. 21B; processing station 2120 may be a curing system, such as a processing chamber or oven, for performing operation 1904; and optional processing station 2130 may be a singulation station for performing operation 1906.

According to certain embodiments, unwinding module 2104 and winding module 2106, which may each include one or more rollers, operate in tandem to facilitate feeding (e.g., rolling) of insulating film 1816 through each of the processing stations 2110, 2120, and 2130. The insulating film 1816 be may passed through each processing station sequentially, such that a desired region of insulating film 1816 is patterned, cured, and singulated in sequence during pre-structuring.

In addition to being utilized to form redistribution layers, pre-structured insulating films 1816 may also be utilized to form the insulation layer(s) encapsulating a substrate/frame, and any semiconductor dies, of an embedded die assembly or other semiconductor device package structure. For example, by utilizing two pre-structured insulating films 1816, an insulating layer 2318 substantially similar to insulating layer 1018 may be formed on a substrate/frame, e.g., substrate 302 described above. FIG. 22 illustrates a flow diagram of a method 2200 for forming such an insulating layer, according to embodiments described herein. FIGS. 23A-23G schematically illustrate cross-sectional views of the substrate 302 at different stages of the method 2200 depicted in FIG. 22. Thus, FIG. 22 and FIGS. 23A-23G are herein described together for clarity.

Generally, the method 2200 begins at operation 2202 and FIG. 23A, wherein the substrate 302, already patterned and having desired features formed therein, is aligned (e.g., via fiducials) and placed on a first pre-structured insulating film 1816. In certain embodiments, the insulating film 1816 is pre-structured, i.e., structured before placement on the substrate 302, to include one or more vias 1803 laterally aligned with vias 303 formed in the substrate 302, such that when the flowable layer 1818 of the insulating film 1816 is laminated to substrate 302, interconnections, e.g., interconnections 1444, may be subsequently plated through both vias 303 and 1803.

In certain embodiments, after placement of the substrate 302 onto the insulating film 1816, and specifically onto the flowable layer 1818 thereof, the substrate 302 and insulating film 1816 may be optionally placed on the carrier 1024 for mechanical support during later processing operations, as described above with reference to similar methods.

At operation 2204 and depicted in FIG. 23B, one or more semiconductor dies 1026 are placed within the cavities 305 formed in the substrate 302, so that the semiconductor dies 1026 are now bordered by the insulating film 1816 on one side, and the substrate 302 on, e.g., four sides thereof (a single semiconductor die 1026 is depicted in FIG. 23B). In certain embodiments, the dies 1026 are multipurpose dies having integrated circuits formed on an active surface 1028 thereof. The dies 1026 are placed within the cavities 305 and positioned onto a surface of the insulating film 1816 exposed through the cavities 305. In certain embodiments, the dies 1026 are placed on an adhesive layer (not shown) disposed or formed on the insulating film 1816.

At operation 2206 and FIG. 23C, the substrate 302, now placed on the insulating film 1816 and further having dies 1026 disposed therein, is exposed to a lamination process. During the lamination process, the substrate 302 is exposed to elevated temperatures, causing the flowable layer 1818 of the insulating film 1816 to soften and flow into gaps 1051 between the interior walls of the cavities 305 and the dies 1026, while the vias 303 of substrate 302 remain unfilled due to prior curing of the sidewalls 2020 of vias 1803. As described above, selectively curing sidewalls 2020 of the vias 1803 maintains the structural integrity thereof and thus prevents the dielectric material of the flowable layer 1818 from flowing into the vias 303 upon lamination (e.g., prevents the flowable layer 1818 from plugging vias 3030). Accordingly, the semiconductor dies 1026 become at least partially embedded within the material of the insulating film 1816 and the substrate 302, as depicted in FIG. 23C. Additionally, the substrate 302 becomes affixed to the flowable layer 1818.

In certain embodiments, prior to lamination, a protective film, e.g., protective film 1060, is placed over the exposed side, e.g., side 1077, of the substrate 302, as shown in FIG. 23C. In certain embodiments, the protective film 1060 is formed of a similar material to that of the support layer 1022a. For example, the protective film 1060 is formed of PET, such as biaxial PET. However, the protective film 1060 may be formed of any suitable protective materials. The protective film 1060 is removed after lamination and prior to operation 2208 discussed below.

At operation 2208 and FIG. 23D, a second pre-structured insulating film 1816 is aligned (e.g., via fiducials) and placed on the opposing side of the substrate 302, e.g., side 1077. In certain embodiments, the second insulating film 1816 is positioned such that the flowable layer 1818 thereof contacts and covers the active surface 1028 of the dies 1026 within the cavities 305. The second insulation film 1816 may be pre-structured to include one or more vias 1803 laterally aligned with vias 303 formed in the substrate 302, as well as one or more vias 1803 laterally aligned with contacts 1030 formed on the active surface 1028 of each embedded die 1026. Accordingly, interconnections, e.g., interconnections 1444, may be subsequently plated through both vias 303 and 1803, and may further be routed to contacts 1030 for connecting embedded dies 1026 to other devices.

The substrate 302, now affixed to the first insulating film 1816 on the first side 1075 and having the second insulating film 1816 placed on the second side 1077, is exposed to a second lamination process at operation 2210 and FIG. 23E. Similar to the lamination process at operation 2206, the substrate 302 is exposed to elevated temperatures, causing the flowable layer 1818 of the second insulating film 1816 to soften and flow into open remaining gaps 1051 between the interior walls of the cavities 305 and the dies 1026, thus integrating itself with the insulating material of the flowable layer 1818 of the first insulating film 1816. Accordingly, the cavities 305 become filled (e.g. packed, sealed) and the semiconductor dies 1026 become entirely embedded within the insulating material of the flowable layers 1818, while vias 303 and 1803 remain open.

In certain embodiments, the second lamination process is a vacuum lamination process that may be performed in an autoclave or other suitable device. In certain embodiments, the lamination process is performed by use of a hot pressing process. In certain embodiments, the lamination process is performed at a temperature of between about 80° C. and about 140° C. and for a period between about 1 minute and about 30 minutes. In some embodiments, the lamination process includes the application of a pressure of between about 10 psig and about 150 psig while a temperature of between about 80° C. and about 140° C. is applied to substrate 302 and insulting film 1016b for a period between about 1 minute and about 30 minutes. For example, the lamination process is performed at a pressure of between about 20 psig and about 100 psig, a temperature of between about 100° C. and about 120° C. for a period between about 2 minutes and 10 minutes. For example, the lamination process is performed at a temperature of about 110° C. for a period of about 5 minutes.

At operation 2212 and FIG. 23F, the laminated embedded die assembly 1002 is disengaged from any carriers and/or protective films, the support layers 1822 are removed, and the embedded die assembly 1002 is exposed to a cure process. Generally, the support layers 1822 and any carriers and/or protective films are removed from the embedded die assembly 1002 by any suitable mechanical processes, such as peeling therefrom. Thereafter, the embedded die assembly 1002 is exposed to a cure process to fully cure (i.e. harden through chemical reactions and cross-linking) the insulating dielectric material of the flowable layers 1818, thus forming the cured insulating layer 2318. The insulating layer 2318 substantially surrounds the substrate 302 and the semiconductor dies 1026 embedded therein, but for the sidewalls of vias 303. For example, the insulating layer 2318 contacts or encapsulates at least the sides 1075, 1077 of the substrate 302 (including surfaces 606, 608) and at least six sides or surfaces of each semiconductor die 1026, while leaving the sidewalls of vias 303 exposed.

In certain embodiments, the cure process is performed at high temperatures to fully cure the embedded die assembly 1002. For example, the cure process is performed at a temperature of between about 140° C. and about 220° C. and for a period between about 15 minutes and about 45 minutes, such as a temperature of between about 160° C. and about 200° C. and for a period between about 25 minutes and about 35 minutes. For example, the cure process is performed at a temperature of about 180° C. for a period of about 30 minutes. In further embodiments, the cure process at operation 2212 is performed at or near ambient (e.g. atmospheric) pressure conditions.

After curing, the embedded die assembly 1002 is ready for formation of interconnection paths therein, as described above with reference to FIG. 13 and FIGS. 14A-14H, as well as singulation, to form a completed package. An exemplary package 2302 is depicted in FIG. 23G for reference. Utilizing the methods described above, interconnections 1444 may be formed through vias 303 and 1803 of the embedded die assembly 1002 for interconnection of one or more components and/or other package structures, including dies 1026. However, unlike previously described examples, interconnections 1444, and/or the adhesion layer 1440 and/or seed layer 1442, may be formed directly on the sidewalls of the vias 303 (rather than within through-assembly vias formed in vias 303), as no insulating material is flowed into the vias 303 during the lamination processes of method 2200. Accordingly, since the sidewalls of vias 303 may have an oxide layer formed thereon (as described with reference to FIG. 2 and FIG. 3D), the interconnections 1444 may be formed over the oxide layer within the vias 303.

Although described above with a separate lamination process for each of the two pre-structured insulating films 1816, in certain embodiments, the method 2200 only includes a single lamination process for both films, thus reducing the amount of operations of method 2200. For example, in certain embodiments, after dies 1026 are placed in cavities 305 at operation 2204, operation 2208 may be performed, wherein the second insulating film 1816 is placed over the substrate 302. Accordingly, thereafter, at operation 2210, both insulating films 1816 may be laminated simultaneously according to the lamination parameters described above.

Note that in certain embodiments, the method 2200 may be performed with a pre-metallized substrate 302. For example, the substrate 302 may include one or more vias 302 already having plated interconnections 1444 formed therein (and/or the adhesion layer 1440 and/or seed layer 1442). Accordingly, after lamination and curing of pre-structured insulating films 1816 thereon, the pre-metallized interconnections may be extended through vias 1803 via any suitable techniques discussed herein.

Utilizing pre-structured insulating films, as described above with reference to FIGS. 17, 18A-18C, 19, 20A-20C, 21A-21B, 22, and 23A-23G, provides several advantages as compared to more traditional insulation and/or build up methods. For example, utilizing pre-structured insulating films enables formation of redistribution vias with greatly scaled down dimensions, such as diameters of about 5 μm or less, using short wavelength lasers (e.g., excimer lasers) without damaging the dielectric material thereof. Since laser ablation of the insulating films occurs before removal of the support and/or cover layers affixed thereto, the support and/or cover layers will absorb any heat accumulated at the surface of the flowable layer during structuring, and can thereafter be removed. Further, since structuring of the insulating films is performed separate from the substrate, any ablation, alteration, undercuts, and/or carbonization of previously metallized contact pads on the substrate/frame can be avoided, and no damaging etch or desmear processes may be needed to remove debris or copper overhang of previously metallized layers. Additionally, the overall number of operations necessary to form a semiconductor device package may be reduced, as several operations can be avoided (e.g., re-drilling through vias of the substrate/frame after lamination, desmear, etch, etc.), thereby making fabrication of semiconductor device packages more efficient.

The package structures formed by the methods described above, e.g., packages 1602 and 2302, may be utilized in any suitable packaging applications and in any suitable configurations. In one exemplary embodiment depicted in FIG. 24A, four packages 1602 are utilized to form a stacked DRAM structure 2400. Accordingly, each package 1602 includes a memory die 2426 (i.e., memory chip) embedded within the substrate 302 and encapsulated by the insulating layer 1018 (e.g., having a portion of each side in contact with the insulating layer 1018). One or more interconnections 1444 are formed though the entire thickness of each package 1602 and are directly in contact with one or more solder bumps 2446 disposed between major surfaces 1005 and 1007 of adjacent (i.e., stacked above or below) packages 1602. For example, as depicted in the stacked DRAM structure 2400, four or more solder bumps 2446 are disposed between adjacent packages 1602 to bridge (e.g., connect, couple) the interconnections 1444 of each package 1602 with the interconnections 1444 of an adjacent package 1602.

In certain embodiments, voids between adjacent packages 1602 connected by the solder bumps 2446 are filled with an encapsulation material 2448 to enhance the reliability of the solder bumps 2446. The encapsulation material 2448 may be any suitable type of encapsulant or underfill. In one example, the encapsulation material 2448 includes a pre-assembly underfill material, such as a no-flow underfill (NUF) material, a nonconductive paste (NCP) material, and a nonconductive film (NCF) material. In one example, the encapsulation material 2448 includes a post-assembly underfill material, such as a capillary underfill (CUF) material and a molded underfill (MUF) material. In certain embodiments, the encapsulation material 2448 includes a low-expansion-filler-containing resin, such as an epoxy resin filled with (e.g., containing) SiO₂, AlN, Al₂O₃, SIC, Si₃N₄, Sr₂Ce₂Ti₅O₁₆, ZrSiO₄, CaSiO₃, BeO, CeO₂, BN, CaCu₃Ti₄O₁₂, MgO, TiO₂, ZnO and the like.

In certain embodiments, the solder bumps 2446 are formed of one or more intermetallic compounds, such as a combination of tin (Sn) and lead (Pb), silver (Ag), Cu, or any other suitable metals thereof. For example, the solder bumps 2446 are formed of a solder alloy such as Sn—Pb, Sn—Ag, Sn—Cu, or any other suitable materials or combinations thereof. In certain embodiments, the solder bumps 2446 include C4 (controlled collapse chip connection) bumps. In certain embodiments, the solder bumps 2446 include C2 (chip connection, such as a Cu-pillar with a solder cap) bumps. Utilization of C2 solder bumps enables a smaller pitch between contact pads and improved thermal and/or electrical properties for the stacked DRAM structure 2400. In some embodiments, the solder bumps 2446 have a diameter between about 10 μm and about 150 μm, such as a diameter between about 50 μm and about 100 μm. The solder bumps 2446 may further be formed by any suitable wafer bumping processes, including but not limited to electrochemical deposition (ECD) and electroplating.

In another exemplary embodiment depicted in FIG. 24B, a stacked DRAM structure 2401 is formed by stacking four packages 1602 and directly bonding one or more interconnections 1444 of each package 1602 with the interconnections 1444 of one or more adjacent packages 1602. As depicted, the packages 1602 may be bonded by hybrid bonding, wherein major surfaces 1005 and 1007 of adjacent packages are planarized and in full contact with each other. Thus, one or more interconnections 1444 of each package 1602 are formed through the entire thickness of each package 1602 and are directly in contact with one or more interconnections 1444 of at least another adjacent package 1602.

The stacked DRAM structures 2400 and 2401 provide multiple advantages over conventional DRAM structures. Such benefits include thin form factor and high die-to-package volume ratio, which enable greater I/O scaling to meet the ever-increasing bandwidth and power efficiency demands of artificial intelligence (AI) and high performance computing (HPC). The utilization of a structured silicon frame provides optimal material stiffness and thermal conductivity for improved electrical performance, thermal management, and reliability of 3-dimensional integrated circuit (3D IC) architecture. Furthermore, the fabrication methods for through-assembly vias and via-in-via structures described herein provide high performance and flexibility for 3D integration with relatively low manufacturing costs as compared to conventional TSV technologies.

The embodiments described herein advantageously provide improved methods of substrate structuring and die assembling for fabricating advanced integrated circuit packages. By utilizing the methods described above, high aspect ratio features may be formed on glass and/or silicon substrates, thus enabling the economical formation of thinner and narrower semiconductor device packages. The thin and small-form-factor packages fabricated by utilizing the methods described above provide the benefits of not only high I/O density and improved bandwidth and power, but also greater reliability with low stress attributed to the reduced weight/inertia and package architecture allowing flexible solder ball distribution. Further merits of the methods described above include economical manufacturing with dual-sided metallization capability and high production yield by eliminating flip-chip attachment and over-molding steps, which are prone to feature damage in high-volume manufacturing of conventional and advanced packages.

While the foregoing is directed to embodiments of the present disclosure, other and further embodiments of the disclosure may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.

Claims

1. A method of forming a semiconductor device package, comprising: placing a pre-structured insulating film over a patterned substrate, the pre-structured insulating film comprising a flowable, polymer-based dielectric material, wherein the patterned substrate comprises one or more features formed in a silicon substrate, the one or more features comprising a first via and a cavity, wherein a semiconductor die is placed into the cavity prior to placement of the pre-structured insulating film over the patterned substrate, andthe pre-structured insulating film further comprising a second via formed therein, the second via aligned with the first via upon placement of the pre-structured insulating film;laminating the pre-structured insulating film onto the patterned substrate;curing the pre-structured insulating film; andforming a conductive layer extending through the first via and the second via.
2. The method of claim 1, further comprising forming the first via in the patterned substrate via a laser ablation process.
3. The method of claim 1, further comprising: structuring an insulating film to form the pre-structured insulating film, the structuring comprising: patterning one or more features into the insulating film via laser ablation, the one or more features comprising the second via; andselectively curing sidewalls of the features patterned into the insulating film to harden the sidewalls.
4. The method of claim 1, wherein the pre-structured insulating film comprises an epoxy resin.
5. The method of claim 4, wherein the epoxy resin comprises ceramic particles.
6. The method of claim 1, wherein lamination of the pre-structured insulating film onto the patterned substrate causes the flowable, polymer-based dielectric material to fill gaps between surfaces of the semiconductor die and surfaces of the cavity.
7. A method of forming a semiconductor device package, comprising: patterning one or more features into a silicon substrate, the one or more features comprising at least a first via and a cavity, wherein a semiconductor die is placed into the cavity prior to placement of the pre-structured insulating film over the patterned substrate;placing the silicon substrate onto a first pre-structured insulating film, the first pre-structured insulating film comprising a second via, the second via aligned with the first via upon placement of the silicon substrate;placing a second pre-structured insulating film over the silicon substrate, the second pre-structured insulating film comprising a third via, the third via aligned with the first via upon placement of the second pre-structured insulating film;laminating the first pre-structured insulating film and the second pre-structured insulating film onto the silicon substrate;curing the first pre-structured insulating film and the second pre-structured insulating film; andforming a conductive layer extending through at least the first via, the second via, and the third via.
8. The method of claim 7, wherein the silicon substrate is pattered via laser ablation.
9. The method of claim 7, further comprising: structuring an insulating film to form the first or second pre-structured insulating film, the structuring comprising: patterning one or more features into the insulating film via laser ablation, the one or more features comprising the second via; andselectively curing sidewalls of the features patterned into the insulating film to harden the sidewalls.
10. The method of claim 7, wherein the first or second pre-structured insulating film comprises an epoxy resin.
11. The method of claim 10, wherein the epoxy resin comprises ceramic particles.
12. The method of claim 7, wherein lamination of the pre-structured insulating film onto the silicon substrate causes the flowable, polymer-based dielectric material to fill gaps between surfaces of the semiconductor die and surfaces of the cavity.
13. A method of forming a semiconductor device package, comprising: patterning one or more features into a silicon substrate, the one or more features comprising at least a first via;placing the silicon substrate onto a first pre-structured insulating film, the first pre-structured insulating film comprising a second via, the second via aligned with the first via upon placement of the silicon substrate;exposing the first pre-structured insulating film and the silicon substrate to a first lamination process;placing a second pre-structured insulating film over the silicon substrate, the second pre-structured insulating film comprising a third via, the third via aligned with the first via upon placement of the second pre-structured insulating film;exposing the first pre-structured insulating film, the substrate, and the second pre-structured insulating film to a second lamination process;curing the first pre-structured insulating film and the second pre-structured insulating film; andforming a conductive layer extending through at least the first via, the second via, and the third via.
14. The method of claim 13, further comprising: structuring an insulating film to form the first or second pre-structured insulating film, the structuring comprising: patterning one or more features into the insulating film via laser ablation, the one or more features comprising the second via; andselectively curing sidewalls of the features patterned into the insulating film to harden the sidewalls.
15. The method of claim 13, wherein the first pre-structured insulating film or the second pre-structured insulating film comprises an epoxy resin.
16. The method of claim 15, wherein the epoxy resin comprises ceramic particles.
17. The method of claim 13, wherein the one or more features patterned into the silicon substrate further comprise a cavity, and wherein a semiconductor die is placed within the cavity prior to placement of the first pre-structured insulating film or the second pre-structured insulating film over the silicon substrate.
18. The method of claim 17, wherein lamination of the pre-structured insulating film onto the substrate causes the flowable, polymer-based dielectric material to fill gaps between surfaces of the semiconductor die and surfaces of the cavity.

US Referenced Citations (290)

Number	Name	Date	Kind
4073610	Cox	Feb 1978	A
5126016	Glenning et al.	Jun 1992	A
5268194	Kawakami et al.	Dec 1993	A
5353195	Fillion et al.	Oct 1994	A
5367143	White, Jr.	Nov 1994	A
5374788	Endoh et al.	Dec 1994	A
5474834	Tanahashi et al.	Dec 1995	A
5670262	Dalman	Sep 1997	A
5767480	Anglin et al.	Jun 1998	A
5783870	Mostafazadeh et al.	Jul 1998	A
5841102	Noddin	Nov 1998	A
5878485	Wood et al.	Mar 1999	A
6039889	Zhang et al.	Mar 2000	A
6087719	Tsunashima	Jul 2000	A
6117704	Yamaguchi et al.	Sep 2000	A
6211485	Burgess	Apr 2001	B1
6384473	Peterson et al.	May 2002	B1
6388202	Swirbel et al.	May 2002	B1
6388207	Figueroa et al.	May 2002	B1
6459046	Ochi et al.	Oct 2002	B1
6465084	Curcio et al.	Oct 2002	B1
6489670	Peterson et al.	Dec 2002	B1
6495895	Peterson et al.	Dec 2002	B1
6506632	Cheng et al.	Jan 2003	B1
6512182	Takeuchi et al.	Jan 2003	B2
6538312	Peterson et al.	Mar 2003	B1
6555906	Towle et al.	Apr 2003	B2
6576869	Gower et al.	Jun 2003	B1
6593240	Page	Jul 2003	B1
6631558	Burgess	Oct 2003	B2
6661084	Peterson et al.	Dec 2003	B1
6713719	De Steur et al.	Mar 2004	B1
6724638	Inagaki et al.	Apr 2004	B1
6775907	Boyko et al.	Aug 2004	B1
6781093	Conlon et al.	Aug 2004	B2
6799369	Ochi et al.	Oct 2004	B2
6894399	Vu et al.	May 2005	B2
7028400	Hiner et al.	Apr 2006	B1
7062845	Burgess	Jun 2006	B2
7064069	Draney et al.	Jun 2006	B2
7078788	Vu et al.	Jul 2006	B2
7091589	Mori et al.	Aug 2006	B2
7091593	Ishimaru et al.	Aug 2006	B2
7105931	Attarwala	Sep 2006	B2
7129117	Hsu	Oct 2006	B2
7166914	DiStefano et al.	Jan 2007	B2
7170152	Huang et al.	Jan 2007	B2
7192807	Huemoeller et al.	Mar 2007	B1
7211899	Taniguchi et al.	May 2007	B2
7271012	Anderson	Sep 2007	B2
7274099	Hsu	Sep 2007	B2
7276446	Robinson et al.	Oct 2007	B2
7279357	Shimoishizaka et al.	Oct 2007	B2
7312405	Hsu	Dec 2007	B2
7321164	Hsu	Jan 2008	B2
7449363	Hsu	Nov 2008	B2
7458794	Schwaighofer et al.	Dec 2008	B2
7511365	Wu et al.	Mar 2009	B2
7690109	Mori et al.	Apr 2010	B2
7714431	Huemoeller et al.	May 2010	B1
7723838	Takeuchi et al.	May 2010	B2
7754530	Wu et al.	Jul 2010	B2
7808799	Kawabe et al.	Oct 2010	B2
7839649	Hsu	Nov 2010	B2
7843064	Kuo et al.	Nov 2010	B2
7852634	Sakamoto et al.	Dec 2010	B2
7855460	Kuwajima	Dec 2010	B2
7868464	Kawabata et al.	Jan 2011	B2
7887712	Boyle et al.	Feb 2011	B2
7914693	Jeong et al.	Mar 2011	B2
7915737	Nakasato et al.	Mar 2011	B2
7932595	Huemoeller et al.	Apr 2011	B1
7932608	Tseng et al.	Apr 2011	B2
7955942	Pagaila et al.	Jun 2011	B2
7978478	Inagaki et al.	Jul 2011	B2
7982305	Railkar et al.	Jul 2011	B1
7988446	Yeh et al.	Aug 2011	B2
8069560	Mori et al.	Dec 2011	B2
8137497	Sunohara et al.	Mar 2012	B2
8283778	Trezza	Oct 2012	B2
8314343	Inoue et al.	Nov 2012	B2
8367943	Wu et al.	Feb 2013	B2
8384203	Toh et al.	Feb 2013	B2
8390125	Tseng et al.	Mar 2013	B2
8426246	Toh et al.	Apr 2013	B2
8476769	Chen et al.	Jul 2013	B2
8518746	Pagaila et al.	Aug 2013	B2
8536695	Liu et al.	Sep 2013	B2
8628383	Starling et al.	Jan 2014	B2
8633397	Jeong et al.	Jan 2014	B2
8698293	Otremba et al.	Apr 2014	B2
8704359	Tuominen et al.	Apr 2014	B2
8710402	Lei et al.	Apr 2014	B2
8710649	Huemoeller et al.	Apr 2014	B1
8728341	Ryuzaki et al.	May 2014	B2
8772087	Barth et al.	Jul 2014	B2
8786098	Wang	Jul 2014	B2
8877554	Tsai et al.	Nov 2014	B2
8890628	Nair et al.	Nov 2014	B2
8907471	Beyne et al.	Dec 2014	B2
8921995	Railkar et al.	Dec 2014	B1
8952544	Lin et al.	Feb 2015	B2
8980691	Lin	Mar 2015	B2
8990754	Bird et al.	Mar 2015	B2
8994185	Lin et al.	Mar 2015	B2
8999759	Chia	Apr 2015	B2
9059186	Shim et al.	Jun 2015	B2
9064936	Lin et al.	Jun 2015	B2
9070637	Yoda et al.	Jun 2015	B2
9099313	Lee et al.	Aug 2015	B2
9111914	Lin et al.	Aug 2015	B2
9142487	Toh et al.	Sep 2015	B2
9159678	Cheng et al.	Oct 2015	B2
9161453	Koyanagi	Oct 2015	B2
9210809	Mallik et al.	Dec 2015	B2
9224674	Malatkar et al.	Dec 2015	B2
9275934	Sundaram et al.	Mar 2016	B2
9318376	Holm et al.	Apr 2016	B1
9355881	Goller et al.	May 2016	B2
9363898	Tuominen et al.	Jun 2016	B2
9396999	Yap et al.	Jul 2016	B2
9406645	Huemoeller et al.	Aug 2016	B1
9499397	Bowles et al.	Nov 2016	B2
9530752	Nikitin et al.	Dec 2016	B2
9554469	Hurwitz et al.	Jan 2017	B2
9660037	Zechmann et al.	May 2017	B1
9698104	Yap et al.	Jul 2017	B2
9704726	Toh et al.	Jul 2017	B2
9735134	Chen	Aug 2017	B2
9748167	Lin	Aug 2017	B1
9754849	Huang et al.	Sep 2017	B2
9837352	Chang et al.	Dec 2017	B2
9837484	Jung et al.	Dec 2017	B2
9859258	Chen et al.	Jan 2018	B2
9875970	Yi et al.	Jan 2018	B2
9887103	Scanlan et al.	Feb 2018	B2
9887167	Lee et al.	Feb 2018	B1
9893045	Pagaila et al.	Feb 2018	B2
9978720	Theuss et al.	May 2018	B2
9997444	Meyer et al.	Jun 2018	B2
10014292	Or-Bach et al.	Jul 2018	B2
10037975	Hsieh et al.	Jul 2018	B2
10053359	Bowles et al.	Aug 2018	B2
10090284	Chen et al.	Oct 2018	B2
10109588	Jeong et al.	Oct 2018	B2
10128177	Kamgaing et al.	Nov 2018	B2
10153219	Jeon et al.	Dec 2018	B2
10163803	Chen et al.	Dec 2018	B1
10170386	Kang et al.	Jan 2019	B2
10177083	Kim et al.	Jan 2019	B2
10211072	Chen et al.	Feb 2019	B2
10229827	Chen et al.	Mar 2019	B2
10256180	Liu et al.	Apr 2019	B2
10269773	Yu et al.	Apr 2019	B1
10297518	Lin et al.	May 2019	B2
10297586	Or-Bach et al.	May 2019	B2
10304765	Chen et al.	May 2019	B2
10347585	Shin et al.	Jul 2019	B2
10410971	Rae et al.	Sep 2019	B2
10424530	Alur et al.	Sep 2019	B1
10515912	Lim et al.	Dec 2019	B2
10522483	Shuto	Dec 2019	B2
10553515	Chew	Feb 2020	B2
10570257	Sun et al.	Feb 2020	B2
10658337	Yu et al.	May 2020	B2
20010020548	Burgess	Sep 2001	A1
20010030059	Sugaya et al.	Oct 2001	A1
20020036054	Nakatani et al.	Mar 2002	A1
20020048715	Walczynski	Apr 2002	A1
20020070443	Mu et al.	Jun 2002	A1
20020074615	Honda	Jun 2002	A1
20020135058	Asahi et al.	Sep 2002	A1
20020158334	Vu et al.	Oct 2002	A1
20020170891	Boyle et al.	Nov 2002	A1
20030059976	Nathan et al.	Mar 2003	A1
20030221864	Bergstedt et al.	Dec 2003	A1
20030222330	Sun et al.	Dec 2003	A1
20040080040	Dotta et al.	Apr 2004	A1
20040118824	Burgess	Jun 2004	A1
20040134682	En et al.	Jul 2004	A1
20040248412	Liu et al.	Dec 2004	A1
20050012217	Mori et al.	Jan 2005	A1
20050170292	Tsai et al.	Aug 2005	A1
20060014532	Seligmann et al.	Jan 2006	A1
20060073234	Williams	Apr 2006	A1
20060128069	Hsu	Jun 2006	A1
20060145328	Hsu	Jul 2006	A1
20060160332	Gu et al.	Jul 2006	A1
20060270242	Verhaverbeke et al.	Nov 2006	A1
20060283716	Hafezi et al.	Dec 2006	A1
20070035033	Ozguz et al.	Feb 2007	A1
20070042563	Wang et al.	Feb 2007	A1
20070077865	Dysard et al.	Apr 2007	A1
20070111401	Kataoka et al.	May 2007	A1
20070130761	Kang et al.	Jun 2007	A1
20080006945	Lin et al.	Jan 2008	A1
20080011852	Gu et al.	Jan 2008	A1
20080090095	Nagata et al.	Apr 2008	A1
20080113283	Ghoshal et al.	May 2008	A1
20080119041	Magera et al.	May 2008	A1
20080173792	Yang et al.	Jul 2008	A1
20080173999	Chung et al.	Jul 2008	A1
20080296273	Lei et al.	Dec 2008	A1
20090084596	Inoue et al.	Apr 2009	A1
20090243065	Sugino et al.	Oct 2009	A1
20090250823	Racz et al.	Oct 2009	A1
20090278126	Yang et al.	Nov 2009	A1
20100013081	Toh et al.	Jan 2010	A1
20100062287	Beresford et al.	Mar 2010	A1
20100068837	Kumar et al.	Mar 2010	A1
20100144101	Chow et al.	Jun 2010	A1
20100148305	Yun	Jun 2010	A1
20100160170	Horimoto et al.	Jun 2010	A1
20100248451	Pirogovsky et al.	Sep 2010	A1
20100264538	Swinnen et al.	Oct 2010	A1
20100301023	Unrath et al.	Dec 2010	A1
20100307798	Izadian	Dec 2010	A1
20110062594	Maekawa et al.	Mar 2011	A1
20110097432	Yu et al.	Apr 2011	A1
20110111300	DelHagen et al.	May 2011	A1
20110204505	Pagaila et al.	Aug 2011	A1
20110259631	Rumsby	Oct 2011	A1
20110291293	Tuominen et al.	Dec 2011	A1
20110304024	Renna	Dec 2011	A1
20110316147	Shih et al.	Dec 2011	A1
20120128891	Takei et al.	May 2012	A1
20120146209	Hu et al.	Jun 2012	A1
20120164827	Rajagopalan et al.	Jun 2012	A1
20120261805	Sundaram et al.	Oct 2012	A1
20130074332	Suzuki	Mar 2013	A1
20130105329	Matejat et al.	May 2013	A1
20130196501	Sulfridge	Aug 2013	A1
20130203190	Reed et al.	Aug 2013	A1
20130286615	Inagaki et al.	Oct 2013	A1
20130341738	Reinmuth et al.	Dec 2013	A1
20140054075	Hu	Feb 2014	A1
20140092519	Yang	Apr 2014	A1
20140094094	Rizzuto et al.	Apr 2014	A1
20140103499	Andry et al.	Apr 2014	A1
20140252655	Tran et al.	Sep 2014	A1
20140353019	Arora et al.	Dec 2014	A1
20150187691	Vick	Jul 2015	A1
20150228416	Hurwitz et al.	Aug 2015	A1
20150296610	Daghighian et al.	Oct 2015	A1
20150311093	Li et al.	Oct 2015	A1
20150359098	Ock	Dec 2015	A1
20150380356	Chauhan et al.	Dec 2015	A1
20160013135	He et al.	Jan 2016	A1
20160020163	Shimizu et al.	Jan 2016	A1
20160049371	Lee et al.	Feb 2016	A1
20160088729	Kobuke et al.	Mar 2016	A1
20160095203	Min et al.	Mar 2016	A1
20160118325	Wang et al.	Apr 2016	A1
20160118337	Yoon et al.	Apr 2016	A1
20160270242	Kim et al.	Sep 2016	A1
20160276325	Nair et al.	Sep 2016	A1
20160329299	Lin et al.	Nov 2016	A1
20160336296	Jeong et al.	Nov 2016	A1
20170047308	Ho et al.	Feb 2017	A1
20170064835	Ishihara et al.	Mar 2017	A1
20170223842	Chujo et al.	Aug 2017	A1
20170229432	Lin et al.	Aug 2017	A1
20170338254	Reit et al.	Nov 2017	A1
20180005982	Knickerbocker	Jan 2018	A1
20180019197	Boyapati et al.	Jan 2018	A1
20180116057	Kajihara et al.	Apr 2018	A1
20180182727	Yu	Jun 2018	A1
20180197831	Kim et al.	Jul 2018	A1
20180204802	Lin et al.	Jul 2018	A1
20180308792	Raghunathan et al.	Oct 2018	A1
20180352658	Yang	Dec 2018	A1
20180374696	Chen et al.	Dec 2018	A1
20180376589	Harazono	Dec 2018	A1
20190088603	Marimuthu et al.	Mar 2019	A1
20190131224	Choi et al.	May 2019	A1
20190131270	Lee et al.	May 2019	A1
20190131284	Jeng et al.	May 2019	A1
20190189561	Rusli	Jun 2019	A1
20190229046	Tsai et al.	Jul 2019	A1
20190237430	England	Aug 2019	A1
20190285981	Cunningham et al.	Sep 2019	A1
20190306988	Grober et al.	Oct 2019	A1
20190355680	Chuang et al.	Nov 2019	A1
20190369321	Young et al.	Dec 2019	A1
20200003936	Fu et al.	Jan 2020	A1
20200039002	Sercel et al.	Feb 2020	A1
20200130131	Togawa et al.	Apr 2020	A1
20200163218	Mok	May 2020	A1
20200357947	Chen et al.	Nov 2020	A1
20200358163	See et al.	Nov 2020	A1

Foreign Referenced Citations (57)

Number	Date	Country
2481616	Jan 2013	CA
1971894	May 2007	CN
100463128	Feb 2009	CN
100502040	Jun 2009	CN
100524717	Aug 2009	CN
100561696	Nov 2009	CN
104637912	May 2015	CN
105436718	Mar 2016	CN
106531647	Mar 2017	CN
106653703	May 2017	CN
108028225	May 2018	CN
111492472	Aug 2020	CN
0264134	Apr 1988	EP
1536673	Jun 2005	EP
1478021	Jul 2008	EP
1845762	May 2011	EP
2942808	Nov 2015	EP
2001244591	Sep 2001	JP
2002246755	Aug 2002	JP
2003188340	Jul 2003	JP
2004311788	Nov 2004	JP
2004335641	Nov 2004	JP
4108285	Jun 2008	JP
2012069926	Apr 2012	JP
5004378	Aug 2012	JP
5111342	Jan 2013	JP
5693977	Apr 2015	JP
5700241	Apr 2015	JP
5981232	Aug 2016	JP
6394136	Sep 2018	JP
6542616	Jul 2019	JP
6626697	Dec 2019	JP
100714196	May 2007	KR
100731112	Jun 2007	KR
10-2008-0037296	Apr 2008	KR
2008052491	Jun 2008	KR
20100097893	Sep 2010	KR
101301507	Sep 2013	KR
20140086375	Jul 2014	KR
101494413	Feb 2015	KR
20160013706	Feb 2016	KR
20180113885	Oct 2018	KR
101922884	Nov 2018	KR
101975302	Aug 2019	KR
102012443	Aug 2019	KR
20210124920	Oct 2021	KR
I594397	Aug 2017	TW
2011130300	Oct 2011	WO
2013008415	Jan 2013	WO
2013126927	Aug 2013	WO
2015126438	Aug 2015	WO
2017111957	Jun 2017	WO
2018013122	Jan 2018	WO
2018125184	Jul 2018	WO
2019023213	Jan 2019	WO
2019066988	Apr 2019	WO
2019177742	Sep 2019	WO

Non-Patent Literature Citations (53)

Entry
PCT International Search Report and Written Opinion dated Nov. 4, 2022, for International Application No. PCT/US2022/036724.
Allresist Gmbh—Strausberg et al: “Resist-Wiki: Adhesion promoter HMDS and diphenylsilanedio (AR 300-80)—. . .—ALLRESIST GmbH—Strausberg, Germany”, Apr. 12, 2019 (Apr. 12, 2019), XP055663206, Retrieved from the Internet: URL:https://web.archive.org/web/2019041220micals-adhesion-promoter-hmds-and-diphenyl2908/https://www.allresist.com/process-chemicals-adhesion-promoter-hmds-and-diphenylsilanedio/, [retrieved on Jan. 29, 2020].
Amit Kelkar, et al. “Novel Mold-free Fan-out Wafer Level Package using Silicon Wafer”, IMAPS 2016—49th International Symposium on Microelectronics—Pasadena, CA USA—Oct. 10-13, 2016, 5 pages. (IMAPS 2016—49th International Symposium on Microelectronics—Pasadena, CA USA—Oct. 10-13, 2016, 5 pages.).
Arifur Rahman. “System-Level Performance Evaluation of Three-Dimensional Integrated Circuits”, vol. 8, No. 6, Dec. 2000. pp. 671-678.
Baier, T. et al., Theoretical Approach to Estimate Laser Process Parameters for Drilling in Crystalline Silicon, Prog. Photovolt: Res. Appl. 18 (2010) 603-606, 5 pages.
Chen, Qiao—“Modeling, Design and Demonstration of Through-Package-Vias in Panel-Based Polycrystalline Silicon Interposers for High Performance, High Reliability and Low Cost,” a Dissertation presented to the Academic Faculty, Georgia Institute of Technology, May 2015, 168 pages.
Chien-Wei Chien et al “Chip Embedded Wafer Level Packaging Technology for Stacked RF-SiP Application”,2007 IEEE, pp. 305-310.
Chien-Wei Chien et al. “3D Chip Stack With Wafer Through Hole Technology”. 6 pages.
Doany, F.E., et al.—“Laser release process to obtain freestanding multilayer metal-polyimide circuits,” IBM Journal of Research and Development, vol. 41, Issue 1/2, Jan./Mar. 1997, pp. 151-157.
Dyer, P.E., et al.—“Nanosecond photoacoustic studies on ultraviolet laser ablation of organic polymers,” Applied Physics Letters, vol. 48, No. 6, Feb. 10, 1986, pp. 445-447.
Han et al.—“Process Feasibility and Reliability Performance of Fine Pitch Si Bare Chip Embedded in Through Cavity of Substrate Core,” IEEE Trans. Components, Packaging and Manuf. Tech., vol. 5, No. 4, pp. 551-561, 2015. [Han et al. IEEE Trans. Components, Packaging and Manuf. Tech., vol. 5, No. 4, pp. 551-561, 2015.].
Han et al.—“Through Cavity Core Device Embedded Substrate for Ultra-Fine-Pitch Si Bare Chips; (Fabrication feasibility and residual stress evaluation)”, ICEP-IAAC, 2015, pp. 174-179. [Han et al., ICEP-IAAC, 2015, pp. 174-179.].
Han, Younggun, et al.—“Evaluation of Residual Stress and Warpage of Device Embedded Substrates with Piezo-Resistive Sensor Silicon Chips” technical paper, Jul. 31, 2015, pp. 81-94.
International Search Report and the Written Opinion for International Application No. PCT/US2019/064280 mailed Mar. 20, 2020, 12 pages.
International Search Report and Written Opinion dated Oct. 7, 2021 for Application No. PCT/US2021037375.
International Search Report and Written Opinion for Application No. PCT/US2020/026832 dated Jul. 23, 2020.
Italian search report and written opinion for Application No. IT 201900006736 dated Mar. 2, 2020.
Italian Search Report and Written Opinion for Application No. IT 201900006740 dated Mar. 4, 2020.
Junghoon Yeom', et al. “Critical Aspect Ratio Dependence in Deep Reactive Ion Etching of Silicon”, 2003 IEEE. pp. 1631-1634.
K. Sakuma et al. “3D Stacking Technology with Low-Volume Lead-Free Interconnections”, IBM T.J. Watson Research Center. 2007 IEEE, pp. 627-632.
Kenji Takahashi et al. “Current Status of Research and Development for Three-Dimensional Chip Stack Technology”, Jpn. J. Appl. Phys. vol. 40 (2001) pp. 3032-3037, Part 1, No. 4B, Apr. 2001. 6 pages.
Kim et al. “A Study on the Adhesion Properties of Reactive Sputtered Molybdenum Thin Films with Nitrogen Gas on Polyimide Substrate as a Cu Barrier Layer,” 2015, Journal of Nanoscience and Nanotechnology, vol. 15, No. 11, pp.8743-8748, doi: 10.1166/jnn.2015.11493.
Knickerbocker, J.U., et al.—“Development of next-generation system-on-package (SOP) technology based on silicon carriers with fine-pitch chip interconnection,” IBM Journal of Research and Development, vol. 49, Issue 4/5, Jul./Sep. 2005, pp. 725-753.
Knickerbocker, John U., et al.—“3-D Silicon Integration and Silicon Packaging Technology Using Silicon Through-Vias,” IEEE Journal of Solid-State Circuits, vol. 41, No. 8, Aug. 2006, pp. 1718-1725.
Knorz, A. et al., High Speed Laser Drilling: Parameter Evaluation and Characterisation, Presented at the 25th European PV Solar Energy Conference and Exhibition, Sep. 6-10, 2010, Valencia, Spain, 7 pages.
L. Wang, et al. “High aspect ratio through-wafer interconnections for 3Dmicrosystems”, 2003 IEEE. pp. 634-637.
Annon, John Jr., et al.—“Fabrication and Testing of a TSV-Enabled Si Interposer with Cu-and Polymer-Based Multilevel Metallization,” IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 4, No. 1, Jan. 2014, pp. 153-157.
Lee et al. “Effect of sputtering parameters on the adhesion force of copper/molybdenum metal on polymer substrate,” 2011, Current Applied Physics, vol. 11, pp. S12-S15, doi: 10.1016/j.cap.2011.06.019.
Liu, C.Y. et al., Time Resolved Shadowgraph Images of Silicon during Laser Ablation: Shockwaves and Particle Generation, Journal of Physics: Conference Series 59 (2007) 338-342, 6 pages.
Malta, D., et al.—“Fabrication of TSV-Based Silicon Interposers,” 3D Systems Integration Conference (3DIC), 2010 EEE International, Nov. 16-18, 2010, 6 pages.
Narayan, C., et al.—“Thin Film Transfer Process for Low Cost MCM's,” Proceedings of 1993 IEEE/CHMT International Electronic Manufacturing Technology Symposium, Oct. 4-6, 1993, pp. 373-380.
NT Nguyen et al. “Through-Wafer Copper Electroplating for Three-Dimensional Interconnects”, Journal of Micromechanics and Microengineering. 12 (2002) 395-399. 2002 IOP.
PCT International Search Report and Written Opinion dated Aug. 28, 2020, for International Application No. PCT/US2020/032245.
PCT International Search Report and Written Opinion dated Feb. 17, 2021 for International Application No. PCT/US2020/057787.
PCT International Search Report and Written Opinion dated Feb. 19, 2021, for International Application No. PCT/US2020/057788.
PCT International Search Report and Written Opinion dated Feb. 4, 2022, for International Application No. PCT/US2021/053821.
PCT International Search Report and Written Opinion dated Feb. 4, 2022, for International Application No. PCT/US2021/053830.
PCT International Search Report and Written Opinion dated Oct. 19, 2021, for International Application No. PCT/US2021/038690.
PCT International Search Report and Written Opinion dated Sep. 15, 2020, for International Application No. PCT/US2020/035778.
Ronald Hon et al. “Multi-Stack Flip Chip 3D Packaging with Copper Plated Through-Silicon Vertical Interconnection”, 2005 IEEE. pp. 384-389.
S. W. Ricky Lee et al. “3D Stacked Flip Chip Packaging with Through Silicon Vias and Copper Plating or Conductive Adhesive Filling”, 2005 IEEE, pp. 798-801.
Shen, Li-Cheng, et al.—“A Clamped Through Silicon Via (TSV) Interconnection for Stacked Chip Bonding Using Metal Cap on Pad and Metal Column Forming in Via,” Proceedings of 2008 Electronic Components and Technology Conference, pp. 544-549.
Shi, Tailong, et al.—“First Demonstration of Panel Glass Fan-out (GFO) Packages for High I/O Density and High Frequency Multi-chip Integration,” Proceedings of 2017 IEEE 67th Electronic Components and Technology Conference, May 30-Jun. 2, 2017, pp. 41-46.
Srinivasan, R., et al.—“Ultraviolet Laser Ablation of Organic Polymers,” Chemical Reviews, 1989, vol. 89, No. 6, pp. 1303-1316.
Taiwan Office Action dated Oct. 27, 2020 for Application No. 108148588.
Tecnisco, Ltd.—“Company Profile” presentation with product introduction, date unknown, 26 pages.
Trusheim, D. et al., Investigation of the Influence of Pulse Duration in Laser Processes for Solar Cells, Physics Procedia Dec. 2011, 278-285, 9 pages.
U.S. Office Action dated May 13, 2021, in U.S. Appl. No. 16/870,843.
Wang et al. “Study of Direct Cu Electrodeposition on Ultra-Thin Mo for Copper Interconnect”, State key lab of ASIC and system, School of microelectronics, Fudan University, Shanghai, China; 36 pages.
Wu et al., Microelect. Eng., vol. 87 2010, pp. 505-509.
Yu et al. “High Performance, High Density RDL for Advanced Packaging,” 2018 IEEE 68th Electronic Components and Technology Conference, pp. 587-593, DOI 10.1109/ETCC.2018.0009.
Yu, Daquan—“Embedded Silicon Fan-out (eSiFO) Technology for Wafer-Level System Integration,” Advances in Embedded and Fan-Out Wafer-Level Packaging Technologies, First Edition, edited by Beth Keser and Steffen Kroehnert, published 2019 by John Wiley & Sons, Inc., pp. 169-184.
Korean Office Action issued to patent application No. 10-2023-7037417 on Oct. 10, 2024.

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	20230129405 A1	Apr 2023	US

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