Patent Grant
10580710
The present technology is related to semiconductor devices, and, in particular, to semiconductor devices with a protection mechanism.
Semiconductor devices dies, including memory chips, microprocessor chips, and imager chips, typically include a semiconductor die mounted on another structure (e.g., a substrate, another die, etc.) and encased in a plastic protective covering. The die includes functional features, such as for memory cells, processor circuits, and imager devices, as well as interconnects that are electrically connected to the functional features. The interconnects can be electrically connected to terminals outside the protective covering to connect the die to higher level circuitry.
As illustrated in
With technological advancements in other areas and increasing applications, the market is continuously looking for faster and smaller devices. To meet the market demand, physical sizes or dimensions of the semiconductor devices are being pushed to the limit. For example, efforts are being made to reduce a separation distance between the die 102 and the substrate structure 106 (e.g., for 3DI devices and die-stacked packages).
However, due to various factors (e.g., viscosity level of the underfill 110, trapped air/gases, uneven flow of the underfill 110, space between the interconnets, etc.), the encapsulation process can be unreliable, such as leaving voids 114 between the die 102 and the substrate structure 106 (e.g., with portions of the interconnects failing to directly contact the underfill 110). The voids 114 can cause shorting and leakage between the interconnects (e.g., between the substrate interconnect 108 and/or between the die interconnects 104), causing an electrical failure for the semiconductor device 100. Further, as the device grows smaller, the manufacturing cost can grow (e.g., based on using nano-particle underfill instead of traditional underfill).
The technology disclosed herein relates to semiconductor devices, systems with semiconductor devices, and related methods for manufacturing semiconductor devices. The term “semiconductor device” generally refers to a solid-state device that includes one or more semiconductor materials. Examples of semiconductor devices include logic devices, memory devices, and diodes, among others. Furthermore, the term “semiconductor device” can refer to a finished device or to an assembly or other structure at various stages of processing before becoming a finished device. Depending upon the context in which it is used, the term “substrate” can refer to a structure that supports electronic components (e.g., a die), such as a wafer-level substrate or to a singulated die-level substrate, or another die for die-stacking or 3DI applications. A person having ordinary skill in the relevant art will recognize that suitable steps of the methods described herein can be performed at the wafer-level or at the die level. Furthermore, unless the context indicates otherwise, structures disclosed herein can be formed using conventional semiconductor-manufacturing techniques. Materials can be deposited, for example, using chemical vapor deposition, physical vapor deposition, atomic layer deposition, spin coating, and/or other suitable techniques. Similarly, materials can be removed, for example, using plasma etching, wet etching, chemical-mechanical planarization, or other suitable techniques.
Many embodiments of the present technology are described below in the context of protecting the semiconductor dies and the associated electrical connections. For example, semiconductor devices (e.g., 3DI packaging solutions) can each include a semiconductor die with die interconnects thereon connected to a substrate structure. To protect the die and the die interconnects (e.g., against environmental factors, such as moisture, debris, etc.), the semiconductor devices can each include a metal (e.g., copper, aluminum, alloy, etc.) enclosure that surrounds the die interconnects along a horizontal plane. The metal enclosure can further extend vertically between and/or directly contacting the die and the substrate to enclose the die interconnects. As such, the semiconductor devices can use the metal enclosure instead of any encapsulants (e.g., underfills) to isolate the die interconnects from surrounding exterior space and/or environment.
In some embodiments, the metal enclosure can be formed based on copper-on-copper (Cu—Cu) bonding (e.g., such as based on diffusion bonding techniques). In some embodiments, the metal enclosure can include solder.
In some embodiments, each semiconductor device can include multiple enclosures. For example, the semiconductor device can include a set of concentric enclosures. Also for example, the semiconductor device can include a set of enclosures that each have a different shape and/or dimension. Some of the enclosures can be used to carry signals or electrical planes (e.g., for power connection, ground planes, etc.).
As used herein, the terms “vertical,” “lateral,” “upper” and “lower” can refer to relative directions or positions of features in the semiconductor die assemblies in view of the orientation shown in the Figures. For example, “upper” or “uppermost” can refer to a feature positioned closer to the top of a page than another feature. These terms, however, should be construed broadly to include semiconductor devices having other orientations, such as inverted or inclined orientations where top/bottom, over/under, above/below, up/down and left/right can be interchanged depending on the orientation.
The semiconductor device 200 can include a metal (e.g., copper, aluminum, alloy, etc.) enclosure structure 210 (“enclosure 210”) that continuously surrounds or encloses the interconnects 204 along a horizontal plane. The enclosure 210 (e.g., a continuous and solid metallic structure that forms a wall peripherally surrounding the interconnects 204) can further extend from and directly contact a die bottom surface 222 and a substrate top surface 224 to enclose an internal space 226 (“enclosed space 226”). The enclosed space 226 can be vacuum or filled with inert or specific gas except for the interconnects 204 (e.g., without any encapculant material or underfill therein). Accordingly, the enclosure 210 can isolate the interconnects 204 from external space on the outside of the enclosure 210.
In some embodiments, the enclosure 210 can be located at an edge offset distance 228 (e.g., a distance measured along a horizontal direction) from a die periphery edge 230. In some embodiments, the enclosure 210 can be located such that an edge or a surface thereof is coplanar or coincident with the die periphery edge 230 along a vertical plane or line (e.g., where the edge offset distance 228 is 0).
For illustrative purposes, the enclosure 210 is shown having a rectangular shape, uniform thickness or width, and concentric with a shape or outline of the die 202. However, it is understood that the enclosure 210 can be different. For example, the enclosure 210 can have an oval shape, an irregular or asymmetrical shape, or any N-sided polygonal shape. Also for example, the enclosure 210 can have varying thickness or width at different portions. Also for example, the enclosure 210 can be offset or non-concentric with respect to the interconnects 204 or an arrangement thereof, the shape or outline of the die 202, or a combination thereof.
The enclosure 210 provides decrease in overall size of the semiconductor device. Because underfill is not necessary, the bond line thickness can be reduced, leading to a very low packaging height for multiple-die stacking. Further, the enclosure 210 that excludes solder (e.g., solid copper structure, such as resulting from Cu—Cu diffusion bonding) provides decrease in manufacturing cost by eliminating pillar bumping. Also, the enclosure 210 that excludes solder provides reduction in failure rates by providing clean joints without solder caps, which removes failure modes associated with solder bridging, slumping, starvation, intermetallic compound (IMC), electromagnetic (EM) effect, etc.
The enclosure 210 also provides decrease in manufacturing cost and failure rates as the package height is decreased. The enclosure 210 can protect and isolate the interconnects 204 from environmental factors (e.g., moisture, debris, etc.), which eliminates the need for underfills (e.g., nano-particle underfills). Accordingly, the costs and the error rates associated with underfill laminate or flowing process, both of which increases rapidly as the space between the die bottom surface 222 and the substrate top surface 224 decreases, can be eliminated based on using the enclosure 210 to replace the underfill. Further, the enclosure 210 provides a joint that satisfies mechanical, thermal, and electrical traits or benefits previously provided by the underfill.
The semiconductor device 400 can include multiple instances of the metal enclosure (e.g., the enclosure 210 of
In some embodiments, the first enclosure 412 can be an inner enclosure and the second enclosure 414 can be an outer enclosure. For example, the first enclosure 412 can be located closer to the interconnects 404 than the second enclosure 414, with the first enclosure 412 located between the interconnects 404 and the second enclosure 414. The first enclosure 412 can peripherally surround or encircle the interconnects 404 along a horizontal plane. Also along the horizontal plane, the second enclosure 414 can peripherally surround or encircle the first enclosure 412 and thereby the interconnects 404.
Similar to the semiconductor device 200, the semiconductor device 400 can isolate inner spaces (e.g., the second space encircled by the second enclosure 414 and the first space encircled by the first enclosure 412, where the first space and the second space can overlap) from space exterior to enclosures. One or more of the enclosed spaces can be void except for the interconnects 404 (e.g., without any encapculant material or underfill therein). Accordingly, the enclosure 210 can isolate the interconnects 204 from the external space and the corresponding environmental factors without the use of underfill or other encapsulants.
For illustrative purposes, the outer-most enclosure (e.g., the second enclosure 414 as illustrated in
The first enclosure 412 can have a first shape 502 (e.g., a shape of a cross-sectional outline), and the second enclosure 414 can have a second shape 504 that is similar to or different from the first shape 502. For illustrative purposes, the first shape 502 is shown using a circle or an oval and the second shape 504 is shown using a rectangle. However, it is understood that the first shape 502 can the second shape 504 can be different (e.g., such as for an irregular or asymmetrical shape or any N-sided polygonal shape).
Also for illustrative purposes, the first enclosure 412 and the second enclosure 414 are shown having a concentric arrangement 506 relative to each other and the die 402. However, it is understood that the first enclosure 412 and the second enclosure 414 can be offset from each other and/or offset from the die 402 for non-concentric arrangements. In some embodiments, the multiple enclosures can electrically float (e.g., without any electrical connections to circuits in the die 402) or connect to signals or electrical levels (e.g., power or ground). For example, the first enclosure 412 can have a first electrical connection 512 (e.g., active signal, power, ground, etc.) and the second enclosure 414 can have a second electrical connection 514 (e.g., active signal, power, ground, etc.). The first electrical connection 512 and the second electrical connection 514 can be connected to the same or different level or signal. In some embodiments, one of the inner electrical connections (e.g., the first electrical connection 512 as illustrated in
Also for illustrative purposes, the first enclosure 412 and the second enclosure 414 are shown as being nested (e.g., with the second enclosure 414 encircling the first enclosure 412). However, it is understood that the first enclosure 412 and the second enclosure 414 can be non-nested (e.g., arranged as non-concentric shapes, as overlapping or non-overlapping shapes, or a combination thereof).
Electrically connecting the metal enclosure(s) to communicate voltages (e.g., common source voltage or ground) and/or signals provides increased efficiency for the semiconductor device. For example, the voltage level and/or the ground can be removed from the interconnects, thereby allowing the interconnects to communicate more signals. Also for example, based on a distance or an arrangement between the interconnects and the enclosure(s), certain signals (e.g., noise sources) can be separated from the interconnects beyond the spacing allowed between the interconnects. Further, electrically connecting the metal enclosure(s) to electrical connections (e.g., ground) can further reduce errors associated with noise or electromagnetic interference (EMI).
Metal or conductive interconnects (e.g., first top interconnects 603, second top interconnects 604, bottom interconnects 605, etc.) can extend vertically to directly contact and electrically couple the dies. As illustrated in
Further similar to the semiconductor device 200 and/or the semiconductor device 400, one or more sets of the interconnects can be encircled or peripherally surrounded by one or more metal enclosures (the enclosure 210 of
In some embodiments, the dies can electrically connect to each other directly without routing through electrical circuits in an intervening die located between the coupled dies. For example, the interconnects can bypass a middle die (e.g., outside of a peripheral edge of the middle die that doesn't extend to the peripheral edges of the outer dies above and below the middle die) and directly contact the outer dies. Also for example, one or more of the dies can include one or more TSVs 608 (e.g., vertical interconnects that pass completely through the die thereon). Based on the TSVs 608, the outer dies can electrically connect to each other directly (e.g., without electrically routing through circuits in the middle die) while passing the electrical signals or levels through the middle die. The TSVs 608 can directly contact the interconnects (e.g., the first top interconnects 603, the second top interconnects 604, the bottom interconnects 605, etc.), the enclosures (e.g., the first top enclosure 612, the second top enclosure 614, the third top enclosure 616, the first bottom enclosure 618, the second bottom enclosure 620, etc.), or a combination thereof.
As discussed above, the one or more metal enclosures can be nested or concentric (e.g., as illustrated in
Electrically connecting the metal enclosure(s) to the TSVs 608 provides reduced package size. The direct contact between the enclosures that have electrical connections (e.g., to signals, power sources, ground, etc.) and the TSVs 608 can allow for increased connection possibilities by allowing pass of electrical circuits of intervening dies.
The die 802 with the die interconnects 804 and the die enclosure 806 can be manufactured using a separate manufacturing process (e.g., wafer or die level manufacturing process). The separate manufacturing process can produce the die interconnects 804 and the die enclosure 806 according to a protrusion measure 812 (e.g., a height of the metal structures, such as a length measured between the die bottom surface 222 and a distal portion of the die interconnects 804 and the die enclosure 806). In some embodiments, the protrusion measure 812 can include a distance less than 20 μm. According to the protrusion measure 812, the distal portions (e.g., relative to the die bottom surface 222) of the die interconnects 804 and the die enclosure 806 can be coplanar along a horizontal plane that is parallel with the die bottom surface 222.
As illustrated in
The substrate 906 with the substrate interconnects 904 and the substrate enclosure 910 (e.g., another die with interconnects and enclosure, such as illustrated in
As illustrated in
As illustrated in
Based on the bonding stage, the metal structures can bond or fuse and form a continuous structure. For example, the die enclosure 810 and the substrate enclosure 910 can be bonded to form the enclosure 210 of
Diffusion bonding the die enclosure 810 to the substrate enclosure 910 (e.g., Cu—Cu diffusion bonding) and the die interconnects 804 and the substrate interconnects 904 (e.g., Cu—Cu diffusion bonding) provides reduced manufacturing failures and cost. The diffusion bonding process can eliminate solder, thereby reducing any potential failures and costs associated with the soldering process. Further, the interconnects and the enclosures can be bonded using one bonding process, which can further simply the manufacturing process.
The die 1202 can further include a die enclosure 1210 (e.g., a solid metal structure, such as for a portion of the metal enclosure structure 210 of
As illustrated in
In some embodiments, the substrate enclosure 1310 can include the solder 1220 of
As illustrated in
As illustrated in
Based on reflowing the solder 1220, a continuous wall structure can be formed encircling the interconnects. For example, the die enclosure 1210 and the substrate enclosure 1310 can be bonded to form the enclosure 210 of
The method 1600 can include providing a semiconductor die (e.g., the die 602 of
In some embodiments the die enclosure can include copper, aluminum, nickel, other metals, or a combination thereof. In some embodiments the die enclosure can include solder directly contacting the die bottom surface 222 or directly attached to a distal surface or portion of a metal wall structure. In some embodiments, the die enclosure can be electrically connected (e.g., the first electrical connection 512 of
The die can be manufactured or formed using a separate manufacturing process, as illustrated at block 1620. For example, the die manufacturing process can include wafer-level processing, such as a doping process to form integrated circuitry and a singulating process to separate the individual dies.
The method 1600 can further include providing a substrate (e.g., the substrate 706 of
In some embodiments the substrate enclosure can include copper, aluminum, nickel, other metals, or a combination thereof. In some embodiments the substrate enclosure can include solder directly contacting the substrate top surface 224 or directly attached to a distal surface or portion of a metal wall structure. In some embodiments, the substrate enclosure can be electrically connected (e.g., the first electrical connection 512 or the second electrical connection 514) to a signal or a voltage level (e.g., such as a voltage source or ground).
The substrate can be manufactured or formed using a separate manufacturing process, as illustrated at block 1640. For example, the substrate manufacturing process (e.g., for manufacturing another die) can include wafer-level processing similar to processes illustrated by block 1620. Also for example, the substrate manufacturing process (e.g., for manufacturing PCB substrate) can include solder mask shaping, trace formation, planarization, etc.
The method 1600 can further include aligning the structures (e.g., the die and the substrate) as illustrated at block 1606. Aligning the structures can correspond to the stage illustrated in
The method 1600 can further include bonding the structures (e.g., the die interconnects to the substrate interconnects and/or the die enclosure to the substrate enclosure) as illustrated at block 1608. The bonding process can correspond to the stage illustrated in
Through the bonding process, the enclosure 210 (e.g., including multiple enclosures, such as the first enclosure 412 and the second enclosure 414), the enclosed space 226 can form for the interconnects 204. Since metal (e.g., copper, solder, etc.) sufficiently blocks moisture and other debris, underfill (e.g., the underfill 110 of
From the foregoing, it will be appreciated that specific embodiments of the present technology have been described herein for purposes of illustration, but that various modifications may be made without deviating from the disclosure. In addition, certain aspects of the disclosure described in the context of particular embodiments may be combined or eliminated in other embodiments. Further, while advantages associated with certain embodiments have been described in the context of those embodiments, other embodiments may also exhibit such advantages. Not all embodiments need necessarily exhibit such advantages to fall within the scope of the present disclosure. Accordingly, the disclosure and associated technology can encompass other embodiments not expressly shown or described herein.
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