The present disclosure relates to semiconductor devices and methods of forming semiconductor devices including stressed materials. For more than three decades, the continued miniaturization of silicon metal oxide semiconductor field effect transistors (MOSFETs) has driven the worldwide semiconductor industry. Various showstoppers to continued scaling have been predicated for decades, but a history of innovation has sustained Moore's Law in spite of many challenges. However, there are growing signs today that metal oxide semiconductor transistors are beginning to reach their traditional scaling limits. Since it has become increasingly difficult to improve MOSFETs and therefore complementary metal oxide semiconductor (CMOS) performance through continued scaling, methods for improving performance without scaling have become critical.
In one embodiment, a method of providing a semiconductor device is provided, in which a stress inducing material that is present atop a gate conductor of a gate structure induces a stress in a channel of a semiconductor device. In one example, a semiconductor structure including a gate structure is formed on a substrate, in which the gate structure includes at least one dummy material that is present on at least one gate conductor, wherein the at least one gate conductor is present on a gate dielectric. A conformal dielectric layer can be formed overlying the semiconductor structure. An interlevel dielectric layer may be formed on the conformal dielectric layer, in which the interlevel dielectric layer is planarized to expose at least a portion of the conformal dielectric layer that is overlying the gate structure. The exposed portion of the conformal dielectric layer is removed to expose an upper surface of the gate structure. The dummy material may be removed from the gate structure to expose the at least one gate conductor. A stress inducing material can be formed on the at least one gate conductor.
In another embodiment, a method of forming a CMOS device is provided, in which a stress inducing material that is present atop the gate conductor of the gate structures to the CMOS devices induces a stress in the channel of the semiconductor device. In one example, the
method of fabricating a CMOS device includes providing a substrate having a first device region and a second device region. A first conductivity type semiconductor device may be formed in the first device region of the substrate, in which the first conductivity type semiconductor device includes a first gate structure including at least one first dummy material that is present on at least one first gate conductor. A second conductivity type semiconductor device may be formed in the second device region of the substrate, in which the second conductivity type semiconductor device includes a second gate structure including at least one second dummy material that is present on at least one second gate conductor. At least one dielectric layer may be formed over the first conductivity type semiconductor device and the second conductivity type semiconductor device. A portion of the at least one dielectric layer may be removed to expose the first dummy material of the first conductivity type semiconductor device, wherein a remaining portion of the at least one dielectric layer is present over the second conductivity type semiconductor device. The first dummy material is removed, and a first stress inducing material is formed on an upper surface of the at least one first gate conductor. The remaining portion of the at least one dielectric layer may be removed. The second dummy material may be removed, and a second stress inducing material may be formed on an upper surface of the second gate conductor.
The following detailed description, given by way of example and not intended to limit the invention solely thereto, will best be appreciated in conjunction with the accompanying drawings, wherein like reference numerals denote like elements and parts, in which:
Detailed embodiments of the present invention are disclosed herein; however, it is to be understood that the disclosed embodiments are merely illustrative of the invention that may be embodied in various forms. In addition, each of the examples given in connection with the various embodiments of the invention are intended to be illustrative, and not restrictive. Further, the figures are not necessarily to scale, some features may be exaggerated to show details of particular components. Therefore, specific structural and functional details disclosed herein are not to be interpreted as limiting, but merely as a representative basis for teaching one skilled in the art to variously employ the present invention.
The embodiments of the present invention relate to methods for producing semiconductor devices having stress induced performance enhancements. In one embodiment, a method is provided, in which a stress inducing material is positioned atop the gate conductor of a gate structure to a semiconductor device, e.g., field effect transistor (FET), to induce a stress in the channel of a semiconductor device. When describing the inventive method and structures, the following terms have the following meanings, unless otherwise indicated.
As used herein, “semiconductor device” refers to an intrinsic semiconductor material that has been doped, that is, into which a doping agent has been introduced, giving it different electrical properties than the intrinsic semiconductor. Doping involves adding dopant atoms to an intrinsic semiconductor, which changes the electron and hole carrier concentrations of the intrinsic semiconductor at thermal equilibrium. Dominant carrier concentration in an extrinsic semiconductor determines the conductivity type of the semiconductor.
As used herein, the term “conductivity type” denotes a dopant region being p-type or n-type.
As used herein, “p-type” refers to the addition of impurities to an intrinsic semiconductor that creates deficiencies of valence electrons. In a silicon containing substrate, examples of n-type dopants, i.e., impurities include but are not limited to boron, aluminum, gallium and indium.
As used herein, “n-type” refers to the addition of impurities that contributes free electrons to an intrinsic semiconductor. In a silicon containing substrate examples of n-type dopants, i.e., impurities, include but are not limited to antimony, arsenic and phosphorous.
A “gate structure” means a structure used to control output current (i.e., flow of carriers in the channel) of a semiconducting device through electrical or magnetic fields.
As used herein, the term “channel” is the region underlying the gate structure and between the source and drain of a semiconductor device that becomes conductive when the semiconductor device is turned on.
As used herein, the term “drain” means a doped region in semiconductor device located at the end of the channel, in which carriers are flowing out of the transistor through the drain.
As used herein, the term “source” is a doped region in the semiconductor device, in which majority carriers are flowing into the channel.
The term “stress inducing liner” and “stress inducing material” denotes a material having an intrinsic stress, in which the intrinsic stress effectuates a stress in an underlying material.
The term “compressive stress inducing material” denotes a material having an intrinsic compressive stress, in which the intrinsic compressive stress produces a compressive stress in an underlying material.
The term “tensile stress inducing material” denotes a material layer having an intrinsic tensile stress, in which the intrinsic tensile stress produces a tensile stress in an underlying material.
“Epitaxial growth and/or deposition” means the growth of a semiconductor material on a deposition surface of a semiconductor material, in which the semiconductor material being grown has the same crystalline characteristics as the semiconductor material of the deposition surface.
The term “Si:C” or “carbon-doped silicon” as used herein refers to silicon having substitutional carbon atoms located therein. The substitutional carbon atoms and the silicon atoms form a silicon-carbon alloy, which is a semiconductor material.
As used herein, the terms “insulating” and “dielectric” denote a material having a room temperature conductivity of less than 10−10 (Ω-m)−1.
A “high-k” dielectric is a dielectric or insulating material having a dielectric constant that is greater than the dielectric constant of silicon oxide.
The term “direct contact” means that a first element, such as a first structure, and a second element, such as a second structure, are connected without any intermediary conducting, insulating or semiconductor layers at the interface of the two elements.
“Planarization” is a material removal process that employs at least mechanical forces, such as frictional media, to produce a planar surface.
“Chemical Mechanical Planarization” is a material removal process using both chemical reactions and mechanical forces to remove material and planarize a surface.
As used herein, the term “selective” in reference to a material removal process denotes that the rate of material removal for a first material is greater than the rate of removal for at least another material of the structure to which the material removal process is being applied.
The terms “overlying”, “atop”, “positioned on” or “positioned atop” means that a first element, such as a first structure, is present on a second element, such as a second structure, wherein intervening elements, such as an interface structure, e.g. interface layer, may be present between the first element and the second element.
The substrate 5 may be composed of a Si-containing material. The term “Si-containing” is used herein to denote a material that includes silicon. Illustrative examples of Si-containing materials include, but are not limited to: Si, SiGe, SiGeC, SiC, polysilicon, i.e., polySi, epitaxial silicon, i.e., epi-Si, amorphous Si, i.e., α:Si, and multi-layers thereof. Although silicon is the predominantly used semiconductor material in wafer fabrication, alternative semiconductor materials can be employed, such as, but not limited to, germanium, gallium arsenide, gallium nitride, silicon germanium, cadmium telluride and zinc sellenide. Although the substrate 5 is depicted as a bulk-Si substrate, semiconductor on insulator (SOI) substrates have also been contemplated and are within the scope of the present disclosure.
A plurality of well regions 21, 22 may be located within the substrate 5 and separated by a plurality of isolation regions 23. In one embodiment, the well regions 21, 22 correspond to the first and second device regions 15, 20, in which the isolation region 23 is present between the first device region 15 and the second device region 20. In one example, in which the first device region 15 is processed to provide at least one n-type field effect transistor (nFET), a first well region 21 is present in the first device region 15 being doped to a p-type conductivity. In one example, in which the second device region 20 is processed to provide at least one p-type field effect transistor (pFET), a second well region 22 is present in the second device region 20 being doped to an n-type conductivity.
The isolation regions 23 may comprise any of several dielectric isolation materials. Non-limiting examples include oxides, nitrides and oxynitrides, particularly of silicon, but oxides, nitrides and oxynitrides of other elements are not excluded. In one embodiment, the isolation regions 23 primarily comprise an oxide of silicon.
Still referring to
In one embodiment, the first conductivity type semiconductor device 25 includes a first gate structure 35, first source and drain regions 38 adjacent to the first gate structure 35, in which the first gate structure 35 further includes a first gate dielectric 39 underlying at least one first gate conductor 37. A first dummy material 36 may be present on the first gate dielectric 39. In one embodiment, the second conductivity type semiconductor device 30 includes a second gate structure 40, second source and drain regions 48 adjacent to the second gate structure 40, in which the second gate structure 40 further includes a second gate dielectric 43 underlying at least one second gate conductor 42. A second dummy material 41 may be present on the second gate dielectric 43.
The first and second gate dielectrics 39, 43 may individually comprise separate dielectric materials such as oxides, nitrides and oxynitrides of silicon that have a dielectric constant ranging from 3.9 to 10, as measured in a vacuum at room temperature. Alternatively, one or both of the first and second gate dielectric 39, 43 may be composed of a higher dielectric constant dielectric material having a dielectric constant ranging from 10 to 100. Such higher dielectric constant dielectric materials may include, but are not limited to, hafnium oxides, hafnium silicates, titanium oxides, barium-strontium-titantates (BSTs) and lead-zirconate-titanates (PZTs). The first and second gate dielectrics 39, 43 may be formed using any of several deposition and growth methods, including but not limited to, thermal or plasma oxidation or nitridation methods, chemical vapor deposition methods and physical vapor deposition methods. The first and second gate dielectrics 39, 43 may be composed of the same material or different materials. Although the first and second gate dielectrics 39, 43 are depicted in the supplied figures as each being a single layer, embodiments have been contemplated in which the first and second gate dielectrics 39, 43 are each a multi-layered structure of conductive materials. In one embodiment, the first and second gate dielectrics 39, 43 have a thickness ranging from 10 angstroms to 200 angstroms.
The first and second gate conductors 37, 42 may be composed of conductive materials including, but not limited to metals, metal alloys, metal nitrides and metal silicides, as well as laminates thereof and composites thereof. In one embodiment, the first and second gate conductors 37, 42 may be any conductive metal including, but not limited to W, Ni, Ti, Mo, Ta, Cu, Pt, Ag, Au, Ru, Ir, Rh, and Re, and alloys that include at least one of the aforementioned conductive elemental metals. The first and second gate conductors 37, 42 may also comprise doped polysilicon and/or polysilicon-germanium alloy materials (i.e., having a dopant concentration from about 1e18 to about 1e22 dopant atoms per cubic centimeter) and polycide materials (doped polysilicon/metal silicide stack materials). The first and second gate conductors 37, 42 may be composed of the same material or different materials. The first and second gate conductors 37, 42 may be formed using a deposition method including, but not limited to, salicide methods, atomic layer deposition methods, chemical vapor deposition methods and physical vapor deposition methods, such as, but not limited to evaporative methods and sputtering methods. Although the first and second gate conductors 37, 42 are depicted in the supplied figures as each being a single layer, embodiments have been contemplated in which the first and second gate conductors 37, 42 are each a multi-layered structure of conductive materials.
The first and second dummy material 36, 41 may be composed of any material that can be etched selectively to the underlying first and second gate conductors 37, 42. In one embodiment, the first and second dummy material 36, 41 may be composed of a silicon-containing material, such as polysilicon. Although, the first and second dummy material 36, 41 is typically composed of a semiconductor material, the first and second dummy material 36, 41 may also be composed of a dielectric material, such as an oxide, nitride or oxynitride material, or amorphous carbon. The first and second dummy material 36, 41 may be formed using a deposition process such as chemical vapor deposition. Variations of CVD processes include, but not limited to, Atmospheric Pressure CVD (APCVD), Low Pressure CVD (LPCVD) and Plasma Enhanced CVD (EPCVD), Metal-Organic CVD (MOCVD) and combinations thereof may also be employed. A first and second dielectric cap 3, 4 may be present on the first and second dummy material 36, 41. In one embodiment, the first and second dielectric cap 3, 4 are each composed of a dielectric material, such as an oxide, nitride or oxynitride material. In one example, the first and second dielectric cap 3, 4 are each composed of silicon nitride. In some embodiments, the first and second dielectric cap 3, 4 may be omitted from the first and second gate structures 25, 30.
The first and second gate structures 35, 40 may further comprise sidewalls spacers. In one embodiment, each of the first and second gate structures 35, 40 includes a first sidewall spacer 11 and a second sidewall spacer 12. The first and second sidewall spacers 11, 12 may be composed of materials including, but not limited to, conductive materials and dielectric materials. The spacer materials may be formed using methods that are generally conventional in the semiconductor fabrication art. Included in general are methods that are analogous, equivalent, or identical to the methods that are used for forming the isolation regions 23. The first sidewall spacer 11 and a second sidewall spacer 12 are often formed by using a blanket layer deposition and anisotropic etchback method. In one embodiment, the first sidewall spacer 11 is composed of silicon oxide and has a thickness ranging from 10 angstroms to 100 angstroms, and the second sidewall spacer 12 is composed of silicon nitride material and has a thickness ranging from 50 to 1000 angstroms. In one embodiment, the first and second gate structures 35, 40 may comprise only sidewalls spacer 12.
In one embodiment, the first conductivity type semiconductor device 25 includes first source and drain regions 38 doped with a first conductivity dopant adjacent to the first gate structure 35, and the second conductivity type semiconductor device 30 includes second source and drain regions 48 with a second conductivity dopant adjacent to the second gate structure 40. In one embodiment, the first source and drain regions 38 are implanted with an n-type dopant, in which the first conductivity type semiconductor device 25 is an n-type conductivity field effect transistor (nFET). In one embodiment, n-type FET devices are produced by doping the silicon-containing substrate 5 with elements from group V of the Periodic Table of Elements. In one embodiment, the group V element is phosphorus, antimony or arsenic. In one embodiment, the second source and drain regions 48 are implanted with a p-type dopant, in which the second conductivity type semiconductor device 30 is a p-type conductivity field effect transistor (nFET). P-type FET devices are produced by doping the silicon containing substrate 5 with elements from group III of the Periodic Table of Elements. In one embodiment, the group III element is boron, aluminum, gallium or indium.
The first and second source and drain regions 38, 48 may be doped using ion implantation. Resulting dopant concentrations for the first and second source and drain regions 38, 48 may range from 1×1018 dopant atoms per cubic centimeter to 1×1021 dopant atoms per cubic centimeter. The first and second conductivity type semiconductor devices 25, 30 may further include extension regions 49, 51 and/or halo implant regions. The implants to provide the extension regions 49, 51 and the halo implant regions may include a combination of normally incident and angled implants to form the desired grading and implant depth.
Still referring to
In one embodiment, compressive stress inducing wells (not shown) are positioned adjacent the second device channel 91 in the second source and drain regions 48. Compressive stress inducing wells formed of intrinsically compressive SiGe can be epitaxially grown atop a recessed portion of the substrate 5. The term “intrinsically compressive SiGe layer” denotes that a SiGe layer is under an intrinsic compressive stress (also referred to as an intrinsic compressive stress), in which the compressive stress is produced by a lattice mismatch between the larger lattice dimension of the SiGe and the smaller lattice dimension of the layer on which the SiGe is epitaxially grown. The compressive stress inducing wells produce a compressive stress in the second device channel 91. The Ge content of the epitaxial grown SiGe may range from 5% to 60%, by atomic weight %. In another embodiment, the Ge content of the epitaxial grown SiGe may range from 10% to 40%.
Plasma enhanced chemical vapor deposition (PECVD) can form stress inducing dielectrics having a compressive or tensile internal stress. The stress state of the stressed dielectric layer deposited by PECVD can be controlled by changing the deposition conditions to alter the reaction rate within the deposition chamber. More specifically, the stress state of the deposited stressed dielectric layer may be set by changing the deposition conditions such as: SiH4/N2/He gas flow rate, pressure, RF power, and electrode gap.
Rapid thermal chemical vapor deposition (RTCVD) can provide stress inducing dielectrics having an internal tensile stress. The magnitude of the internal tensile stress produced within the stressed dielectric layer deposited by RTCVD can be controlled by changing the deposition conditions. More specifically, the magnitude of the tensile stress within the deposited stressed dielectric layer may be set by changing deposition conditions such as: precursor composition, precursor flow rate and temperature.
In one embodiment, tensile stress inducing liner 55 formation includes PECVD of silicon nitride, in which the deposition conditions include a low frequency power ranging from 0 W to 100 W, a high frequency power ranging from 200 W to 600 W, a silane flow rate ranging from 50 sccm to 200 seem, an NH3 flow rate ranging from 1,500 sccm to 3,000 sccm, and a deposition pressure of 15 Torr or less. The tensile stress inducing liner 55 can be deposited to a thickness generally in the range from 300 angstroms to 1500 angstroms. In one embodiment, the tensile stress liner 55 has a thickness ranging from 300 angstroms to 1000 angstroms.
Optionally, silicide 52 may be formed by conventional salicide process on source/drain regions 38 and 48 before the deposition of the stress inducing liners 55 and 60.
In one embodiment, the compressive stress inducing liner 60 comprises PECVD of silicon nitride, in which the deposition conditions include a low frequency power ranging from 500 W to 1,500 W, a high frequency power ranging from 250 W to 500 W, a silane flow rate ranging from 800 sccm to 2,000 sccm, an NH3 flow rate ranging from 6,000 to 10,000 sccm, and a deposition pressure of 10 Torr or less. The compressive stress inducing liner 60 can be deposited to a thickness generally in the range of from 300 angstroms to 1500 angstroms. In one embodiment, compressive stress inducing liner 60 has a thickness ranging from 300 angstroms to 1000 angstroms.
Referring to
The interlevel dielectric layer 65 may be selected from the group consisting of silicon-containing materials such as silicon oxide, silicon nitride, SiOxNy, SiC, SiCO, SiCOH, and SiCH compounds; the above-mentioned silicon-containing materials with some or all of the Si replaced by Ge; carbon-doped oxides; inorganic oxides; inorganic polymers; hybrid polymers; organic polymers such as polyamides or SiLK™; other carbon-containing materials; organo-inorganic materials such as spin-on glasses and silsesquioxane-based materials; and diamond-like carbon (DLC, also known as amorphous hydrogenated carbon, α-C:H). Additional choices for the interlevel dielectric layer 65 include any of the aforementioned materials in porous form, or in a form that changes during processing to or from being porous and/or permeable to being non-porous and/or non-permeable.
The interlevel dielectric layer 65 may be formed by various deposition methods, including, but not limited to: spinning from solution, spraying from solution, chemical vapor deposition (CVD), plasma enhanced CVD (PECVD), sputter deposition, reactive sputter deposition, ion-beam deposition, and evaporation. The interlevel dielectric layer 65 may be planarized to expose the portion of the tensile stress inducing liner 55 and the portion of the compressive stress inducing liner 60 that is present atop the first and second gate structures 25, 30, as depicted in
Referring to
Following removal of the at least one dielectric layer, i.e., tensile stress inducing liner 55 or first portion of the conformal dielectric layer 70, the upper portion of the first gate stack 35, i.e., the first dielectric cap 3 and the first dummy material 36, may be removed by etching with an etch chemistry that is selective to the first gate structure 37. More specifically, in one embodiment, a first etch chemistry removes the first dielectric cap 3 selective to the photoresist mask 75, the interlevel dielectric 65 and the first dummy material 36. In another embodiment, a second etch chemistry removes the first dummy material 36 selective to the photoresist mask 75, the interlevel dielectric 65 and the first gate conductor 37. In one embodiment, the etch chemistry is selected to remove the first dielectric cap 3 and the first dummy material 36 selective to the photoresist mask 75, the interlevel dielectric 65 and the first gate conductor 37. The photoresist mask 75 may then be removed by a chemical stripping process. The photoresist mask 75 may also be removed during the aforementioned etch processes to remove the first dummy material 36. In one embodiment, a hardmask (e.g., amorphous carbon which is not shown) can be used in conjunction with photoresist mask 75 to facilitate the removal of the first dummy material 36.
In another embodiment, the first stress inducing material 80 may be provided by a dielectric material having an intrinsic tensile stress. In one example, the first stress inducing material 80 may be composed of a similar material and formed using a similar process as the tensile stress inducing liner 55 that is described above with reference to
Still referring of
In another embodiment, the second stress inducing material 85 may be provided by a dielectric material having an intrinsic compressive stress. In one example, the second stress inducing material 85 may be composed of a similar material and formed using a similar process as the compressive stress inducing liner 60 that is describe above with reference to
Referring to
Although, the above description is directed to a CMOS device, the method is also applicable to a MOSFT devices. Referring to
Referring to
While this invention has been particularly shown and described with respect to preferred embodiments thereof, it will be understood by those skilled in the art that the foregoing and other changes in forms and details may be made without departing from the spirit and scope of the present invention. It is therefore intended that the present invention not be limited to the exact forms and details described and illustrated, but fall within the scope of the appended claims.