Patent Application
20250157961
The present disclosure relates to a semiconductor device.
A semiconductor device is mountable on a printed circuit board. The semiconductor device includes a semiconductor element, a lead frame, a clip, and a sealing resin portion.
According to one aspect of the present disclosure, a semiconductor device includes: a semiconductor substrate for a semiconductor element; a first electrode provided on one surface of the semiconductor element and formed of an Ni plating layer; a second electrode provided on the one surface of the semiconductor element and formed of the Ni plating layer; and a partition wall formed of an insulating material and provided on the one surface of the semiconductor element to separate the first electrode and the second electrode. A phosphorus concentration in the Ni plating layer of the first electrode and the second electrode is 4 wt % or less. The partition wall has a shape protruding toward the first electrode or the second electrode.
A semiconductor device is mountable on a printed circuit board. The semiconductor device includes a semiconductor element, a lead frame, a clip, and a sealing resin portion. The semiconductor element is, for example, a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) or an Insulated-Gate Bipolar Transistor (IGBT). A structure including the semiconductor device and the printed circuit board on which the semiconductor device is mounted is called an electronic device.
The semiconductor element has electrodes on both sides. Specifically, a drain electrode is provided on the back side of the semiconductor element. A source electrode and a gate electrode are provided on the front side of the semiconductor element. The lead frame has a drain terminal and a source terminal. The drain terminal has a semiconductor element mounted on the mounting surface. That is, the drain terminal is electrically connected to the drain electrode via a conductive connecting member such as solder. The source terminal is electrically connected to the source electrode via a clip. Specifically, the clip is mainly made of a conductive material such as a metal material. The clip has an electrode facing portion facing the source electrode, a terminal facing portion facing the source terminal, and a connecting portion connecting the electrode facing portion and the terminal facing portion. The electrode facing portion, the terminal facing portion, and the connecting portion are configured as an integral part. The electrode facing portion of the clip is electrically connected to the source electrode via solder. The terminal facing portion of the clip is electrically connected to the source terminal via solder.
For example, a module including a semiconductor element (e.g., a power module) and a circuit are integrally mounted on a printed circuit board, in order to reduce the area of a semiconductor device or electronic device. Here, it is preferable that the current-carrying electrode such as drain terminal and source terminal in a semiconductor element has as large an area as possible. In order to eliminate parasitic resistance and achieve low on-resistance by adopting so-called clip mounting, it is preferable to use solder in the semiconductor device that has a higher melting point than the solder used when mounting on a printed circuit board, so as to increase the area of the current-carrying electrode. If a control electrode such as gate electrode is formed on the same surface as the current-carrying electrode, there is a concern that the element area will become large. The present disclosure has been made in view of the circumstances and the like exemplified above. The present disclosure provides, for example, a technique that can effectively realize a reduction in the area of a semiconductor device.
According to one aspect of the present disclosure, a semiconductor device includes: a semiconductor substrate constituting a semiconductor element; a first electrode provided on one surface of the semiconductor element and formed of an Ni plating layer; a second electrode provided on the one surface of the semiconductor element and formed of an Ni plating layer; and a partition wall formed of an insulating material and provided on the one surface of the semiconductor element so as to separate the first electrode and the second electrode. A phosphorus concentration in the Ni plating layer of the first electrode and the second electrode is 4 wt % or less. The partition wall has a convex shape protruding toward the first electrode or the second electrode.
Embodiments of the present disclosure will be described below with reference to the drawings. Note that the descriptions of each drawing and the corresponding device configurations and their functions or operations described below have been simplified to concisely explain the contents of this disclosure and are not intended to limit the contents of this disclosure in any way. Therefore, it goes without saying that the exemplary configurations shown in the drawings do not necessarily match the specific configurations that are actually manufactured and sold. In other words, unless the applicant explicitly limits it through the prosecution history of this application, it goes without saying that this disclosure should not be interpreted in a limited manner by the descriptions in each drawing or the corresponding descriptions of the device configuration and its functions or operations described below.
A schematic configuration of a semiconductor device 1 according to the present embodiment will be described with reference to
The semiconductor device 1 is mounted on a printed circuit board (not shown) by soldering to form an electronic device. As shown in
In this embodiment, the semiconductor device 1 is a so-called power device, that includes the semiconductor element 2 such as a MOSFET, which is a power semiconductor. As shown in
The lead frame 3 is formed of a metal plate conductor such as copper. The lead frame 3 has lead portions 32 in addition to the element mounting portion 31. The lead portions 32 are provided around the element mounting portion 31, which is also called a die pad. Of the lead portions 32, a source terminal portion 33 is joined to the clip 5 via the third solder layer 8 having a melting point of 290° C. or higher. That is, the source terminal portion 33 is electrically connected to the clip 5 via the third solder layer 8. A gate terminal portion 34 of the lead portions 32 is electrically connected to a control electrode 232 (described later) provided on the upper surface 22 of the semiconductor element 2 via the bonding wire 4.
The clip 5 is formed seamlessly and integrally from a highly conductive metal plate such as copper. The clip 5 has an element facing portion 51, a lead frame facing portion 52, and a connecting portion 53. Each of the element facing portion 51, the lead frame facing portion 52, and the connecting portion 53 is formed in a flat plate shape. The element facing portion 51 is joined to the second solder layer 7. The lead frame facing portion 52 is joined to the third solder layer 8. The element facing portion 51 and the lead frame facing portion 52 are provided in parallel to each other. The lead frame facing portion 52 is provided at a position offset from the element facing portion 51 in the thickness direction, that is, downward (toward the negative side) in the Z direction in
As the overall configuration, the semiconductor device 1 has the lead frame 3 and the clip 5. Further detailed explanation of the lead frame 3 and the clip 5 will be omitted. Hereinafter, the semiconductor device 1 will be described with reference to
As shown in
As shown in
As shown in
The passivation film 204 has a side wall 241 and a partition wall 242. The side wall 241 is provided to surround the periphery, i.e., the outer side, of the current-carrying electrode 231 and the control electrode 232. The partition wall 242 is provided between the current-carrying electrode 231 and the control electrode 232 so as to separate the current-carrying electrode 231 and the control electrode 232. In this embodiment, the partition wall 242 has a convex shape protruding toward the current-carrying electrode 231. That is, the partition wall 242 is formed in a substantially L-shape, in a plan view, that opens toward the control electrode 232. In this manner, the current-carrying electrode 231, the control electrode 232, and the partition wall 242 are disposed inside the side wall 241 formed in a substantially rectangular ring shape. The side wall 241 and the partition wall 242 are formed in a wall shape standing approximately vertically from the second interlayer interface 206 upward (along the positive side) in the Z direction. That is, the inner and outer wall surfaces of the side wall 241 and the partition wall 242 along the thickness direction are provided approximately parallel to the YZ plane. The side wall 241 and the partition wall 242 are formed seamlessly and integrally from the same material.
The partition wall 242 has a protrusion 243. The protrusion 243 is a corner of the partition wall 242 that is closest to the center position of the current-carrying electrode 231 in the in-plane direction, and is provided so as to protrude toward the center of the current-carrying electrode 231 in the in-plane direction. The protrusion 243 is formed in a rounded shape, specifically, in a plan view. Specifically, in this embodiment, the protrusion 243 is formed so that the radius of curvature of the round shape is 30 μm or more.
Hereinafter, the effects achieved by the configuration of this embodiment will be described with reference to the drawings.
In a comparison example, a circuit and a semiconductor module are integrally mounted on a printed circuit board to reduce the cost and the area in an electronic device. It is preferable that an electrode for current flow, such as the drain terminal and the source terminal, is formed with as large an area as possible in order to pass a comparatively large current therethrough. In addition, by adopting clip mounting, parasitic resistance is eliminated, achieving low on-resistance. In order to realize such a configuration, it is preferable to use a solder in the semiconductor device 1 that has a higher melting point than the solder used when mounting the semiconductor device on the printed circuit board, so as to increase the source area. When the melting point of such high melting point solder is, for example, 290° C. or higher, a processing temperature of about 390° C. is required in the mounting process. The semiconductor element 2 as the semiconductor module is plated with Ni for solder bonding. In this regard, cracks may occur in the Ni plating due to thermal stress during reflow of high melting point solder, using a medium-phosphorus Ni plating.
Further, as in a comparison example, a current-carrying electrode such as a source electrode and a control electrode such as a gate electrode may be provided on the same surface. In such a configuration, in order to reduce the area of the elements while making the area of the current-carrying electrode as large as possible, it is preferable to form the control electrode with a small area at one corner of a single rectangle within which the two electrodes are arranged in a plan view. In this case, from the viewpoint of insulation and electrode protection, it is preferable to provide a wall having a convex shape to separate the two electrodes. However, cracks are likely to occur in the Ni plating due to stress concentration caused by, for example, the convex shape of the wall.
In this regard, the inventors have focused on the following facts. As is clear from the NI-P binary system diagram, in so-called low-phosphorus Ni plating, in which the phosphorus concentration is 4 wt % or less, the phase transition temperature at which the film stress changes is high. As shown in
The preferred value of the planar shape, i.e., the radius of curvature, of the protrusion 243 can be determined taking into consideration the variety of chip sizes and other factors, as well as variations during manufacturing. Specifically, for example, the thickness of the semiconductor substrate 201 may be about 70 μm or less, or may be within a range more than 70 μm and less than 160 μm. The following will consider the specifications of the semiconductor element 2, such as the material and the thickness of the semiconductor substrate 201, and the radius of curvature of the protrusion 243 of the partition wall 242.
However, various variations due to processing tolerances and the like may occur during the actual manufacturing of products. For this reason, it is necessary to provide a margin that takes such variations into consideration. Specifically, for example, if the radius of curvature is 30 μm or more for a substrate thickness of 70 μm, and if the radius of curvature is 60 μm or more for a substrate thickness of 140 μm, it is possible to provide a sufficient margin taking into consideration variations. In both the cases of SiC substrate and Si substrate, when the radius of curvature is 60 μm or more, the maximum stress is less than 1000 MPa regardless of the substrate thickness, therefore does not exceed the fracture stress. Furthermore, in order to obtain an even larger margin, for example, if a substrate thickness of 70 μm is considered, the variation in generated stress relative to the variations in substrate thickness, plating thickness, and radius of curvature is approximately ±5%. Stable production is possible, even if a variation of 10% is taken into consideration in the development of product types such as changes in chip size, the radius of curvature that does not exceed 1259 MPa is approximately 60 μm. See the X mark, in
Considering the above-mentioned results comprehensively, when the semiconductor element 2 is formed of the semiconductor substrate 201 having a thickness of 70 μm or less, for example, 70 to 50 μm or 70 to 25 μm, it is preferable that the ratio of columnar crystal layer is 50% or less and the radius of curvature is 30 μm or more. When the semiconductor element 2 is formed of the semiconductor substrate 201 having a thickness of 160 μm or less, for example, 160 to 100 μm or 160 to 75 μm, it is preferable that the ratio of columnar crystal layer is 50% or less and the radius of curvature is 60 μm or more. As a result, the occurrence of cracks in the Ni plating layer 203 can be effectively suppressed up to a higher temperature range, i.e., up to 390° C. Furthermore, even if the radius of curvature is reduced in the comparative temperature range, i.e., 290° C., the occurrence of cracks in the Ni plating layer 203 can be effectively suppressed. The ratio of the columnar crystal layer can be set to 50% or less by appropriately adjusting the plating conditions. The crystalline state in electroless Ni plating can be changed by a complexing agent, a trace amount of additives, and the like, see, for example, the following reference material: Kamei, Masaru et al., “Influence of Kinds of Copper foil, Crystal Structure and Thickness of Electroless Ni—P on the Bend Durability of Copper Wiring” MES2016 (26th Microelectronics Symposium) Abstract Collection, September 2016, pp. 63-66, which is incorporated herein by reference. The plating conditions can be satisfactorily set without excessive trial and error, by simple and small number of trials using, for example, an L8 orthogonal table or an L12 orthogonal table in an experimental design method.
It is also preferable that the step at the first interlayer interface 205 and the second interlayer interface 206 be small at least at the position corresponding to the partition wall 242, i.e., the protrusion 243, in the in-plane direction. This effectively restricts cracks from occurring due to stress concentration. Specifically, for example, it is preferable that the first interlayer interface 205 is flattened so that the step is 0.2 μm or less. Alternatively, for example, it is preferable that the second interlayer interface 206 is flattened so that the step is equal to or smaller than a dimension corresponding to 10% of the film thickness of the base metal layer 202. Such planarization can be achieved by using, for example, BPSG reflow technology, chemical mechanical polishing, aluminum reflow technology, or the like. BPSG is an abbreviation for Boron Phosphorus Silicon Glass.
A second embodiment will be described with reference to
As shown in
A third embodiment will be described with reference to
A partition wall 242 having a substantially cross shape in a plan view is provided between the terminal electrodes 283. The partition wall 242 has a protrusion 285. The protrusion 285 is disposed at a position corresponding to the recess 284 in the terminal electrode 283. Moreover, the protrusion 285 is provided so as to fit closely with the recess 284 without any gaps in the plan view. That is, the protrusion 285 is formed in a round shape having a predetermined radius of curvature corresponding to the radius of curvature of the recess 284 in a plan view. According to this configuration, the occurrence of cracks in the terminal electrode 283 at the location where the recess 284 is provided can be effectively suppressed.
A fourth embodiment will be described with reference to
Specifically, referring to
The semiconductor substrate 201 has plural trenches 2906 between the channel layer 2901 and the source layer 2902. The trenches 2906 are formed in a stripe shape at equal intervals along the Y direction which is one of the in-plane direction on one surface of the semiconductor substrate 201, in
An interlayer insulating film 2909 is formed on one surface of the semiconductor substrate 201 adjacent to the channel layer 2901. The interlayer insulating film 2909 has a contact hole 2910 communicating with the contact trench 2903. An embedded portion 2911 is disposed in the contact hole 2910 and the contact trench 2903 and connected to the first contact region 2904 and the second contact region 2905. The embedded portion 2911 is made of, for example, a tungsten plug.
A barrier metal layer 2912 is provided between the embedded portion 2911 and the base metal layer 202. The barrier metal layer 2912 is formed by stacking, for example, titanium nitride and titanium. The first interlayer interface 205 is formed by the lower surface of the barrier metal layer 2912. The second interlayer interface 206 is formed by the upper surface of the base metal layer 202. A Pd layer 2913 and an Au layer 2914 are arranged in this order on the Ni plating layer 203.
In such a configuration, as in the first embodiment, it is preferable to reduce the step at the first interlayer interface 205 and the second interlayer interface 206 at least at positions corresponding to the partition wall 242 (i.e., the protrusion 243 and the protrusion 285) and the additional partition wall 281 (i.e., the protrusion 282). Specifically, for example, it is preferable that the step at the first interlayer interface 205 is equal to or smaller than the dimension corresponding to the film thickness of the barrier metal layer 2912, that is, 0.2 μm or smaller. This effectively restricts cracks from occurring in the Ni plating layer 203 due to stress concentration.
The present disclosure is not necessarily limited to the above embodiments. Thus, it is possible to appropriately modify the above-described embodiments. Hereinafter, typical modifications will be described. In the following description of the modifications, differences from the above embodiments will be mainly described. In the above embodiments and the modifications, the same reference numerals are assigned to the same or equivalent parts. Therefore, in the description of the following modifications, regarding components having the same reference numerals as the components of the above-described embodiment, the description in the above-described embodiment can be appropriately cited unless there is a technical inconsistency or a specific additional explanation.
The present disclosure is not limited to the specific device configurations described in the above embodiments. That is, as described above, the description of the above embodiment has been simplified in order to concisely explain the contents of the present disclosure. For this reason, illustrations and descriptions of components that are normally provided in products that are actually manufactured and sold, such as casings, bonding materials, terminals, wiring, etc., are appropriately omitted in the above embodiments and the corresponding drawings.
The present disclosure is suitably applicable to the semiconductor device 1 in various package types such as SOP, QFP, SON, and QFN. SOP is an abbreviation for Small Outline Package. QFP is an abbreviation for Quad Flat Package. SON is an abbreviation for Small Outline Non-Leaded Package. QFN is an abbreviation for Quad Flat Non-Leaded Package.
The semiconductor element 2 may have a configuration as an IGBT or an RC-IGBT in which an IGBT and a diode are integrated together. RC is an abbreviation for Reverse Conducting.
As shown in
The additional partition wall 281 may be provided to extend along the Y direction in
In the above description, plural elements formed integrally with each other with no seam may be formed by bonding separate members together. Similarly, plural elements formed by bonding separate members together may be formed integrally with each other with no seam. In the above description, plural elements formed of the same material may be formed of different materials. Similarly, plural elements formed of different materials may be formed of the same material.
The constituent element(s) of each of the above embodiments and the above modifications is/are not necessarily essential unless it is specifically stated that the constituent element(s) is/are essential in the above embodiments, or unless the constituent element(s) is/are obviously essential in principle. When numerical values such as the number, amount, dimension, and range of elements are mentioned, the present disclosure is not limited to the specific numerical values unless otherwise specified as essential or obviously limited to the specific numerical values in principle. Similarly, in the case where the shape, the direction, the positional relationship, and/or the like of the constituent element(s) is specified, the present disclosure is not necessarily limited to the shape, the direction, the positional relationship, and/or the like unless the shape, the direction, the positional relationship, and/or the like is/are indicated as essential or is/are obviously essential in principle.
The modifications are also not necessarily limited to the above examples. For example, multiple embodiments may be combined with each other unless technically inconsistent. That is, a part of one embodiment and a part of another embodiment may be combined with each other unless technically inconsistent. Furthermore, any one of the multiple embodiments and any one of the multiple modified examples may be combined with each other unless technically inconsistent. Similarly, one of the multiple modified examples may be combined with another one, unless technically inconsistent.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2022-117887 | Jul 2022 | JP | national |
The present application is a continuation application of International Patent Application No. PCT/JP2023/023837 filed on Jun. 27, 2023, which designated the U.S. and claims the benefit of priority from Japanese Patent Application No. 2022-117887, filed on Jul. 25, 2022. The entire disclosures of all of the above applications are incorporated herein by reference.
| Number | Date | Country | |
|---|---|---|---|
| Parent | PCT/JP2023/023837 | Jun 2023 | WO |
| Child | 19022203 | US |
