Patent Application
20240377851
The present disclosure relates to semiconductor devices, and in particular to a technique suitable for a band gap reference circuit and peripheral circuits thereof that inhibit the effects of stress fluctuations.
A conventional band gap reference circuit that inhibits the effects of stress fluctuations is disclosed, for example, in Patent Literature (PTL) 1. Stress fluctuations are fluctuations of stress in a semiconductor package (hereinafter also referred to simply as “package”) caused by fluctuations in external environmental conditions such as temperature and humidity. A band gap reference circuit is a circuit that uses a band gap voltage to cause an output having a negative temperature coefficient and an output having a positive temperature coefficient to cancel each other and output a constant voltage. In PTL 1, a plurality of reference voltage generation sources are connected in parallel, and an average value of the outputs of the plurality of reference voltage generation sources is used as an output. In addition, an output from a reference voltage generation source, among the plurality of reference voltage generation sources, that outputs a value deviating from a desired output value of the band gap reference circuit is blocked, thereby achieving high accuracy. In addition, the plurality of reference voltage generation sources are symmetrically arranged throughout the chip in layout to provide a configuration that is resistant to stress fluctuations and thermal distribution fluctuations.
The conventional technique described above requires a plurality of reference voltage generation sources, and the plurality of reference voltage generation sources are distributed on the chip, resulting in complicated wiring and an increase in semiconductor chip area.
In view of the above, an object of the present disclosure is to provide a semiconductor device having a configuration that is small in overall size and alleviates stress fluctuations in a package, and including a circuit that outputs a highly accurate and highly stable reference voltage.
In view of the above, a semiconductor device according to one aspect of the present disclosure includes: a lead frame; a first semiconductor chip mounted face-up above the lead frame; and a second semiconductor chip mounted face-down above the first semiconductor chip, the second semiconductor chip having a chip size smaller than a chip size of the first semiconductor chip. In the semiconductor device, the second semiconductor chip includes a bandgap element including a positive-negative (PN) junction and included in a band gap reference circuit.
According to the present disclosure, a semiconductor device having a configuration that is small in overall size and alleviates stress fluctuations in a package, and including a circuit that outputs a highly accurate and highly stable reference voltage is implemented.
These and other advantages and features will become apparent from the following description thereof taken in conjunction with the accompanying Drawings, by way of non-limiting examples of embodiments disclosed herein.
The following describes in detail embodiments according to the present disclosure, with reference to the drawings. It should be noted that each of the exemplary embodiments described below shows one specific example of the present disclosure. The numerical values, shapes, materials, structural components, the arrangement and connection of the structural components, signal waveforms, signal timing, etc. described in the following embodiments are mere examples, and therefore do not limit the scope of the present disclosure. In addition, the respective diagrams are not necessarily precise illustrations. Throughout the drawings, the same reference sign is given to substantially the same structural component, and redundant description will be omitted or simplified.
Hereinafter, a semiconductor device according to embodiments will be described with reference to the drawings.
Band gap reference circuit 120 generates reference voltage Vref from input power supply voltage VDD. Reference voltage Vref is output to power supply circuit 110 included in first semiconductor chip 103 via another connection terminal 106. Power supply circuit 110 generates power supply voltage Vdd from input power supply voltage VDD using reference voltage Vref, and supplies power to each of the other circuits included in first semiconductor chip 103.
Here, reference voltage Vref is required to be small in fluctuation and variation, and band gap reference circuit 120 is configured with various ingenuities described below to generate a stable reference voltage against temperature fluctuations. On the other hand, other than temperature fluctuations, factors that cause fluctuations in reference voltage Vref include stress due to package warpage, etc. This is because the piezo resistance effect in which resistance changes due to stress affects the characteristics of a bipolar transistor which is a main circuit element of the bandgap reference circuit. Factors that cause package warpage, etc. include the difference in the thermal expansion coefficient between the semiconductor chip and the sealing resin, and by reducing the contact area between the semiconductor chip and the sealing resin, it can be expected that stress fluctuations are alleviated. In the present disclosure, second semiconductor chip 107 has a minimum configuration including band gap reference circuit 120 to reduce the area, and is flip-chip mounted facing first semiconductor chip 103, thereby alleviating stress fluctuations due to package warpage, etc.
The following describes the details of power supply circuit 110 and band gap reference circuit 120.
First, an example of the configuration of power supply circuit 110 will be described with referenced to
Vdd=(1+R18/R17)·Vref
As described above, when reference voltage Vref is highly accurate and highly stable with less fluctuation, power supply voltage Vdd that is output by power supply circuit 110 and supplied to each of the circuits included in first semiconductor chip 103 is likewise highly accurate and highly stable, and thus the operation of each of the circuits to which power is supplied is stabilized.
Next, an example of the configuration of band gap reference circuit 120 will be described with referenced to
It is assumed that the resistance values of resistor 122 and resistor 124 are currently equal (the resistance value is assumed to be r), and that the resistance value of resistor 125 is R. NPN transistor 123 has a diode configuration in which the collector terminal and the base terminal are connected, and its base-emitter voltage is assumed to be Vbe1. N-parallel NPN transistor 126 includes N transistors of the same configuration as NPN transistor 123 which are connected in parallel, and its base-emitter voltage is assumed to be Vbe2. The inverting input terminal and the non-inverting input terminal of amplifier 127 are connected to the connection point of resistor 122 and NPN transistor 123 and the connection point of resistor 124 and resistor 125, respectively, and the output terminal of amplifier 127 is connected to the gate terminal of current supplying PMOS transistor 121. Here, current supplying PMOS transistor 121, resistor 122, resistor 124, and amplifier 127 constitute a negative feedback loop, and the inverting input terminal and the non-inverting input terminal of amplifier 127 are at the same potential. Accordingly, a current of the same value flows in the first series circuit and second the series circuit. Here, Vbe1−Vbe2=(kT/q)InN is satisfied where Boltzmann's constant is denoted by k, an absolute temperature is denoted by T, and electron charge is denoted by q. In is the natural logarithm. Accordingly, output voltage Vref of band gap reference circuit 120 is Vref=Vbe1+(r/R)·(kT/q)InN. Thus, by setting resistance ratio r/R and the total number of parallel connections N of N-parallel NPN transistor 126 to appropriate values, the negative temperature coefficient (for example, −2 mV/° C.) of base-emitter voltage Vbe1 of NPN transistor 123 can be canceled and a stable output voltage can be obtained against temperature fluctuations.
In the present disclosure, stress fluctuations due to package warpage, etc. are suppressed in second semiconductor chip 107 in which band gap reference circuit 120 is included. In other words, it is possible to provide band gap reference circuit 120 that supplies a stable reference voltage against temperatures and stress which are factors that cause voltage fluctuations.
It should be noted that, although band gap reference circuit 120 is included in second semiconductor chip 107 in the present disclosure, the configuration of the present disclosure for achieving the advantageous effect of alleviation of stress fluctuations is not limited to this configuration. It is sufficient if at least the band gap elements (in the present disclosure, NPN transistor 123 and N-parallel NPN transistor 126) included in band gap reference circuit 120 are included in second semiconductor chip 107.
As described above, the semiconductor device according to the present embodiment includes: lead frame 101; first semiconductor chip 103 mounted face-up above lead frame 101; and second semiconductor chip 107 mounted face-down above first semiconductor chip 103, second semiconductor chip 107 having a chip size smaller than a chip size of first semiconductor chip 103. In the semiconductor device, second semiconductor chip 107 includes a bandgap element (NPN transistor 123, N-parallel NPN transistor 126) including a positive-negative (PN) junction and included in band gap reference circuit 120.
According to this configuration, the semiconductor device includes first semiconductor chip 103 and second semiconductor chip 107 that is mounted above and smaller in size than first semiconductor chip 103. Second semiconductor chip 107 is minimized to a small area with a minimal configuration including a band gap element, and is flip-chip mounted facing first semiconductor chip 103. Accordingly, the overall size is reduced, stress fluctuations due to package warpage, etc. are alleviated, and as a result, a semiconductor device including a circuit that outputs a highly accurate and highly stable reference voltage is implemented.
More specifically, second semiconductor chip 107 includes band gap reference circuit 120 that receives input DC voltage VDD as an input to output reference voltage Vref, and first semiconductor chip 103 supplies input DC voltage VDD to second semiconductor chip 107 and second semiconductor chip 107 supplies reference voltage Vref to first semiconductor chip 103. As a result, second semiconductor chip 107 has a minimal configuration including band gap reference circuit 120, and thus the area of second semiconductor chip 107 is reduced and stress fluctuations due to package warpage, etc. are alleviated.
The band gap reference circuit of the present disclosure has stable characteristics against temperature and stress which are factors that cause fluctuations in reference voltage Vref that is an output. Here, a method of inhibiting variations in reference voltage Vref caused by variations in the characteristics of the structural components will further be described.
Band gap reference circuit 120A illustrated in (a) of
As described above, band gap reference circuit 120A measures reference voltage Vref that is output by applying input power supply voltage VDD, and input blowing signals (F1, F2, F3, F4) of eFuses F1 to F4 to the blowing circuit (not illustrated) so as to bring reference voltage Vref closer to the target value, thereby allowing trimming to fine-tune reference voltage Vref.
Second semiconductor chip 107 requires inspection terminals including input terminals for trimming information (e.g., a data terminal and a clock terminal of an inter-integrated circuit (I2C) (input terminals Data and CLK described below with referenced to
One advantageous effect is the alleviation of stress generated from the difference in thermal expansion of connection materials due to not increasing the total number of connection terminals between first semiconductor chip 103 and second semiconductor chip 107. Inhibiting fluctuations of the reference voltage, etc. by stress alleviation is an essence of the present disclosure. However, the difference in thermal expansion coefficients between the connection terminals and the interchip sealing resin is another factor that causes stress on second semiconductor chip 107, and thus, for example, the total number of connection terminals is minimized.
Another advantageous effect is the reduction of inspection time by conducting the inspection of second semiconductor chip 107 with a plurality of chips at the same time, in the process before second semiconductor chip 107 is mounted on first semiconductor chip 103. In the inspection and adjustment process, voltage information at a plurality of temperatures such as high, normal, and low temperatures and the optimal trimming information according to the voltage information are set. If this is conducted in the package inspection after mounting on first semiconductor chip 103, the inspection time would increase because the measurement of a plurality of items at the same time as in the chip inspection is not possible.
It should be noted that, the illustration of the blowing circuit that receives blowing signals (F1, F2, F3, F4) as inputs and blows the eFuse designated is omitted because it is not the essence of present disclosure and is also complicated. In addition, the eFuse described above is one example of fine-tuning, and thus the present disclosure is not limited to this configuration. There are other ways to use switch elements, etc. other than the eFuse to adjust each parameter including the resistance value, and in such cases, the means to hold inspection data including trimming information is also effective.
As described above, in the semiconductor device according to the present embodiment, second semiconductor chip 107 includes: input terminal Data through which trimming information for adjusting reference voltage Vref output by band gap reference circuit 120A is input; and storage circuit (LOGIC section) for holding the trimming information. According to this configuration, it is possible to inspect second semiconductor chip 107 with a plurality of chips at the same time, and receive trimming information as an input. As a result, inspection and adjustment time is reduced.
One factor that causes variation in reference voltage Vref output by band gap reference circuit is the variation of base-emitter voltage Vbe of the transistor. In Embodiment 3, this variation is inhibited.
An input voltage to filter circuit 132 is referred to as pre-reference voltage Vref1. Pre-reference voltage Vref1 is input to buffer circuit 133 included in first semiconductor chip 103 through filter circuit 132, and reference voltage Vref is supplied from buffer circuit 133. For the convenience of explanation, the divider signal is assigned with the same reference sign as the switch to be driven.
In the first period of signal CLK illustrated in
Filter circuit 132 constitutes a low-pass filter including a resistor and a capacitor as illustrated in
As illustrated in
As described above, according to the present embodiment, by using an average value of nine transistors as the base-emitter voltage which is the main setting element of reference voltage Vref, the variation of the base-emitter voltage is inhibited. The technique of correcting manufacturing variations in a unit element included in the configuration by using the average of the characteristics of a plurality of elements is called dynamic element matching (DEM). In the embodiments of the present disclosure, the circuits necessary for DEM (the frequency divider circuit, the selection circuit, and the filter circuit in the present embodiment) are provided on second semiconductor chip 107, and signal CLK is transmitted from first semiconductor chip 103, thereby allowing reference voltage Vref with low noise and inhibited variation to be supplied to each circuit included in first semiconductor chip 103, in addition to achieving the effect of inhibiting stress fluctuations.
As described above, in the semiconductor device according to the present embodiment, first semiconductor chip 103 and second semiconductor chip 107 include, as a terminal connecting each other, a clock terminal (input terminal CLK illustrated in
In addition, first semiconductor chip 103 and second semiconductor chip 107 include, as a terminal connecting each other, a power supply terminal (power supply terminal VDD), a first ground terminal (power supply terminal VSS), a reference voltage terminal (output terminal Vref), and a second ground terminal (output terminal SVSS), input DC voltage VDD is supplied from first semiconductor chip 103 to second semiconductor chip 107 via the power supply terminal (power supply terminal VDD) and the first ground terminal (power supply terminal VSS) included in first semiconductor chip 103 and second semiconductor chip 107, and reference voltage Vref is supplied from second semiconductor chip 107 to first semiconductor chip 103 via the reference voltage terminal (output terminal Vref) and the second ground terminal (output terminal SVSS) included in first semiconductor chip 103 and second semiconductor chip 107. As a result, since reference voltage Vref is supplied using the second ground terminal (output terminal SVSS) as the reference terminal which is different from the first ground terminal (power supply terminal VSS) where potential fluctuation and noise superposition can occur, a highly accurate and low-noise reference voltage Vref can be obtained.
In addition, band gap reference circuit 120B includes filtering circuit 132 that outputs reference voltage Vref. According to this configuration, it is possible to inhibit the generation of noise due to periodic switching of the combination of the devices to be used among the plurality of devices according to clock signal CLK.
Although filter circuit 132 is included in second semiconductor chip 107 so as to prioritize the noise inhibiting effect in the present embodiment, if the priority is to reduce the area of second semiconductor chip 107, filter circuit 132 may be included in first semiconductor chip 103. In such a case, for example, filter circuit 132 is placed near the connection terminal to reduce, as much as possible, pattern wiring on which noise is superimposed.
As described above, in the semiconductor device according to the present embodiment, first semiconductor chip 103 includes ADC 140 that receives reference voltage Vref, and clock signal CLK supplied from first semiconductor chip 103 to second semiconductor chip 107 is synchronized with a sampling period of ADC 140 with a phase difference. According to this configuration, it is possible to inhibit the effect of noise superimposed on reference voltage Vref and dedicated ground SVSS in ADC 140, and inhibit an output error of ADC 140.
With a semiconductor device according to Embodiment 4, it is possible to easily determine anomaly of the band gap reference circuit. In the present embodiment, in order to determine whether the reference voltage output by the band gap reference circuit is a normal value or not, another similar band gap reference circuit is provided and the outputs of both circuits are compared. For example, the reference voltage output by the band gap reference circuit is determined as normal if the difference between the reference voltages output by the both circuits is less than or equal to a predetermined value, and determined as anomalous if the difference exceeds the predetermined value.
As described above, in the semiconductor device according to the present embodiment, first semiconductor chip 103 includes secondary band gap reference circuit 150. First semiconductor chip 103 includes anomaly determiner circuit 151 that determines anomaly of reference voltage Vref by comparing reference voltage Vref with the output voltage from secondary band gap reference circuit 150. In this manner, it is possible to determine whether the reference voltage output by the band gap reference circuit has a normal value. In addition, since secondary band gap reference circuit 150 for which high accuracy is not required is included in first semiconductor chip 103, the increase in area of second semiconductor chip 107 is inhibited.
Embodiments 1 to 4 have described embodiments of providing a band gap reference circuit that generates a highly accurate and highly stable reference voltage by taking advantage of stress fluctuation alleviation to second semiconductor chip 107. Here, a reference current supply circuit that generates a reference current may be provided to second semiconductor chip 107.
In the present embodiment, gate terminal Ibias1 of PMOS transistors 204 to 206, drain terminal Ic1 of PMOS transistor 206, gate terminal Ibias2 of NMOS transistors 207 to 208, and drain terminal Ic2 of NMOS transistor 208 are connected to first semiconductor chip 103 as current supply output terminals. It is assumed that constant current Ic1 flows out from terminal Ic1 and constant current Ic2 flows in from terminal Ic2. When each transistor size is the same, the current ratio of the current mirror; that is, a mirror ratio, is 1, and Ic0=Ic1=Ic2. On second semiconductor chip 107 in which stress fluctuations are alleviated and fluctuations in transistor characteristics are inhibited, fluctuations in the mirror ratio are also inhibited. In addition, although illustrations and detailed descriptions are omitted, resistance value R3 of resistor 203 can also be fine-tuned as with resistor 125A of band gap reference circuit 120A described above, and thus constant currents Ic1 and Ic2 with high accuracy and inhibited fluctuations and variations can be supplied to first semiconductor chip 103.
When the inhibiting of fluctuations of the mirror ratio is not required much, a current mirror of PMOS transistor 209 and NMOS transistor 210 may be included in first semiconductor chip 103 using terminals Ibias1 and Ibias2, as illustrated in first semiconductor chip 103 of
As described above, in the semiconductor device according to the present embodiment, second semiconductor chip 107 includes reference current supply circuit 200 that generates a reference current using reference voltage Vref, and the reference current generated by reference current supply circuit 200 is supplied from second semiconductor chip 107 to first semiconductor chip 103. As a result, a highly accurate and highly stable reference current is supplied from second semiconductor chip 107 in addition to a highly accurate and highly stable reference voltage.
In the diagram, the BGR section is a band gap reference circuit which generates pre-reference voltage Vref1 from input power supply voltage VDD from power supply terminal VDD and outputs pre-reference voltage Vref1 to the Filter section which is filter circuit 132 described in
The LOGIC section performs switching operation according to clock signal CLK from input terminal CLK, and thus noise is generated. In order to improve the noise inhibiting effect in the Filter section, output terminals Vref and SVSS are not located near a noise generation source but are placed at a distance from the noise generation source, for example. Therefore, as illustrated in
It should be noted that, although input power supply voltages VDD and VSS are supplied to each of the circuit sections illustrated in
As described above, in the semiconductor device according to the present embodiment, the reference voltage terminal (output terminal Vref) and the second ground terminal (output terminal SVSS) are disposed on an opposite side or a diagonal corner of second semiconductor chip 107 from the clock terminal (input terminal CLK). As a result, the reference voltage terminal (output terminal Vref) and the second ground terminal (output terminal SVSS) are located away from a noise generation source caused by the switching operation according to clock signal CLK, thereby reducing the deterioration of the accuracy of reference voltage Vref due to noise.
It should be noted that second semiconductor chip 107 may have a dielectric isolation structure. The dielectric isolation structure is a structure in which a semiconductor element formation substrate is provided on a semiconductor support substrate via an inter-substrate insulation layer. The characteristics of a bipolar transistor used in a bandgap reference circuit is affected by leakage current due to thermal fluctuations. In other words, the dielectric isolation structure with low leakage current leads to high stability of the reference voltage which is the output of the band gap reference circuit.
Although the semiconductor device according to the present disclosure has been described so far based on Embodiments 1 to 6, the present disclosure is not limited to the above embodiments. Those skilled in the art will readily appreciate that various modifications may be made in these embodiments and that other embodiments may be obtained by arbitrarily combining the elements of these embodiments and working examples without materially departing from the novel teachings and advantages of the present disclosure. Accordingly, all such modifications and other embodiments are included in the present disclosure.
For example, ADC 140 according to Embodiment 3, secondary band gap reference circuit 150 and anomaly determiner circuit 151 according to Embodiment 4, and reference current supply circuit 200 according to Embodiment 5 may be provided in the semiconductor device according to Embodiment 1.
In addition, although the semiconductor device is provided with a band gap reference circuit according to the foregoing embodiments, it is not necessary to include a band gap reference circuit itself, but it is sufficient if a band gap element including a PN junction and included in the band gap reference circuit is included.
Although only some exemplary embodiments of the present disclosure have been described in detail above, those skilled in the art will readily appreciate that many modifications are possible in the exemplary embodiments without materially departing from the novel teachings and advantages of the present disclosure. Accordingly, all such modifications are intended to be included within the scope of the present disclosure.
The present disclosure can be used as a semiconductor device, in particular as a semiconductor device having a configuration that is small in overall size and alleviates stress fluctuations in a package, and including a circuit that outputs a highly accurate and highly stable reference voltage.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2022-014202 | Feb 2022 | JP | national |
This is a continuation application of PCT International Application No. PCT/JP2023/002372 filed on Jan. 26, 2023, designating the United States of America, which is based on and claims priority of Japanese Patent Application No. 2022-014202 filed on Feb. 1, 2022. The entire disclosures of the above-identified applications, including the specifications, drawings and claims are incorporated herein by reference in their entirety.
| Number | Date | Country | |
|---|---|---|---|
| Parent | PCT/JP2023/002372 | Jan 2023 | WO |
| Child | 18781507 | US |
