1. Field of the Invention
The present invention relates to a semiconductor device and, more particularly, a semiconductor device having a wafer-level package structure that makes it possible to execute the CSP (Chip Size Package) process on the wafer.
2. Description of the Related Art
In recent years, development of the LSI technology as the key technology to implement the multimedia equipments is proceeding steadily to the higher speed and the larger capacity of the data transmission. A higher density of the packaging technology as the interface between the LSI and the electronic equipment is also promoted pursuant to this progress.
As the IC package to meet such requirements, there is known the CSP (Chip Size Package) that is packaged in the almost same size as a chip size. In addition, there is known the wafer-level CSP from which individual CSP can be obtained by executing film formation, processing, etc. required for the CSP structure at the wafer stage and then dicing such wafer.
(Related Art 1)
In the bump forming method in the wafer-level CSP according to the related art 1, as shown in
Then, as shown in
Then, as shown in
Then, as shown in
Then, as shown in
Then, as shown in
(Relate Art 2)
In other words, a metal wire made of gold, or the like is pulled out from the capillary of the wire bonder by a predetermined length. Then, the top end portion of this metal wire is rounded like a ball by the electric discharge. Then, the ball-like top end portion of the metal wire is brought into contact with the electrode pad 104 by lowering the capillary. Then, the metal wire is jointed to the electrode pad 104 by applying the heat and the ultrasonic vibration.
Then, the metal wire is pulled off by fixing the metal wire by the clamper while pulling up the capillary. Thus, the stud bumps 112x that are connected electrically to the electrode pad 104 and have the pointed top end are formed.
(Related Art 3)
Then, as shown in
Then, as shown in
Then, as shown in
In the related art, according to the method such as one of the above-described related arts 1 to 3, etc., the metal bumps that are connected electrically to the electrode pads 104 are formed, and then the semiconductor substrate 100 is diced. Thus, the semiconductor devices each having the CSP structure are manufactured.
In the related art 1, when the metal bumps 112 are to be jointed to the connecting pads on the wiring substrate, the top end surfaces, which have a relatively large area, of the metal bumps 112 and the connecting pads are jointed together via the solder paste, or the like. Therefore, an amount of solder that is interposed between the metal bumps 112 and connecting pads is increased indispensably. As a result, there is caused such a problem that a thickness of the electronic parts in which the semiconductor device and the wiring substrate are jointed together is increased.
In addition, when the barrier film patterns 108a are formed by wet-etching the barrier conductive film 108, a depth of side-etching of the barrier conductive film 108 that comes into contact with the metal bump 112 is relatively large. Thus, the metal bumps 112 must be formed larger than the electrode pad 104 by estimating such depth of side-etching. Therefore, the method in the related art 1 cannot easily deal with the case that the pitch between the electrode pads 104 should be narrowed, and also it is possible that the metal bumps 112 come into contact with each other.
Also, in the related art 2, since the stud bumps 112x are formed by bonding the metal wire with the pressure, the area of the top end surface that is jointed to the connecting pad on the wiring substrate tends to reduce. Thus, there is such a possibility that reliability of the jointing is lowered. Also, since the wire-bonding equipment is used, there is a limit to the pitch between the formed stud bumps 112x and also there is a limit to the reduction in size of the stud bump 112x itself. As a result, the method in the related art 2 cannot easily deal with the case that the pitch between the electrode pads 104 should be narrowed.
Also, in the related art 3, since the solder balls 112y are employed, it is difficult to reduce the thickness of the electronic parts because of the same reason as the related art 1. Also, when the solder balls 112y are electrically jointed to the barrier conductive film 108 by the reflow-heating, such solder balls 112y are also re-flown in the lateral direction. As a result, the method in the related art 3 cannot easily deal with the case that the pitch between the electrode pads 104 should be narrowed, and also there is such a possibility that the solder bumps 112z come into contact with each other.
In this case, in Patent Application Publication (KOKAI) 2001-57374, the semiconductor device having the conductive bumps that are connected to the bonding pads on the semiconductor substrate is set forth. But no regard is paid to the above-mentioned problems.
It is an object of the present invention to provide a semiconductor device having a wafer-level CSP structure, capable of reducing a thickness of an electronic parts in which a semiconductor device and a wiring substrate are jointed together, and capable of dealing easily with a narrower pitch between electrode pads, and thus improving the reliability of the jointing to the wiring substrate.
The present invention is concerned with a semiconductor device having a wafer-level package structure in which CSP structures are formed at a wafer level, which comprises a semiconductor substrate; an electrode pad formed over the semiconductor substrate; and a tail terminal formed to have an area that is smaller than the electrode pad and connected electrically to the electrode pad.
In the present invention, the column-like tail terminal having an area smaller than that of the electrode pad is formed on the electrode pad of the semiconductor device in such a state that it is connected electrically to the electrode pad. For example, a diameter of the tail terminal is set to about ⅓ to ⅔ of a diameter of the electrode pad, and the tail terminal is formed on the center portion of the electrode pad.
Since such structure is employed, an area of a top end surface of the tail terminal can be reduced when the semiconductor device is mounted on the wiring substrate. Therefore, an amount of the jointing material such as the solder, which joints the tail terminal portion of the semiconductor device and the connecting pad of the wiring substrate, or the like can be reduced rather than the related art. In addition, since the jointing material is also formed around side surfaces of the tail terminal, not only the top end surface of the tail terminal but also the side surfaces thereof can act as the jointing portion. In other words, although an amount of the jointing material is reduced by employing the tail terminal having a diameter that is smaller than that of the electrode pad as the connecting electrode, the sufficient jointing area can be assured.
In this manner, while assuring the reliability of the jointing to the wiring substrate, an amount of the jointing material that is interposed between the semiconductor device and the wiring substrate can be reduced. Therefore, a thickness of the electronic parts in which the semiconductor device is mounted on the wiring substrate can be reduced.
Also, the structure in which the conductive body such as the jointing material, or the like seldom protrudes from the electrode pad area to the outside can be formed. Thus, even if the pitch between the electrode pads is narrowed, generation of the electric short circuit between the electrode pads can be prevented. Therefore, the present invention can easily deal with the narrower pitch between the electrode pads.
In one preferred mode of the present invention, the electrode pad and the tail terminal are covered with the barrier conductive film, and also the resin layer is formed to expose the tail terminal portion and its neighboring area.
According to this, since the electrode pad and the tail terminal are covered with the barrier conductive film, mutual diffusion of materials between the jointing material, the tail terminal, and the electrode pad can be prevented and also the reliability of the semiconductor device can be improved.
Also, since the resin layer is provided on the outside of the tail terminal such that areas containing the tail terminal are exposed, protrusion of the jointing material from the electrode pad area to the outside can be suppressed physically. Therefore, the present invention can deal with the much more narrow pitch between the electrode pads.
Otherwise, the structure in which the barrier conductive film is formed between the electrode pad and the tail terminal may be employed. In this case, even if the materials of the electrode pad and the tail terminal are different, mutual diffusion of these materials can be prevented and also the reliability of the semiconductor device can be improved.
Embodiments of the present invention will be explained with reference to the drawings hereinafter.
(First Embodiment)
In
These Cu electrode pads 14 are of the area-array type and are arranged in plural on the overall surface of the chip area over the semiconductor substrate 10. Also, the passivation film 16 is made of a silicon nitride (SiN) film whose film thickness is about 15 μm, for example.
In the semiconductor device manufacturing method according to the first embodiment of the present invention, first the semiconductor substrate 10 having such a structure that the Cu electrode pads 14 are exposed from the opening portions 16a in the passivation film 16 shown in
Then, as shown in
Then, as shown in
Then, as shown in FIG. 4E and
Since this tail terminal 20 is formed in the opening portion 18a of the first dry-film photoresist 18, its height is formed at about 25 to 200 μm. Also, it is preferable that the tail terminal 20 should be formed in the center portion of the Cu electrode pad 14 such that its diameter is set to ⅓ to ⅔, about ½ as the optimum value, of a diameter of the Cu electrode pad 14.
In this case, the tail terminal 20 may be formed in any manner if its area is smaller than an area of the Cu electrode pad 14. Also, such tail terminal 20 may be formed at a position that is displaced from the center portion of the Cu electrode pad 14.
Also, it is preferable that a height of the tail terminal 20 should be set higher. But such height can be adjusted appropriately with regard to the area of the Cu electrode pad 14, the area of the tail terminal 20, characteristics of the electronic parts into which the semiconductor device is packaged, etc.
For example, if a size of the Cu electrode pad 14 is about 60 μm□, preferably the tail terminal 20 should be formed to have a size of about 30 μm□ and a height of about 50 μm□.
Then, as shown in
The barrier conductive film 22 is not limited to the above laminated film. A metal film made of a metal selected from nickel (Ni), platinum (Pt), gold (Au), chromium (Cr), titanium (Ti), tungsten (W), palladium (Pd), and the like, or a laminated film made of them may be employed.
Then, as shown in
Then, as shown in FIG. 4J and
Then, as shown in
As shown in
According to the above, the semiconductor device having the wafer-level CSP structure according to the first embodiment of the present invention is completed. In this case, as the semiconductor device according to the first embodiment of the present invention, the semiconductor wafer 1 having the CSP structure may also be used, or the semiconductor chip 1a having the CSP structure, which is obtained by separating the semiconductor wafer 1 into individual pieces by means of the dicing, may also be used.
Next, a method of mounting the semiconductor chip 1a with this CSP structure on the wiring substrate will be explained hereunder. First, as shown in
Then, the semiconductor chip 1a is mounted on the wiring substrate 30 such that the tail terminal 20 portions of the semiconductor chip 1a having the above CSP structure are arranged in registration with the connecting pads 32 of the wiring substrate 30.
Then, solder layers 34 are formed by executing the reflow soldering at the temperature of about 200 to 250° C. As a result, the Cu electrode pads 14 and the tail terminals 20 of the semiconductor chip 1a are connected electrically to the connecting pads 32 of the wiring substrate 30 via the barrier film patterns 22a and the solder layers 34. In this case, the jointing material such as the conductive resin, or the like may be used in place of the metal brazing material such as the solder layer 34, etc.
As described above, in the semiconductor chip 1a having the CSP structure according to the present embodiment, the column-like tail terminals 20 whose top end area is smaller than the area of the Cu electrode pad 14 are formed on the Cu electrode pads 14 in such a manner that they are connected electrically to the Cu electrode pads 14. Then, the Cu electrode pad 14 and the tail terminal 20 are covered with the barrier film pattern 22a. Then, preferably the resin layer 26 should be formed to expose the tail terminal 20 portions and their neighboring areas.
Since the area of the top end surface of the tail terminal 20 is reduced smaller by employing such structure, an amount of solder paste that is coated on the connecting pads 32 of the wiring substrate 30 can be reduced smaller rather than the related art. In addition, since the solder layers 34 are formed such that the solder paste is filled into spaces between side surfaces of the tail terminal 20 portions and the resin layer 26, not only the top end surface of the tail terminal 20 but also the overall side surfaces thereof can act as the jointing portion.
Therefore, although the column-like tail terminal 20 portion that is narrower than the related art is employed as the connecting electrode and also a coated amount of the solder paste is reduced, the large jointing area can be assured between the tail terminal 20 and the connecting pad 32 of the wiring substrate 30 via the solder layer 34. As a result, the reliability of the jointing to the wiring substrate 30 can be improved.
Also, since a film thickness of the solder layer 34 that is interposed between the semiconductor chip 1a and the wiring substrate 30 can be reduced, a thickness of the electronic parts in which the semiconductor chip 1a is mounted on the wiring substrate 30 can also be reduced. In addition, since the structure in which the solder layer 34, the barrier film pattern 22a, and the tail terminal 20 seldom protrude from the Cu electrode pad 14 area to the outside can be obtained, generation of the electric short-circuit between the Cu electrode pads 14 can be prevented even if the pitch between the Cu electrode pads 14 is narrowed. Thus, the method of the first embodiment of the present invention can easily deal with the case that the pitch between the electrode pads 14 should be narrowed.
Also, the Cu electrode pad 14 and the tail terminal 20 are covered with the barrier film pattern 22a. Therefore, mutual diffusion between materials of the solder layer 34, the tail terminal 20, and the Cu electrode pad 14 can be prevented, and thus reliability of the semiconductor device can be improved.
In this case, in case the resin layer 26 is omitted, protrusion of the solder paste in the lateral direction can be prevented to some extent by the surface tension of the solder that are melted when the reflow soldering is executed. However, from such a viewpoint that the Cu electrode pads are caused to deal with the narrower pitch by suppressing further the protrusion of the solder layer 34 from the Cu electrode pad 14 area to the outside, it is preferable that the resin layer 26 should be provided.
(Second Embodiment)
In the semiconductor device manufacturing method according to the second embodiment, like
Then, as shown in
Then, as shown in
Then, as shown in
Then, as shown in
Then, as shown in FIG. 7H and
Then, as shown in FIG. 7J and
Then, as shown in
Then, like the first embodiment, the semiconductor substrate 10 is subjected to the dicing, and thus individual semiconductor chips each having the CSP structure are obtained.
Then, as shown in
According to the semiconductor chip 1b of the second embodiment, the concave portion due to the opening portion 16a of the passivation film 16 is not formed around the root portion of the tail terminal 20. Therefore, in addition to the similar advantages to the first embodiment, a coated amount of the solder paste can be reduced rather than the first embodiment, and thus a thickness of the electronic parts can be further reduced. In particular, if the passivation film 16 is formed as a thick film, a coated amount of the solder paste can be reduced remarkably.
(Third Embodiment)
The third embodiment shows such a manner that the Al-series electrode pad made of aluminum (Al) or Al alloy such as Al—Cu, or the like is used as the electrode pad of the semiconductor device.
In the semiconductor device manufacturing method according to the third embodiment, as shown in
Then, as shown in
Then, as shown in FIG. 9C and
Then, as shown in FIG. 9E and
Then, as shown in FIG. 9G and
Then, as shown in FIG. 9I and
As a result, the tail terminals 20 that are connected electrically to the Al-series electrode pads 14a via the barrier film patterns 25a can be obtained. The barrier film patterns 25a have respective functions of improving the adhesiveness between the Al-series electrode pads 14a and the tail terminals 20, and preventing mutual diffusions of these materials, and preventing diffusion of the solder from the solder layer to the Al-series electrode pads 14a side at the time of mounting.
Then, like the first embodiment, the semiconductor substrate 10 is separated into individual pieces by the dicing, and thus individual semiconductor chips each having the CSP structure can be obtained.
Then, as shown in
In this case, such a mode is shown that the resin layer is not formed. However, like the first and second embodiments, such a mode may be employed that the resin layer is formed to expose the tail terminals 20 and main portions of the barrier conductive film 25.
In the semiconductor device according to the third embodiment, even if materials of the electrode pads and the tail terminals of the semiconductor device are different, the barrier conductive film is formed between the electrode pads and the tail terminals. Therefore, in addition to the similar advantages as the first embodiment, both the reliability of the semiconductor device and the reliability of the jointing to the wiring substrate can be improved.
In this case, in the semiconductor device according to the third embodiment, the case where the electrode pads and the tail terminals are formed of different material respectively is exemplified. The materials of the electrode pads and the tail terminals are not limited to the above metal materials, and other metal materials may be employed.
Number | Date | Country | Kind |
---|---|---|---|
2002-167229 | Jun 2002 | JP | national |
Number | Name | Date | Kind |
---|---|---|---|
5172212 | Baba | Dec 1992 | A |
5293073 | Ono | Mar 1994 | A |
5422516 | Hosokawa et al. | Jun 1995 | A |
5640052 | Tsukamoto | Jun 1997 | A |
5914536 | Shizuki et al. | Jun 1999 | A |
6433426 | Ikegami | Aug 2002 | B1 |
6458622 | Keser et al. | Oct 2002 | B1 |
6465879 | Taguchi | Oct 2002 | B1 |
6545355 | Yanagida | Apr 2003 | B2 |
6555757 | Saiki et al. | Apr 2003 | B2 |
6759751 | Sinha | Jul 2004 | B2 |
Number | Date | Country |
---|---|---|
2001-57374 | Feb 2001 | JP |
Number | Date | Country | |
---|---|---|---|
20030227096 A1 | Dec 2003 | US |