Patent Application
20240096851
This application is based on and claims priority under 35 U.S.C. ยง 119 to Korean Patent Application No. 10-2022-0117244, filed on Sep. 16, 2022, in the Korean Intellectual Property Office, the disclosure of which is incorporated by reference herein in its entirety.
The inventive concept relates to a semiconductor package and a method of manufacturing the semiconductor package.
Due to the rapid development of the electronics industry and user demand, electronic equipment is becoming increasingly smaller in size, more multi-functional, and larger in capacity. Therefore, semiconductor packages including a plurality of semiconductor chips are required. For example, methods of mounting various semiconductor chips on substrates side by side, methods of stacking semiconductor chips or packages on one package substrate, methods of mounting interposers, on which a plurality of semiconductor chips are mounted, on package substrates, and the like are being used.
The inventive concept provides a semiconductor package and a method of manufacturing the semiconductor package.
According to an aspect of the inventive concept, there is provided a semiconductor package including a first redistribution structure including a first redistribution pattern and a first redistribution insulating layer, a first semiconductor chip on the first redistribution structure and including a first semiconductor substrate and a first through-electrode extending through the first semiconductor substrate, a second semiconductor chip on the first semiconductor chip and including a central portion vertically overlapping the first semiconductor chip and an outer portion horizontally offset from a sidewall of the first semiconductor chip, an inter-chip connection bump between the first semiconductor chip and the second semiconductor chip, a molding layer in contact with the first redistribution structure, the first semiconductor chip, the second semiconductor chip, and the inter-chip connection bump, a second redistribution structure on the second semiconductor chip and the molding layer and including a second redistribution pattern and a second redistribution insulating layer, a first vertical connection wire extending through the molding layer and extending from the first redistribution structure to the second redistribution structure, and a second vertical connection wire extending through the molding layer and extending from the first redistribution structure to the outer portion of the second semiconductor chip.
According to another aspect of the inventive concept, there is provided a semiconductor package including a first redistribution structure including a first redistribution pattern and a first redistribution insulating layer, a first semiconductor chip on the first redistribution structure and including a first semiconductor substrate and a first through-electrode extending through the first semiconductor substrate, a first conductive connection pillar extending between a first lower connection pad of the first semiconductor chip and a first redistribution pad of the first redistribution structure, a second semiconductor chip on the first semiconductor chip and electrically connected to the first through-electrode, wherein an outer portion of the second semiconductor chip is laterally offset from a sidewall of the first semiconductor chip, an inter-chip connection bump between the first semiconductor chip and the second semiconductor chip, a second conductive connection pillar extending between a second lower connection pad of the second semiconductor chip and the inter-chip connection bump, a molding layer in contact with the first redistribution structure, the sidewall of the first semiconductor chip, a sidewall of the second semiconductor chip, and the inter-chip connection bump, a second redistribution structure on the second semiconductor chip and the molding layer and including a second redistribution pattern and a second redistribution insulating layer, a first vertical connection conductor extending through the molding layer and extending between the first redistribution structure and the second redistribution structure, and a second vertical connection conductor extending through the molding layer and extending between the first redistribution structure and the second semiconductor chip.
According to yet another aspect of the inventive concept, there is provided a semiconductor package including a first redistribution structure including a first redistribution pattern and a first redistribution insulating layer, a first semiconductor chip on the first redistribution structure and including a first semiconductor substrate and a first through-electrode extending through the first semiconductor substrate, a first conductive connection pillar between the first semiconductor chip and the first redistribution structure and including copper, a second semiconductor chip on the first semiconductor chip and including a central portion vertically overlapping the first semiconductor chip and an outer portion horizontally offset from a sidewall of the first semiconductor chip, an inter-chip connection bump between the first semiconductor chip and the second semiconductor chip and including solder, a second conductive connection pillar between the inter-chip connection bump and the second semiconductor chip and including copper, a molding layer in contact with the first redistribution structure, the first semiconductor chip, the second semiconductor chip, the first conductive connection pillar, the second conductive connection pillar, and the inter-chip connection bump, a second redistribution structure on the second semiconductor chip and the molding layer and including a second redistribution pattern and a second redistribution insulating layer, an upper semiconductor chip on the second redistribution structure, a first vertical connection wire extending through the molding layer between a first bonding pad of the first redistribution structure and a second bonding pad of the second redistribution structure, and a second vertical connection wire extending through the molding layer between a third bonding pad of the first redistribution structure and a fourth bonding pad of the second semiconductor chip, wherein a contact area between the first vertical connection wire and the second bonding pad is greater than a contact area between the first vertical connection wire and the first bonding pad, and a contact area between the second vertical connection wire and the fourth bonding pad is greater than a contact area between the second vertical connection wire and the third bonding pad.
According to yet another aspect of the inventive concept, there is provided a method of manufacturing a semiconductor package, the method including forming, on a carrier substrate, a second redistribution structure including a second redistribution pattern, mounting, on the second redistribution structure, a second semiconductor chip including a second semiconductor substrate and a second active layer on an active surface of the second semiconductor substrate, forming a first vertical connection wire, which extends in a vertical direction from a bonding pad of the second redistribution structure, and a second vertical connection wire, which extends in the vertical direction from a bonding pad of the second semiconductor chip, by performing a wire bonding process, mounting a first semiconductor chip on the second semiconductor chip using an inter-chip connection bump, wherein the first semiconductor chip includes a first semiconductor substrate, a first active layer on an active surface of the first semiconductor substrate, and a first through-electrode extending through the first semiconductor substrate, forming a molding layer on the first semiconductor chip, the second semiconductor chip, the first vertical connection wire, and the second vertical connection wire, polishing the molding layer to expose the first vertical connection wire and the second vertical connection wire, forming, on the first semiconductor chip and the molding layer, a first redistribution structure including a first redistribution pattern, which is electrically connected to the first vertical connection wire and the second vertical connection wire, and separating the carrier substrate from the second redistribution structure.
Embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings in which:
Hereinafter, embodiments of the inventive concept will be described in detail with reference to the accompanying drawings. Like components are denoted by like reference numerals throughout the specification, and repeated descriptions thereof may be omitted in the interest of brevity.
Referring to
The first redistribution structure 110 may be a substrate on which the first semiconductor chip 120 is mounted. For example, the first redistribution structure 110 may include a first redistribution pattern 113, and a first redistribution insulating layer 111 that covers or surrounds the first redistribution pattern 113.
Hereinafter, a direction parallel to an upper surface of the first redistribution structure 110 facing the first semiconductor chip 120 is defined as a horizontal direction (for example, an X direction and/or a Y direction), a direction perpendicular to the upper surface of the first redistribution structure 110 is defined as a vertical direction (for example, a Z direction), and a horizontal width is defined as a distance in the horizontal direction (for example, the X direction and/or the Y direction).
The first redistribution insulating layer 111 may be formed of a material film including an organic compound. The first redistribution insulating layer 111 may include an insulating material including a photo imageable dielectric (PID) material. For example, the first redistribution insulating layer 111 may include a photosensitive polyimide (PSPI). The first redistribution insulating layer 111 may include a plurality of insulating layers stacked in the vertical direction (for example, the Z direction), or a single insulating layer.
The first redistribution pattern 113 may include a plurality of first redistribution conductive layers 1131 extending in the horizontal direction (for example, the X direction and/or the Y direction), and a plurality of first redistribution vias 1133 extending to at least partially pass through the first redistribution insulating layer 111. The plurality of first redistribution conductive layers 1131 may extend along at least one of respective upper and lower surfaces of the insulating layers constituting the first redistribution insulating layer 111. The plurality of first redistribution vias 1133 may electrically connect the first redistribution conductive layers 1131, which are located at different levels from each other in the vertical direction (for example, the Z direction), to each other. In some embodiments, each of the plurality of first redistribution vias 1133 may have a tapered shape having a decreasing horizontal width toward the upper surface of the first redistribution structure 110. For example, the first redistribution pattern 113 may include a metal, such as copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), indium (In), molybdenum (Mo), manganese (Mn), cobalt (Co), tin (Sn), nickel (Ni), magnesium (Mg), rhenium (Re), beryllium (Be), gallium (Ga), or ruthenium (Ru), or an alloy thereof. A seed metal layer may be arranged between the first redistribution pattern 113 and the first redistribution insulating layer 111.
The first redistribution conductive layers 1131 provided on an upper surface of the first redistribution insulating layer 111 may include a first upper redistribution pad 114, a first redistribution bonding pad 116, and a second redistribution bonding pad 117. In a cross-sectional view, each of the first upper redistribution pad 114, the first redistribution bonding pad 116, and the second redistribution bonding pad 117 may have a rectangular shape. In addition, the first redistribution conductive layers 1131 provided on a lower surface of the first redistribution insulating layer 111 may include a first lower redistribution pad 115. The semiconductor package 1000 may further include an external connection terminal 171 attached onto a lower surface of the first redistribution structure 110. The external connection terminal 171 may be attached to the first lower redistribution pad 115 of the first redistribution structure 110. The external connection terminal 171 may include, for example, a solder. The external connection terminal 171 may physically and electrically connect an external device with the semiconductor package 1000.
The first semiconductor chip 120 may be mounted on the first redistribution structure 110. In some embodiments, the first semiconductor chip 120 may be physically and electrically connected to the first redistribution pattern 113 of the first redistribution structure 110 via a first conductive connection pillar 141. An upper portion of the first conductive connection pillar 141 may be connected to a first lower connection pad 125 provided on a lower surface of the first semiconductor chip 120, and a lower portion of the first conductive connection pillar 141 may be connected to the first upper redistribution pad 114 of the first redistribution structure 110. The first conductive connection pillar 141 may have a pillar shape extending from the first lower connection pad 125 of the first semiconductor chip 120 to the first upper redistribution pad 114 of the first redistribution structure 110. For example, the first conductive connection pillar 141 may include copper (Cu).
The second semiconductor chip 130 may be stacked on the first semiconductor chip 120. The second semiconductor chip 130 may be physically and electrically connected to the first semiconductor chip 120 via an inter-chip connection bump 145. The inter-chip connection bump 145 may be arranged between a second lower connection pad 135 provided on a lower surface of the second semiconductor chip 130 and a first upper connection pad 126 provided on an upper surface of the first semiconductor chip 120 and may electrically connect the second lower connection pad 135 of the second semiconductor chip 130 with the first upper connection pad 126 of the first semiconductor chip 120. For example, the inter-chip connection bump 145 may include a solder.
In some embodiments, the semiconductor package 1000 may include a second conductive connection pillar 143 attached to the second lower connection pad 135 of the second semiconductor chip 130. The second conductive connection pillar 143 may have a pillar shape extending downwards from the second lower connection pad 135 of the second semiconductor chip 130. The second conductive connection pillar 143 may physically and electrically connect the second lower connection pad 135 of the second semiconductor chip 130 with the inter-chip connection bump 145, and the first semiconductor chip 120 and the second semiconductor chip 130 may be physically and electrically connected to each other via the second conductive connection pillar 143 and the inter-chip connection bump 145. An upper portion of the second conductive connection pillar 143 may be connected to the second lower connection pad 135 of the second semiconductor chip 130, and a lower portion of the second conductive connection pillar 143 may be connected to the inter-chip connection bump 145. The inter-chip connection bump 145 may partially cover or surround a sidewall of the second conductive connection pillar 143. The second conductive connection pillar 143 may include a material that is different from a material of the inter-chip connection bump 145. For example, the second conductive connection pillar 143 may include copper (Cu).
In some embodiments, the footprint of the second semiconductor chip 130 may be greater than the footprint of the first semiconductor chip 120. In some embodiments, a second horizontal width of the second semiconductor chip 130 may be greater than a first horizontal width of the first semiconductor chip 120. A central portion of the second semiconductor chip 130 may vertically overlap the first semiconductor chip 120, and an outer portion of the second semiconductor chip 130 may laterally protrude or be horizontally offset from a sidewall of the first semiconductor chip 120. The first semiconductor chip 120 may not be arranged between the outer portion of the second semiconductor chip 130 and the first redistribution structure 110, and the outer portion of the second semiconductor chip 130 may directly face or vertically overlap the first redistribution structure 110. A bonding pad 137 may be provided on a lower surface of the outer portion of the second semiconductor chip 130.
In some embodiments, each of the first semiconductor chip 120 and the second semiconductor chip 130 may include a logic chip and/or a memory chip. The logic chip may include a central processing unit (CPU) chip, a graphics processing unit (GPU) chip, an application processor (AP) chip, and an application specific integrated circuit (ASIC) chip. The memory chip may include a dynamic random access memory (DRAM) chip, a static random access memory (SRAM) chip, a flash memory chip, an electrically erasable and programmable read-only memory (EEPROM) chip, a phase-change random access memory (PRAM) chip, a magnetic random access memory (MRAM) chip, or a resistive random access memory (RRAM) chip. The first semiconductor chip 120 and the second semiconductor chip 130 may include the same types of semiconductor chips or different types of semiconductor chips, respectively. In some embodiments, each of the first semiconductor chip 120 and the second semiconductor chip 130 may include a logic chip. In some embodiments, one of the first semiconductor chip 120 and the second semiconductor chip 130 may include a logic chip, and the other may include a memory chip. In some embodiments, the first semiconductor chip 120 and the second semiconductor chip 130 may respectively include chiplets configured to perform different functions from each other and may be respectively referred to as a first chiplet and a second chiplet. The first chiplet and the second chiplet may be electrically connected to each other to operate as one logic chip.
The molding layer 151 may be arranged on the first redistribution structure 110 and cover or surround at least a portion of the first semiconductor chip 120 and at least a portion of the second semiconductor chip 130. The molding layer 151 may extend along a sidewall, an upper surface, and a lower surface of the first semiconductor chip 120 and at least partially cover the sidewall, the upper surface, and the lower surface of the first semiconductor chip 120. The molding layer 151 may extend along a sidewall and a lower surface of the second semiconductor chip 130 and at least partially cover the sidewall and the lower surface of the second semiconductor chip 130. The molding layer 151 may not cover an upper surface of the second semiconductor chip 130. In some embodiments, an upper surface of the molding layer 151 and the upper surface of the second semiconductor chip 130 may be coplanar with each other. The molding layer 151 may be in or fill a gap between the first semiconductor chip 120 and the first redistribution structure 110 and surround a sidewall of the first conductive connection pillar 141. The molding layer 151 may be in or fill a gap between the first semiconductor chip 120 and the second semiconductor chip 130 and surround a sidewall of the inter-chip connection bump 145 and a sidewall of the second conductive connection pillar 143. The molding layer 151 may include an insulating polymer or an epoxy resin. For example, the molding layer 151 may include an epoxy mold compound (EMC).
The second redistribution structure 160 may be arranged on the second semiconductor chip 130 and the molding layer 151. The second redistribution structure 160 may directly contact the upper surface of the second semiconductor chip 130 and the upper surface of the molding layer 151. The second redistribution structure 160 may include a second redistribution pattern 163 and a second redistribution insulating layer 161 that covers or surrounds the second redistribution pattern 163.
The second redistribution insulating layer 161 may be formed of a material film including an organic compound. The second redistribution insulating layer 161 may include a PID or a PSPI. The material of the second redistribution insulating layer 161 may be the same as the material of the first redistribution insulating layer 111. The second redistribution insulating layer 161 may include a plurality of insulating layers stacked in the vertical direction (for example, the Z direction).
The second redistribution pattern 163 may include a plurality of second redistribution conductive layers 1631 extending in the horizontal direction (for example, the X direction and/or the Y direction), and a plurality of second redistribution vias 1633 extending to at least partially pass through the second redistribution insulating layer 161. The plurality of second redistribution conductive layers 1631 may extend along at least one of respective upper and lower surfaces of the insulating layers constituting the second redistribution insulating layer 161. The plurality of second redistribution vias 1633 may electrically connect the second redistribution conductive layers 1631, which are located at different levels from each other in the vertical direction (for example, the Z direction), to each other. In some embodiments, each of the plurality of second redistribution vias 1633 may have a tapered shape having a decreasing horizontal width toward the upper surface of the second redistribution structure 160 (or away from the lower surface of the second redistribution structure 160). The material of the second redistribution pattern 163 may be the same as the material of the first redistribution pattern 113. A seed metal layer may be arranged between the second redistribution pattern 163 and the second redistribution insulating layer 161. The plurality of second redistribution conductive layers 1631 may include a second upper redistribution pad 164 provided on an upper surface of the second redistribution insulating layer 161, and a third redistribution bonding pad 166 provided on a lower surface of the second redistribution insulating layer 161. An electronic component (for example, a semiconductor package, a semiconductor chip, a passive component, or the like) may be mounted on the second redistribution structure 160. In a cross-sectional view, the second upper redistribution pad 164 may have a rectangular shape. An upper surface of the second upper redistribution pad 164 may be substantially coplanar with the upper surface of the second redistribution insulating layer 161. A connection terminal for connecting the second redistribution structure 160 to the electronic component may be attached onto the second upper redistribution pad 164.
In some embodiments, the sidewall of the first redistribution structure 110, the sidewall of the molding layer 151, and the sidewall of the second redistribution structure 160 may be aligned with each other in the vertical direction (for example, the Z direction) and may be coplanar with each other. In some embodiments, the first redistribution structure 110, the molding layer 151, and the second redistribution structure 160 may respectively have footprints that overlap each other or are equal to each other. The footprint of the first redistribution structure 110 may be greater than the footprint of the footprint of the first semiconductor chip 120 and the footprint of the second semiconductor chip 130. In some embodiments, the first redistribution structure 110, the molding layer 151, and the second redistribution structure 160 may respectively have third horizontal widths that are equal to each other. The third horizontal width of the first redistribution structure 110 may be greater than the first horizontal width of the first semiconductor chip 120 and the second horizontal width of the second semiconductor chip 130.
The first vertical connection conductor 153 may vertically pass through the molding layer 151 and extend from the first redistribution structure 110 to the second redistribution structure 160. A lower end portion of the first vertical connection conductor 153 may be directly connected to the first redistribution bonding pad 116 of the first redistribution structure 110, and an upper end portion of the first vertical connection conductor 153 may be directly connected to the third redistribution bonding pad 166 of the second redistribution structure 160. For example, the first vertical connection conductor 153 may include copper (Cu), silver (Ag), gold (Au), and/or aluminum (Al). In some embodiments, the first vertical connection conductor 153 may include a vertical connection wire, which is formed by a wire bonding process. In some embodiments, the first vertical connection conductor 153 may include a conductive post, which is formed by a plating process.
The second vertical connection conductor 155 may vertically pass through the molding layer 151 and extend from the first redistribution structure 110 to the second semiconductor chip 130. A lower end portion of the second vertical connection conductor 155 may be directly connected to the second redistribution bonding pad 117 of the first redistribution structure 110, and an upper end portion of the second vertical connection conductor 155 may be directly connected to the bonding pad 137 of the second semiconductor chip 130. For example, the second vertical connection conductor 155 may include copper (Cu), silver (Ag), gold (Au), and/or aluminum (Al). In some embodiments, the second vertical connection conductor 155 may include a vertical connection wire, which is formed by a wire bonding process. In some embodiments, the second vertical connection conductor 155 may include a conductive post, which is formed by a plating process.
Referring to
The first semiconductor substrate 121 may include a first active surface 1211 and a first inactive surface 1213, which are opposite to each other. The first active surface 1211 of the first semiconductor substrate 121 may correspond to a lower surface of the first semiconductor substrate 121, which faces the first redistribution structure 110, and the first inactive surface 1213 of the first semiconductor substrate 121 may correspond to an upper surface of the first semiconductor substrate 121, which faces the second semiconductor chip 130.
The first semiconductor substrate 121 may be formed of a semiconductor wafer. The first semiconductor substrate 121 may include, for example, silicon (Si). Alternatively, the first semiconductor substrate 121 may include a semiconductor element, such as germanium (Ge), or a compound semiconductor, such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), and indium phosphide (InP). The first semiconductor substrate 121 may include a conductive region, for example, an impurity-doped well or an impurity-doped structure. In addition, the first semiconductor substrate 121 may have various device isolation structures, such as a shallow trench isolation (STI) structure.
The first active layer 122 may be formed on the first active surface 1211 of the first semiconductor substrate 121. The first active layer 122 may include a circuit pattern, a discrete device such as a transistor, and the like. The first active layer 122 may include a first front-end-of-line (FEOL) structure 124 arranged on the first active surface 1211 of the first semiconductor substrate 121, and a first interconnect structure 123 arranged on the first FEOL structure 124.
The first FEOL structure 124 may include a first insulating layer 1241 and various first discrete devices 1242. The first insulating layer 1241 may be arranged on the first active surface 1211 of the first semiconductor substrate 121. The first insulating layer 1241 may include a plurality of interlayer dielectrics, which are sequentially stacked on the first active surface 1211 of the first semiconductor substrate 121. The first discrete devices 1242 may be formed in the first semiconductor substrate 121 and/or on the first active surface 1211 of the first semiconductor substrate 121. The first discrete devices 1242 may include, for example, a transistor. The first discrete devices 1242 may include microelectronic devices, for example, a metal-oxide-semiconductor field effect transistor (MOSFET), a system large-scale integration (LSI), an image sensor such as a CMOS imaging sensor (CIS), a micro-electro-mechanical system (MEMS), an active element, a passive element, and the like. The first discrete devices 1242 may be electrically connected to the conductive region of the first semiconductor substrate 121. Each of the first discrete devices 1242 may be electrically isolated from other first discrete devices 1242 adjacent thereto by the first insulating layer 1241.
The first interconnect structure 123 may include a back-end-of-line (BEOL) structure, which is formed on the first FEOL structure 124. The footprint of the first interconnect structure 123 may be equal to the footprint of the first FEOL structure 124 and the footprint of the first semiconductor substrate 121. The first interconnect structure 123 may include a first interconnect insulating layer 1231, and a first interconnect pattern 1233 covered or surrounded by the first interconnect insulating layer 1231. The first interconnect pattern 1233 may be electrically connected to the first discrete devices 1242 and the conductive region of the first semiconductor substrate 121. The first interconnect pattern 1233 may include a plurality of first conductive layers 1233L extending in the horizontal direction (for example, the X direction and/or the Y direction), and a plurality of first vias 1233V extending to at least partially pass through the first interconnect insulating layer 1231. The plurality of first conductive layers 1233L may include the first lower connection pad 125 provided on a lower surface of the first interconnect insulating layer 1231. The plurality of first vias 1233V may electrically connect the first conductive layers 1233L, which are located at different levels from each other in the vertical direction (for example, the Z direction), to each other. In some embodiments, each of the plurality of first vias 1233V may have a tapered shape having a decreasing horizontal width toward the first active surface 1211 of the first semiconductor substrate 121. For example, the first interconnect pattern 1233 may include a metal, such as copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), indium (In), molybdenum (Mo), manganese (Mn), cobalt (Co), tin (Sn), nickel (Ni), magnesium (Mg), rhenium (Re), beryllium (Be), gallium (Ga), or ruthenium (Ru), or an alloy thereof.
The first backside interconnect structure 128 may be arranged on the first inactive surface 1213 of the first semiconductor substrate 121. The footprint of the first backside interconnect structure 128 may be equal to the footprint of the first semiconductor substrate 121. The first backside interconnect structure 128 may include a first backside interconnect insulating layer 1281, and a first backside interconnect pattern 1283 covered or surrounded by the first backside interconnect insulating layer 1281. The first backside interconnect pattern 1283 may include a plurality of first backside conductive layers 1283L extending in the horizontal direction (for example, the X direction and/or the Y direction), and a plurality of first backside vias 1283V extending to at least partially pass through the first backside interconnect insulating layer 1281. The plurality of first backside conductive layers 1283L may include the first upper connection pad 126 provided on an upper surface of the first backside interconnect insulating layer 1281. The plurality of first backside vias 1283V may electrically connect the first backside conductive layers 1283L, which are located at different levels from each other in the vertical direction (for example, the Z direction), to each other. In some embodiments, each of the plurality of first backside vias 1283V may have a tapered shape having a decreasing horizontal width toward the first inactive surface 1213 of the first semiconductor substrate 121. For example, the material of the first backside interconnect pattern 1283 may be substantially identical or similar to the material of the first interconnect pattern 1233.
The first through-electrode 129 may vertically pass through the first semiconductor substrate 121. The first through-electrode 129 may electrically connect the first interconnect pattern 1233 of the first interconnect structure 123 with the first backside interconnect pattern 1283 of the first backside interconnect structure 128. The first through-electrode 129 may be provided to the inside of a through-hole of the first semiconductor substrate 121, and a via insulating layer 1291 may be arranged between the first through-electrode 129 and the first semiconductor substrate 121. For example, the first through-electrode 129 may include a conductive plug having a pillar shape, and a conductive barrier layer surrounding a sidewall of the conductive plug. The conductive plug may include, for example, at least one material selected from among copper (Cu), nickel (Ni), gold (Au), silver (Ag), tungsten (W), titanium (Ti), tantalum (Ta), indium (In), molybdenum (Mo), manganese (Mn), cobalt (Co), tin (Sn), magnesium (Mg), rhenium (Re), beryllium (Be), gallium (Ga), and ruthenium (Ru). The conductive barrier layer may include at least one material selected from among titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), ruthenium (Ru), and cobalt (Co).
The second semiconductor chip 130 may include a second semiconductor substrate 131 and a second active layer 132.
The second semiconductor substrate 131 may include a second active surface 1311 and a second inactive surface 1313, which are opposite to each other. The second active surface 1311 of the second semiconductor substrate 131 may correspond to a lower surface of the second semiconductor substrate 131, which faces the first semiconductor chip 120, and the second inactive surface 1313 of the second semiconductor substrate 131 may correspond to an upper surface of the second semiconductor substrate 131, which faces the second redistribution structure 160. The material of the second semiconductor substrate 131 may be substantially identical or similar to the material of the first semiconductor substrate 121. The second semiconductor substrate 131 may include a conductive region, for example, an impurity-doped well or an impurity-doped structure. In addition, the second semiconductor substrate 131 may have various device isolation structures, such as an STI structure.
The second active layer 132 may be formed on the second active surface 1311 of the second semiconductor substrate 131. The second active layer 132 may include a circuit pattern, a discrete device such as a transistor, and the like. The second active layer 132 may include a second FEOL structure 134 arranged on the second active surface 1311 of the second semiconductor substrate 131, and a second interconnect structure 133 arranged on the second FEOL structure 134.
The second FEOL structure 134 may include a second insulating layer 1343 and various second discrete devices 1341. The second insulating layer 1343 may be arranged on the second active surface 1311 of the second semiconductor substrate 131. The second insulating layer 1343 may include a plurality of interlayer dielectrics that are sequentially stacked on the second active surface 1311 of the second semiconductor substrate 131. The second discrete devices 1341 may be formed in the second semiconductor substrate 131 and/or on the second active surface 1311 of the second semiconductor substrate 131. The second discrete devices 1341 may include, for example, a transistor. The second discrete devices 1341 may include microelectronic devices, for example, a MOSFET, a system LSI, an image sensor such as a CIS, a MEMS, an active element, a passive element, and the like. The second discrete devices 1341 may be electrically connected to the conductive region of the second semiconductor substrate 131. Each of the second discrete devices 1341 may be electrically isolated from other second discrete devices 1341 adjacent thereto by the second insulating layer 1343.
The second interconnect structure 133 may include a BEOL structure, which is formed on the second FEOL structure 134. The footprint of the second interconnect structure 133 may be equal to the footprint of the second FEOL structure 134 and the footprint of the second semiconductor substrate 131. The second interconnect structure 133 may include a second interconnect insulating layer 1331, and a second interconnect pattern 1333 covered or surrounded by the second interconnect insulating layer 1331. The second interconnect pattern 1333 may be electrically connected to the second discrete devices 1341 and the conductive region of the second semiconductor substrate 131. The second interconnect pattern 1333 may include a plurality of second conductive layers 1333L extending in the horizontal direction (for example, the X direction and/or the Y direction), and a plurality of second vias 1333V extending to at least partially pass through the second interconnect insulating layer 1331. The plurality of second conductive layers 1333L may include the second lower connection pad 135 provided on a lower surface of the second interconnect insulating layer 1331. The plurality of second vias 1333V may electrically connect the second conductive layers 1333L, which are located at different levels from each other in the vertical direction (for example, the Z direction), to each other. In some embodiments, each of the plurality of second vias 1333V may have a tapered shape having a decreasing horizontal width toward the second active surface 1311 of the second semiconductor substrate 131. The material of the second interconnect pattern 1333 may be substantially identical or similar to the material of the first interconnect pattern 1233.
The first semiconductor chip 120 may be configured to transmit electrical signals to and receive electrical signals from an external device via the first redistribution structure 110 and the first conductive connection pillar 141. In some embodiments, an input-output data signal between the first semiconductor chip 120 and the external device may be transferred via the first redistribution pattern 113 and the first conductive connection pillar 141. In some embodiments, a power signal (for example, a power supply signal and/or a ground signal) between the first semiconductor chip 120 and the external device may be transferred via the first redistribution pattern 113 and the first conductive connection pillar 141.
The second semiconductor chip 130 may be configured to transmit electrical signals to and receive electrical signals from an external device via the first redistribution structure 110 and the second vertical connection conductor 155. In some embodiments, an input-output data signal between the second semiconductor chip 130 and the external device may be transferred via the first redistribution pattern 113 and the second vertical connection conductor 155. In some embodiments, a power signal (for example, a power supply signal and/or a ground signal) between the second semiconductor chip 130 and the external device may be transferred via the second redistribution pattern 163 and the second vertical connection conductor 155. In addition, the second semiconductor chip 130 may be electrically connected with the first semiconductor chip 120 via the second conductive connection pillar 143, the inter-chip connection bump 145, and the first through-electrode 129. That is, an electrical signal between the first semiconductor chip 120 and the second semiconductor chip 130 may be transmitted via a signal transfer path that includes the second conductive connection pillar 143, the inter-chip connection bump 145, and the first through-electrode 129.
Referring to
When the first vertical connection conductor 153 is formed by a wire bonding process, a bonding portion 1531, which is bonded to the third redistribution bonding pad 166, is formed first by using a capillary for supplying a conductive wire, and then, a wire portion 1533, which extends in the vertical direction, is formed by moving the capillary. The bonding portion 1531 at an end of the first vertical connection conductor 153 may have a profile of a ball shape or a curve shape such as a hemispherical shape. For example, in a cross-sectional view, the bonding portion 1531 at the end of the first vertical connection conductor 153 may have a laterally convex shape. The wire portion 1533 may extend with a uniform width and have a profile of a straight-line shape. Therefore, an upper end portion of the first vertical connection conductor 153, which is bonded to the third redistribution bonding pad 166, may have a shape having a decreasing horizontal width away from the third redistribution bonding pad 166. In addition, other portions of the first vertical connection conductor 153 except for the upper end portion thereof may have a line shape having a substantially constant width. The contact area between the first vertical connection conductor 153 and the third redistribution bonding pad 166 may be greater than the contact area between the first vertical connection conductor 153 and the first redistribution bonding pad 116.
In general, when a vertical connection conductor is formed by a plating process, a seed metal layer and/or an adhesive metal layer (for example, a Ti layer) is arranged between the vertical connection conductor and a pad. However, when the first vertical connection conductor 153 includes a vertical connection wire formed by a wire bonding process, any other metal layer may not be arranged between the first vertical connection conductor 153 and the third redistribution bonding pad 166, and the first vertical connection conductor 153 may be directly connected to the third redistribution bonding pad 166.
Referring to
When the second vertical connection conductor 155 is formed by a wire bonding process, a bonding portion 1551, which is bonded to the bonding pad 137 of the second semiconductor chip 130, is formed first by using a capillary for supplying a conductive wire, and then, a wire portion 1553, which extends in the vertical direction, is formed by moving the capillary. The bonding portion 1551 at an end of the second vertical connection conductor 155 may have a profile of a ball shape or a curve shape such as a hemispherical shape. For example, in a cross-sectional view, the bonding portion 1551 at the end of the second vertical connection conductor 155 may have a laterally convex shape. The wire portion 1553 may extend with a uniform width and have a profile of a straight-line shape. Therefore, an upper end portion of the second vertical connection conductor 155, which is bonded to the bonding pad 137 of the second semiconductor chip 130, may have a shape having a decreasing horizontal width away from the bonding pad 137 of the second semiconductor chip 130. In addition, other portions of the second vertical connection conductor 155 except for the upper end portion thereof may have a line shape having a substantially constant width. The contact area between the second vertical connection conductor 155 and the bonding pad 137 of the second semiconductor chip 130 may be greater than the contact area between the second vertical connection conductor 155 and the second redistribution bonding pad 117. When the second vertical connection conductor 155 includes a vertical connection wire formed by a wire bonding process, any other metal layer may not be arranged between the second vertical connection conductor 155 and the bonding pad 137 of the second semiconductor chip 130, and the second vertical connection conductor 155 may be directly connected to the bonding pad 137 of the second semiconductor chip 130.
Referring to
In some embodiments, the upper semiconductor device 200 may include an upper substrate 210, one or more upper semiconductor chips 220 mounted on the upper substrate 210, an upper molding layer 240 arranged on the upper substrate 210 to cover the upper semiconductor chips 220, and a conductive connection member 230 electrically connecting the upper semiconductor chips 220 with the upper substrate 210. The upper substrate 210 may include, for example, a printed circuit board. The upper semiconductor chips 220 may each include a memory chip and/or a logic chip. In some embodiments, each of the upper semiconductor chips 220 may include a memory chip, and each of the first and second semiconductor chips 120 and 130 may include a logic chip.
In some embodiments, the upper semiconductor chips 220 may be directly mounted on the second redistribution structure 160.
The first semiconductor chip 120 may be electrically connected with the upper semiconductor chips 220 via an electrical connection path, which includes the first conductive connection pillar 141, the first redistribution pattern 113, the first vertical connection conductor 153, the second redistribution pattern 163, and the upper connection terminal 173. The second semiconductor chip 130 may be electrically connected with the upper semiconductor chips 220 via an electrical connection path, which includes the second vertical connection conductor 155, the first redistribution pattern 113, the first vertical connection conductor 153, the second redistribution pattern 163, and the upper connection terminal 173.
The semiconductor package 1002 may further include a board substrate 300 arranged under the first redistribution structure 110. The board substrate 300 may include, for example, a printed circuit board. The board substrate 300 may include a core insulating layer 310, and a substrate pad 320 arranged on the core insulating layer 310. An external connection terminal 171 may be arranged between the substrate pad 320 of the board substrate 300 and the first lower redistribution pad 115 of the first redistribution structure 110 and may electrically and physically connect the substrate pad 320 of the board substrate 300 with the first lower redistribution pad 115 of the first redistribution structure 110.
Referring to
The second semiconductor chip 130 may be electrically connected to the second redistribution structure 160 via a connection bump 149. More specifically, the second redistribution pattern 163 of the second redistribution structure 160 may include the second lower redistribution pad 165 provided on the lower surface of the second redistribution insulating layer 161, and the connection bump 149 may be arranged between the second upper connection pad 136 of the second semiconductor chip 130 and the second lower redistribution pad 165 of the second redistribution structure 160. The connection bump 149 may electrically and physically connect the second upper connection pad 136 of the second semiconductor chip 130 with the second lower redistribution pad 165 of the second redistribution structure 160. The molding layer 151 may be in or fill a gap between the second semiconductor chip 130 and the second redistribution structure 160 and surround a sidewall of the connection bump 149.
The second semiconductor chip 130 may include the second active layer 132, a second backside interconnect structure 138, and a second through-electrode 139.
The second active layer 132 may include the second FEOL structure 134 on the second active surface 1311 of the second semiconductor substrate 131, and the second interconnect structure 133 on the second FEOL structure 134. The second interconnect pattern 1333 of the second interconnect structure 133 may include the second upper connection pad 136 arranged on the second interconnect insulating layer 1331.
The second backside interconnect structure 138 may be arranged on the second inactive surface 1313 of the second semiconductor substrate 131. The footprint of the second backside interconnect structure 138 may be equal to the footprint of the second semiconductor substrate 131. The second backside interconnect structure 138 may include a second backside interconnect insulating layer 1381, and a second backside interconnect pattern 1383 covered or surrounded by the second backside interconnect insulating layer 1381. The second backside interconnect pattern 1383 may include a plurality of second backside conductive layers 1383L extending in the horizontal direction (for example, the X direction and/or the Y direction), and a plurality of second backside vias 1383V extending to at least partially pass through the second backside interconnect insulating layer 1381. The plurality of second backside conductive layers 1383L may include a second lower connection pad 135 provided on a lower surface of the second backside interconnect insulating layer 1381. The plurality of second backside vias 1383V may electrically connect the second backside conductive layers 1383L, which are located at different levels from each other in the vertical direction (for example, the Z direction), to each other. In some embodiments, each of the plurality of second backside vias 1383V may have a tapered shape having a decreasing horizontal width toward the second inactive surface 1313 of the second semiconductor substrate 131. For example, the material of the second backside interconnect pattern 1383 may be substantially identical or similar to the material of the second interconnect pattern 1333.
The second through-electrode 139 may vertically pass through the second semiconductor substrate 131. The second through-electrode 139 may electrically connect the second interconnect pattern 1333 of the second interconnect structure 133 with the second backside interconnect pattern 1383 of the second backside interconnect structure 138. The second through-electrode 139 may be provided to the inside of a through-hole of the second semiconductor substrate 131, and a via insulating layer 1391 may be arranged between the second through-electrode 139 and the second semiconductor substrate 131. For example, the second through-electrode 139 may include a conductive plug having a pillar shape, and a conductive barrier layer surrounding a sidewall of the conductive plug. The material of the second through-electrode 139 may be substantially identical or similar to the material of the first through-electrode 129.
In some embodiments, the first semiconductor chip 120 may be electrically connected with the second semiconductor chip 130 via an electrical connection path, which includes the first through-electrode 129, the inter-chip connection bump 145, the second conductive connection pillar 143, and the second through-electrode 139.
In some embodiments, the upper semiconductor device 200 (see
Referring to
Next, the second redistribution structure 160 is formed on the carrier substrate CS, the second redistribution structure 160 including the second redistribution pattern 163 and the second redistribution insulating layer 161. For example, sub-insulating layers (for example, first to third sub-insulating layers) constituting the second redistribution insulating layer 161 may each be formed by a lamination process, and the second redistribution pattern 163 may be formed by a plating process. For example, forming the second redistribution structure 160 may include forming the second upper redistribution pad 164 on an upper surface of the adhesive material layer AM, forming the first sub-insulating layer to cover the second upper redistribution pad 164, forming the second redistribution via 1633 to fill a via hole of the first sub-insulating layer simultaneously with forming the second redistribution conductive layer 1631 to extend along an upper surface of the first sub-insulating layer, forming the second sub-insulating layer to cover the first sub-insulating layer, forming the second redistribution via 1633 to fill a via hole of the second sub-insulating layer simultaneously with forming the second redistribution conductive layer 1631 to extend along an upper surface of the second sub-insulating layer, forming the third sub-insulating layer to cover the second sub-insulating layer, and forming the second redistribution via 1633 to fill a via hole of the third sub-insulating layer simultaneously with forming the second redistribution conductive layer 1631 to extend along an upper surface of the third sub-insulating layer. The second redistribution conductive layer 1631 arranged on the upper surface of the third sub-insulating layer may include the third redistribution bonding pad 166.
Referring to
Referring to
In some embodiments, the first vertical connection conductor 153 and the second vertical connection conductor 155 may each be formed by a wire bonding process. To form the first vertical connection conductor 153, a bonding portion, which is directly coupled to the third redistribution bonding pad 166 of the second redistribution structure 160, may be formed first, and a wire portion, which extends in the vertical direction from the bonding portion, may be formed while moving a capillary for supplying a conductive wire, upwards. To form the second vertical connection conductor 155, a bonding portion, which is directly coupled to the bonding pad 137 of the second semiconductor chip 130, may be formed first, and a wire portion, which extends in the vertical direction from the bonding portion, may be formed while moving a capillary for supplying a conductive wire, upwards.
Referring to
Although
Referring to
Referring to
Referring to
After the first redistribution structure 110 is formed, the external connection terminal 171 is formed on the first lower redistribution pad 115 of the first redistribution structure 110. The external connection terminal 171 may be formed by, for example, a reflow process using a solder ball.
Referring to
After the carrier substrate CS is separated from the second redistribution structure 160, a sawing process for cutting a panel-shaped structure, which has a size corresponding to the carrier substrate CS, along a cutting line CL may be performed. Through the sawing process, the panel-shaped structure may be separated into individual-unit packages PS.
Next, referring together to
In general, when a vertical connection structure is formed by using an electrolytic plating process, to cause current to uniformly flow on the whole, in performing the electrolytic plating process, an intermediate structure on a carrier substrate is required to have a flat upper surface. In general, when vertical connection conductors having different heights from each other (that is, a long vertical connection conductor and a short vertical connection conductor) are formed by electrolytic plating processes, forming a lower portion of the long vertical connection conductor by a first electrolytic plating process, performing first molding for forming a first molding film to cover the lower portion of the long vertical connection conductor, planarizing the first molding film, forming both an upper portion of the long vertical connection conductor and the short vertical connection conductor by a second electrolytic plating process, forming a second molding film to cover the long vertical connection conductor and the short vertical connection conductor, and planarizing the second molding film are required.
However, according to some embodiments, by forming the first and second vertical connection conductors 153 and 155 having different lengths from each other through wire bonding processes, the molding layer 151, which covers the first and second semiconductor chips 120 and 130 and the first and second vertical connection conductors 153 and 155, may be formed by one molding process. Therefore, a manufacturing process of a semiconductor package may be simplified, and the manufacturing cost thereof may be reduced.
While the inventive concept has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the scope of the following claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10-2022-0117244 | Sep 2022 | KR | national |
