Patent Application
20250029882
This application claims priority under 35 U.S.C. § 119 to Chinese Patent Application No. 202310875558.3, filed on Jul. 17, 2023, in the State Intellectual Property Office of the P.R.C., the disclosure of which is incorporated herein in its entirety by reference.
The present disclosure relates to semiconductor packages and/or methods of manufacturing the same, and more particularly, relates to semiconductor packages having an electromagnetic shielding function and/or methods of manufacturing the same.
In highly integrated semiconductor packages, there may be relatively large electromagnetic signal interference between devices. A conventional solution is to provide shielding cases (or covers) outside the devices, but this will lead to an increase in volume and cost of the semiconductor packages, and it is contrary to the trend of miniaturization of the semiconductor packages. Therefore, this method is greatly limited in practical use.
The above information disclosed in this Background section is only for enhancement of understanding of the background of the inventive concepts, and therefore the above information may contain information that does not form prior art already known in the country to those skilled in the art.
Some example embodiments provide semiconductor packages having an improved electromagnetic shielding effect and/or methods of manufacturing the same.
Some example embodiments provide semiconductor packages having improved reliability and/or methods of manufacturing the same.
Some example embodiments provide a semiconductor package, which may be manufactured by a simplified manufacturing process, and/or methods of manufacturing the same.
A semiconductor package according to an example embodiment may include a substrate including a first surface and a second surface opposite to the first surface, the substrate having a groove recessed from the first surface, a chip within the groove and including an active surface facing a bottom surface of the groove, an inactive surface opposite to the active surface, and a side surface connecting the active surface with the inactive surface, a plurality of chip pads on the active surface of the chip, and a shielding layer including a first sub-shielding layer, a second sub-shielding layer, and a third sub-shielding layer, the first sub-shielding layer between the bottom surface of the groove and the active surface of the chip, the third sub-shielding layer on the inactive surface of the chip, and the second sub-shielding layer between the side surface of the chip and a side surface of the groove and connecting the first sub-shielding layer with the third sub-shielding layer, wherein the first sub-shielding layer has a plurality of openings corresponding to the plurality of chip pads, respectively.
In an example embodiment, the substrate may include a plurality of through holes corresponding to the plurality of openings, respectively, and the semiconductor package may further include a plurality of conductive connectors within the plurality of through holes, respectively.
In an example embodiment, the semiconductor package may further include conductive bumps between the chip pads and the conductive connectors, and the chip pads may be electrically connected to the conductive connectors through the conductive bumps.
In an example embodiment, the conductive bumps and the conductive connectors may not overlap the first sub-shielding layer in a plan view.
In an example embodiment, at least one of the conductive bumps and the conductive connectors may have a same shape as the openings of the first sub-shielding layer in a plan view.
In an example embodiment, each of the conductive bumps may include a lower conductive bump and an upper conductive bump overlapping each other, the lower conductive bump may contact a corresponding one of the conductive connectors, and the upper conductive bump may contact a corresponding one of the chip pads.
In an example embodiment, the semiconductor package may further include a protective layer between the active surface of the chip and the first sub-shielding layer and between the side surface of the chip and the second sub-shielding layer.
In an example embodiment, the semiconductor package may further include a redistribution layer on the second surface of the substrate and electrically connected to the conductive connectors.
In an example embodiment, the semiconductor package may further include a solder resist layer on the second surface of the substrate and partially covering the redistribution layer, and the solder resist layer may have an opening exposing a portion of the redistribution layer.
In an example embodiment, the semiconductor package may further include a solder ball on the solder resist layer and electrically connected to the redistribution layer through the opening of the solder resist layer.
A method of manufacturing a semiconductor package according to an example embodiment may include preparing a substrate including a first surface and a second surface opposite to the first surface, forming a groove recessed from the first surface in the substrate, forming a first preliminary sub-shielding layer and a second sub-shielding layer covering a bottom surface and a side surface of the groove, respectively, the first preliminary sub-shielding layer and the second sub-shielding layer being connected to each other, forming a plurality of openings for exposing the bottom surface of the groove in the first preliminary sub-shielding layer to form a first sub-shielding layer, placing a chip including an active surface, an inactive surface opposite to the active surface, and a side surface connecting the active surface with the inactive surface, in the groove such that the active surface of the chip faces the bottom surface of the groove, and a plurality of chip pads disposed on the active surface of the chip correspond to the plurality of openings, respectively, and forming a third sub-shielding layer connected to the second sub-shielding layer on the inactive surface of the chip.
In an example embodiment, the method may further include forming through holes penetrating the substrate in correspondence with the openings before the placing of the chip, filling the through holes with a conductive material to form conductive connectors, and forming lower conductive bumps within the groove and on the conductive connectors.
In an example embodiment, the chip may further include upper conductive bumps on the chip pads. The placing may include coupling the upper conductive bumps with corresponding ones of the lower conductive bumps, respectively, to form conductive bumps. Both the conductive bumps and the conductive connectors may not overlap the first sub-shielding layer in a plan view.
In an example embodiment, the chip may further include upper conductive bumps on the chip pads. The method may further include forming a preliminary protective layer between the upper conductive bumps and on the side surface of the chip before the placing of the chip. The placing may include coupling the upper conductive bumps with the lower conductive bumps to form conductive bumps, and disposing the preliminary protective layer between the active surface of the chip and the first sub-shielding layer and between the side surface of the chip and the second sub-shielding layer to form a protective layer. The conductive bumps and the conductive connectors may not overlap the first sub-shielding layer in a plan view.
In an example embodiment, the chip may further include upper conductive bumps on the chip pads. The placing may include coupling the upper conductive bumps with the lower conductive bumps to form conductive bumps. The method may further include filling the groove with a protective material to form a protective layer between the active surface of the chip and the first sub-shielding layer and between the side surface of the chip and the second sub-shielding layer. The conductive bumps and the conductive connectors may not overlap the first sub-shielding layer in a plan view.
In an example embodiment, the method may further include providing a redistribution layer electrically connected to the conductive connectors on the second surface of the substrate.
In an example embodiment, the method may further include providing a solder resist layer partially covering the redistribution layer on the second surface of the substrate, and the solder resist layer may have an opening exposing a portion of the redistribution layer.
In an example embodiment, the method may further include providing a solder ball on the solder resist layer, and the solder ball may be electrically connected to the redistribution layer through the opening of the solder resist layer.
According to some example embodiment of the present disclosure, the semiconductor package may have an improved electromagnetic shielding effect. Also, the semiconductor package may have improved reliability. Also, the semiconductor package may be manufactured by a simplified manufacturing process.
The above and other aspects, features and advantages of the present disclosure will be apparent by describing in detail some example embodiments of the present disclosure hereinafter in combination with the accompanying drawings. In the drawings, like reference numerals will always denote like elements. In the drawings:
Hereinafter, various example embodiments of the present disclosure will be described more fully with reference to the drawings. The present disclosure, however, may be embodied in various different forms, and should not be construed as being limited to the example embodiments set forth herein. Rather, these example embodiments are provided so that the present disclosure will be thorough and complete, and these example embodiments will fully convey the scope of the present disclosure to those skilled in the art. In the drawings, the sizes of layers and regions may be exaggerated for clarity.
Spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper,” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or in operation, in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as “below” or “beneath” other elements would then be oriented “above” the other elements. Thus, the example terms “below” can encompass both an orientation of “above” and “below”. The device may be otherwise oriented (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should be interpreted accordingly.
While the term “same,” “equal” or “identical” is used in description of example embodiments, it should be understood that some imprecisions may exist. Thus, when one element is referred to as being the same as another element, it should be understood that an element or a value is the same as another element within a desired manufacturing or operational tolerance range (e.g., ±10%).
When the terms “about” or “substantially” are used in this specification in connection with a numerical value, it is intended that the associated numerical value includes a manufacturing or operational tolerance (e.g., ±10%) around the stated numerical value. Moreover, when the words “about” and “substantially” are used in connection with geometric shapes, it is intended that precision of the geometric shape is not required but that latitude for the shape is within the scope of the disclosure. Further, regardless of whether numerical values or shapes are modified as “about” or “substantially,” it will be understood that these values and shapes should be construed as including a manufacturing or operational tolerance (e.g., ±10%) around the stated numerical values or shapes.
Referring to
The substrate 110 may be any substrate commonly used in the art for manufacturing a semiconductor package. In an example embodiment, the substrate 110 may be formed of an insulating material such as quartz, glass, silicon nitride, silicon oxynitride, and organic resin. In an example embodiment, the substrate 110 may be formed of a semiconductor material. For example, the substrate 110 may be a silicon substrate or may include other materials such as silicon germanium, silicon germanium on insulator (SGOI), indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. In an example embodiment, the substrate 110 may be formed of a conductive material. When the substrate 110 is formed of a conductive material or a semiconductor material, an insulating layer such as a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer may further be formed on an inner surface (e.g., a side surface and a bottom surface of a groove to be described later and an inner surface of through holes to be described later) and a portion of an outer surface (e.g., a lower surface or a bottom surface) of the substrate 110.
The substrate 110 may include a first surface (e.g., an upper surface or a top surface) 110S1 and a second surface (e.g., a lower surface or a bottom surface) 110S2 opposite to the first surface 110S1. A groove 111 is provided at the first surface 110S1 of the substrate 110, that is, the substrate 110 has a groove 111 recessed (inwardly) from the first surface 110S1. The groove 111 may have a rectangular shape, however, the shape of the groove 111 is not limited thereto. For example, the groove may have a cylindrical shape or a shape of frustum of a cone. The depth of the groove 111 is not particularly limited as long as the depth of the groove 111 matches the thickness of the chip 120.
The chip 120 is disposed in the groove 111. The chip 120 may be a logic chip, a memory chip, an analog chip, or a combination thereof, or the like. The chip 120 may include an active surface 120AS, an inactive surface 120IS opposite to the active surface 120AS, and a side surface 120SS connecting the active surface 120AS with the inactive surface 120IS. The active surface 120AS of the chip 120 may face a bottom surface 111BS of the groove 111, and the inactive surface 120IS of the chip 120 may face an open side of the groove 111.
A plurality of chip pads 121 are disposed on the active surface 120AS of the chip 120. The chip pads 121 may be formed of or include a conductive material such as a metal (e.g., copper (Cu)). In some example embodiments, the chip pads 121 may be disposed in an edge region of the active surface 120AS of the chip 120. In other example embodiments, at least one chip pad 121 may be disposed in a central region of the active surface 120AS of the chip 120, in addition to the chip pads 121 disposed in the edge region of the active surface 120AS of the chip 120. In still other example embodiments, the chip pads 121 may be disposed in substantially the entire region of the active surface 120AS of the chip 120.
The shielding layer 130 is disposed on a side surface 111SS and the bottom surface 111BS of the groove 111 and the inactive surface 120IS of the chip 120. For example, the shielding layer 130 may include a first sub-shielding layer 131 disposed between the bottom surface 111BS of the groove 111 and the active surface 120AS of the chip 120, a third sub-shielding layer 133 disposed on the inactive surface 120IS of the chip 120, and a second sub-shielding layer 132 disposed between the side surface 120SS of the chip 120 and the side surface 111SS of the groove 111 and connecting the first sub-shielding layer 131 with the third sub-shielding layer 133. The first sub-shielding layer 131 and the second sub-shielding layer 132 may be formed at the same time in the same process, or may be formed separately by the same process, or may be formed separately by different processes. The first sub-shielding layer 131, the second sub-shielding layer 132, and the third sub-shielding layer 133 are electrically connected to each other to constitute the shielding layer 130. Two or all of the first sub-shielding layer 131, the second sub-shielding layer 132, and the third sub-shielding layer 133 may be formed integrally.
The first sub-shielding layer 131, the second sub-shielding layer 132, and the third sub-shielding layer 133 may include the same material, or may include different materials. The materials of the first sub-shielding layer 131, the second sub-shielding layer 132, and the third sub-shielding layer 133 are not particularly limited, and may include any material having an electromagnetic shielding property. For example, the first sub-shielding layer 131, the second sub-shielding layer 132, and the third sub-shielding layer 133 may include a metal material such as copper, aluminum, iron, silver, nickel, lead, manganese, or an alloy thereof. For example, the first sub-shielding layer 131, the second sub-shielding layer 132, and the third sub-shielding layer 133 may include a composite material having an electromagnetic shielding property, for example, a composite material containing a substance having an electromagnetic shielding property such as graphene, carbon nanotubes, fullerenes, or MXene.
An upper surface of the third sub-shielding layer 133 may be coplanar with the first surface 110S1 of the substrate 110. However, the present disclosure is not limited thereto. The upper surface of the third sub-shielding layer 133 may be lower or higher than the first surface 110S1 of the substrate 110.
The thicknesses of the first sub-shielding layer 131, the second sub-shielding layer 132, and the third sub-shielding layer 133 are not particularly limited, and may be variously determined according to the intensity of an electromagnetic signal and/or a desired electromagnetic shielding effect. For example, the thickness of each of the first sub-shielding layer 131, the second sub-shielding layer 132, and the third sub-shielding layer 133 may range from about 5 μm to about 20 μm.
The first sub-shielding layer 131 has a plurality of openings 131OP that are disposed in correspondence with the plurality of chip pads 121, respectively. For example, each of the plurality of openings 131OP penetrates the first sub-shielding layer 131. In some example embodiments, the openings 131OP may be disposed in an edge region of the first sub-shielding layer 131. In other example embodiments, at least one opening 131OP may be disposed in a central region of the first sub-shielding layer 131, in addition to the openings 131OP disposed in the edge region of the first sub-shielding layer 131. In still other example embodiments, the openings 131OP may be disposed in substantially the entire region of the first sub-shielding layer 131. The shape of each of the openings 131OP is not particularly limited. For example, the opening 131OP may have a circular shape, a elliptical shape, or a quadrilateral (such as rectangle, square, and rhombus) shape in a plan view.
The plurality of chip pads 121 are disposed in correspondence with a plurality of openings 131OP of the first sub-shielding layer 131, respectively. The chip pads 121 may be electrically connected to the conductive connectors 140 to be described later via the openings 131OP.
The substrate 110 may further include a plurality of through holes 112 corresponding to the plurality of openings 131OP of the first sub-shielding layer 131, respectively. Each of the through holes 112 may penetrate the substrate 110, that is, may extend from the second surface 110S2 of the substrate 110 to the bottom surface 111BS of the groove 111. The size (e.g., width or diameter) of the through hole 112 in a horizontal direction may be smaller than the size (e.g., width or diameter) of the opening 131OP in the horizontal direction. For example, the through hole 112 may have a shape the same as the shape of the opening 131OP, and a size (e.g., width or diameter) smaller than the size (e.g., width or diameter) of the opening 131OP in a plan view.
A plurality of conductive connectors 140 may be disposed (e.g., filled) within the plurality of through holes 112, respectively. The conductive connector 140 may include a conductive material such as Cu, W, Al, Au, Ag, Ni, Ta, Ti, TaN, TiN, or a combination thereof.
A plurality of conductive bumps 150 may be disposed on the plurality of conductive connectors 140, respectively. For example, the conductive bump 150 may be disposed between a corresponding one of the conductive connectors 140 and a corresponding one of the chip pads 121. The conductive bump 150 may include a material the same as or different from that of the conductive connector 140. Each of the chip pads 121 is electrically connected to a corresponding one of the conductive connectors 140 through a corresponding one of the conductive bumps 150.
In a plan view, the conductive connector 140 and the conductive bump 150 may be located inside a corresponding one of the openings 131OP of the first sub-shielding layer 131 and spaced apart from an edge of the opening 131OP. In other words, the conductive connectors 140 and the conductive bumps 150 may not overlap the first sub-shielding layer 131 in a plan view.
For example, similarly to the through hole 112 in which the conductive connector 140 is formed, the conductive bump 150 may have the same shape as that of the opening 131OP, and a size (e.g., width or diameter) smaller than the size (e.g., width or diameter) of the opening 131OP in a plan view. In an example embodiment, the size (e.g., width or diameter) of each of the opening 131OP may range, for example, from about 100 μm to about 200 μm, the size (e.g., width or diameter) of each of the conductive bumps 150 may range, for example, from about 30 μm to about 150 μm, and the size (e.g., width or diameter) of each of the through holes 112 may range, for example, from about 10 μm to about 60 μm.
Each of the conductive bumps 150 may have an integral (or unitary) structure. In some example embodiments, each of the conductive bumps 150 may include a lower conductive bump 151 (see
The semiconductor package 100 according to an example embodiment may further include a protective layer 160. The protective layer 160 is disposed between the active surface 120AS of the chip 120 and the first sub-shielding layer 131 and between the side surface 120SS of the chip 120 and the second sub-shielding layer 132. The protective layer 160 may further be disposed between the active surface 120AS of the chip 120 and a portion of the bottom surface 111BS of the groove 111 that is not covered by the first sub-shielding layer 131. The protective layer 160 is provided to protect the chip 120, the first sub-shielding layer 131, the second sub-shielding layer 132, the chip pads 121, and the conductive bumps 150. As shown in
A redistribution layer 170 may be disposed on the second surface 110S2 of the substrate 110 to be electrically connected (e.g., directly electrically connected) to the conductive connectors 140. An example embodiment in which the redistribution layer 170 includes a single conductive layer is schematically shown in
A solder resist layer 180 may be disposed on the second surface 110S2 of the substrate 110 and partially cover the redistribution layer 170. The solder resist layer 180 may be formed of a solder resist material. The solder resist layer 180 may have an opening 180OP that exposes a portion of the redistribution layer 170.
Solder balls 190 may be formed on the solder resist layer 180 and electrically connected to the redistribution layer 170 through the openings 180OP of the solder resist layer 180. The solder balls 190 may be disposed directly on the redistribution layer 170 and optionally include a portion disposed on the solder resist layer 180. The solder balls 190 may be used as connection terminals for connecting the semiconductor package 100 to an external device. For example, an electrical signal may be transmitted from the chip 120 to the external device through the chip pad 121, the conductive bump 150, the conductive connector 140, the redistribution layer 170 and the solder ball 190, or an electrical signal may be transmitted from the external device to the chip 120 through the solder ball 190, the redistribution layer 170, the conductive connector 140, the conductive bump 150 and the chip pad 121.
The semiconductor package 100 according to an example embodiment of the present disclosure includes the groove 111 formed in the substrate 110, in which the chip 120 is disposed, and the first sub-shielding layer 131, the second sub-shielding layer 132, and the third sub-shielding layer 133 electrically connected to each other are disposed on the bottom surface 111BS and the side surface 111SS of the groove 111 and the inactive surface 120IS of the chip 120, respectively. By such configuration, all surfaces of the chip 120 (e.g., six surfaces including an upper surface, a lower surface, a left surface, a right surface, a front surface, and a rear surface) can be electromagnetically shielded without increasing a volume of the semiconductor package 100. Therefore, the semiconductor package 100 according to an example embodiment of the present disclosure may have an improved electromagnetic shielding effect. In addition, the first sub-shielding layer 131, the second sub-shielding layer 132, and the third sub-shielding layer 133 are connected to each other (e.g., formed integrally), and thus the strength of the shielding layer 130 may be enhanced. Therefore, the semiconductor package 100 including such a shielding layer 130 is not prone to failure, and thus has improved reliability. In addition, the semiconductor package according to an example embodiment of the present disclosure may be manufactured by a simplified manufacturing process which will be described later.
As described above, in an example embodiment in which the substrate 110 is formed of a conductive material or a semiconductor material, the semiconductor package 100 may further include an insulating layer disposed between the substrate 110 and other elements in contact with the substrate 110 (e.g., on the side surface 111SS and the bottom surface 111BS of the groove 111, on the inner surface of the through hole 112, and on the second surface 110S2 of the substrate 110).
A method of manufacturing a semiconductor package according to an example embodiment of the present disclosure will be described below with reference to
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Through the above steps, the semiconductor package 100 according to an example embodiment of the present disclosure may be manufactured.
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Subsequently, in step S260′, a protective material may be filled (e.g., charged) between the chip 120 and the first and second sub-shielding layers 131 and 132 (or in a gap between the chip 120 and the side surface 111SS and the bottom surface 111BS of the groove 111) by a dispensing process to form the protective layer 160. The protective layer 160 may be located between the side surface 120SS of the chip 120 and the second sub-shielding layer 132 and between the active surface 120AS of the chip 120 and the first sub-shielding layer 131. The protective layer 160 may also be located between the active surface 120AS of the chip 120 and a portion of the bottom surface 111BS of the groove 111 that is not covered by the first sub-shielding layer 131. In addition, the protective layer 160 may surround the conductive bumps 150 and the chip pads 121.
Next, step S270 described with reference to
According to the method of manufacturing the semiconductor package 100 in accordance with an example embodiment of the present disclosure, the groove 111 for accommodating the chip 120 is formed in the substrate 110, and the first sub-shielding layer 131, the second sub-shielding layer 132 and the third sub-shielding layer 133 are formed on the bottom surface 111BS and the side surface 111SS of the groove 111 and the inactive surface 120IS of the chip, respectively. Therefore, all surfaces of the chip 120 (e.g., six surfaces including an upper surface, a lower surface, a left surface, a right surface, a front surface, and a rear surface) can be electromagnetically shielded without increasing a volume of the semiconductor package 100. Therefore, the semiconductor package 100 according to an example embodiment of the present disclosure can have an improved electromagnetic shielding effect. In addition, there is no need to provide a separate shielding case (or cover) compared with a typical semiconductor package in which a shielding case (or cover) is provided, and thus the manufacturing process can be simplified. In addition, the first sub-shielding layer 131, the second sub-shielding layer 132 and the third sub-shielding layer 133 are connected to each other (e.g., formed integrally), and thus the strength of the shielding layer 130 may be enhanced. Therefore, the semiconductor package 100 including such a shielding layer 130 is not prone to failure, and thus has improved reliability.
Although the present disclosure has been specifically shown and described with reference to some example embodiments thereof, it will be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the appended claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2023 1 0875558.3 | Jul 2023 | CN | national |
