Patent Application
20250167134
This application claims priority to Chinese Patent Application No. 202311560185.7, filed on Nov. 22, 2023, in the China National Intellectual Property Administration, the disclosure of which is incorporated by reference herein in its entirety.
Embodiments of the present disclosure relate to a semiconductor package structure and a method of manufacturing the semiconductor package structure.
Along with the development of the electronic industry, electronic components mounted on electronic devices have become increasingly miniaturized and light weighted. For example, semiconductor package structures that are mounted on electronic components and handle high-capacity data while having relatively small volumes are being developed. Thus, a three-dimensional semiconductor package structure including a plurality of chips stacked to one another has been proposed.
In the existing semiconductor package structures, chips with identical or different specifications, types, and sizes may be stacked. When at least one portion of an upper chip protrudes with respect to a lower chip (e.g., a size of the lower chip is less than a size of the upper chip), the at least one portion of the upper chip may be in an overhanging state, that is, the upper chip includes an overhanging portion. Because chips may be generally thin, they may experience defects such as jitter, chip fragmentation, and non-bonding when performing a wire bonding operation (wire bonding process). Further, when stress is applied to the overhanging portion of the upper chip, the overhanging portion is prone to bending. Therefore, during the manufacturing of semiconductor package structures, there is a high likelihood that package yields will be reduced due to the overhanging portion of the upper chip.
One or more embodiments are directed to improving the overhanging defect caused by an overhanging portion of an upper chip during a wire bonding process.
One or more embodiments provide a semiconductor package structure and a method of manufacturing the semiconductor package structure that improves or reduces the overhanging defect caused by the overhanging portion of the upper chip by increasing the mechanical strength of the upper chip.
According to an aspect of an embodiment, there is provided a semiconductor package structure including a substrate, a plurality of chips stacked on the substrate in a second direction perpendicular to a surface of the substrate, a plurality of bonding wires connecting the plurality of chips to bonding pads included in the substrate, respectively, and a molding layer on the substrate, the molding layer encapsulating the plurality of chips and the plurality of bonding wires, wherein at least one first chip of the plurality of chips includes an overhanging portion protruding with respect to a second chip of the plurality of chips on the at least one first chip in a first direction parallel to the surface of the substrate, and wherein a support is on the at least one first chip.
A thickness of the support in the second direction may be equal to or less than a height of a wire loop of a corresponding bonding wire of the plurality of bonding wires.
The support may include a rigid material.
The rigid material may include silicon, a metal or a polymer resin.
Both end portions of the at least one first chip in the first direction may protrude with respect to the second chip on the at least one first chip.
One end portion of the at least one first chip in the first direction may protrude with respect to the second chip on the at least one first chip, and the other end portion of the at least one first chip in the first direction may be aligned with the second chip on the at least one first chip.
One end portion of the at least one first chip in the first direction may protrude with respect to one end portion of the second chip on the at least one first chip in the first direction, and the other end portion of the second chip on the at least one first chip in the first direction may protrude with respect to the other end portion of the at least one first chip in the first direction.
According to another aspect of an embodiment, there is provided a method of manufacturing a semiconductor package structure including providing a substrate, providing a first chip on the substrate along a second direction perpendicular to a surface of the substrate, providing a second chip on the first chip, the second chip including an overhanging portion protruding with respect to the first chip in a first direction parallel to the surface of the substrate, providing a support on the second chip and exposing a bonding pad included in the second chip, providing a bonding wire to connect the bonding pad included in the second chip to a bonding pad included in the substrate, and providing a molding layer on the substrate and encapsulating the first chip, the second chip, and the bonding wire.
A thickness of the support in the second direction may be equal to or less than a height of a wire loop of the bonding wire.
The support may include a rigid material.
The rigid material may include silicon, a metal or a polymer resin.
The second chip may include another overhanging portion protruding with respect to the first chip in the first direction.
According to another aspect of an embodiment, there is provided a semiconductor package structure including a substrate, a first chip on the substrate, a second chip on the first chip, a third chip on the second chip, a plurality of bonding wires connecting the first chip, the second chip, and the third chip to bonding pads included in the substrate, respectively, a first support between the first chip and the second chip, and a molding layer on the substrate, wherein the second chip includes an overhanging portion protruding with respect to first chip in a first direction parallel to a surface of the substrate.
A thickness of the first support in a second direction perpendicular to the surface of the substrate may be equal to or less than a height of a wire loop of a bonding wire of the plurality of bonding wires connecting the second chip to a bonding pad included in the substrate.
The first support may include a rigid material.
The rigid material may include silicon, a metal or a polymer resin.
Both end portions of the second chip in the first direction may protrude with respect to the first chip in the first direction.
At least one of end portions of the third chip in the first direction may protrude with respect to at least one of end portions of the second chip in the first direction.
The semiconductor package structure may further include a second support on the third chip opposite to the second chip.
A thickness of the second support in the second direction may be equal to or less than a height of a wire loop of a bonding wire of the plurality of bonding wires connecting the third chip to a bonding pad included in the substrate.
The above and/or other aspects will become clear and more easily understood from the following description for embodiments taken in conjunction with the accompanying drawings, in which:
Embodiments of the present disclosure will be more fully described with reference to the accompanying drawings in which exemplary embodiments of the present disclosure are illustrated. However, the present disclosure may be implemented in many different forms, and should not be constructed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that the present disclosure will be thorough and complete, and will fully convey the concepts of the embodiments of the present disclosure to those of ordinary skill in the art.
It will be understood that, although the terms first, second, third, fourth, etc. may be used herein to describe various elements, components, regions, layers and/or sections (collectively “elements”), these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Thus, a first element described in this description section may be termed a second element or vice versa in the claim section without departing from the teachings of the disclosure.
It will be understood that when an element or layer is referred to as being “over,” “above,” “on,” “below,” “under,” “beneath,” “connected to” or “coupled to” another element or layer, it can be directly over, above, on, below, under, beneath, connected or coupled to the other element or layer or intervening elements or layers may be present. In contrast, when an element is referred to as being “directly over,” “directly above,” “directly on,” “directly below,” “directly under,” “directly beneath,” “directly connected to” or “directly coupled to” another element or layer, there are no intervening elements or layers present.
As used herein, an expression “at least one of” preceding a list of elements modifies the entire list of the elements and does not modify the individual elements of the list. For example, an expression, “at least one of a, b, and c” should be understood as including only a, only b, only c, both a and b, both a and c, both b and c, or all of a, b, and c.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art of which the present disclosure is as a part. Terms, such as those defined in commonly used dictionaries, should be interpreted as having meanings that are consistent with their meaning in the context of the relevant art, and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
In the following description, for the purposes of explanation, numerous specific details are set forth to provide a thorough understanding of various exemplary embodiments. It is apparent, however, that various exemplary embodiments may be practiced without these specific details or with one or more equivalent arrangements.
Embodiments of the present disclosure will be described in detail hereinafter with reference to the accompanying drawings. Throughout the specification, the like components are referred to by the like reference numerals, and the repeated descriptions thereof may be omitted for conciseness of the description.
Referring to
The substrate 110 may be a printed circuit board (PCB). For example, the substrate 110 may be a multilayer printed circuit board. However, embodiments are not necessarily limited thereto. The substrate 110 has an upper surface and a lower surface opposite to the upper surface. The substrate 110 may include an upper bonding pad 111 disposed on the upper surface, a lower bonding pad 112 disposed on the lower surface, and an internal wire disposed inside the substrate 110 to electrically connect the upper bonding pad 111 and the lower bonding pad 112.
In an embodiment, the package substrate 110 may include a substrate base. The substrate base may include a single base layer or a structure in which a plurality of base layers are stacked. In an embodiment, the substrate base may include at least one material selected from a phenolic resin, an epoxy resin, and polyimide. The substrate base may include, for example, at least one material selected from flame retardant 4 (FR4), a tetrafunctional epoxy resin, polyphenyl ether, an epoxy resin/a polyphenylene oxide, bismaleimide triazine (BT), polyamide, cyanoacrylate ester, polyimide, and a liquid crystal polymer. However, embodiments are not necessarily limited thereto.
The chips may be mounted on the substrate 110 by front mounting or flip mounting, and may include a first chip 121, a second chip 122 and a third chip 123 sequentially stacked on the upper surface of the substrate 110. Types and structures of the first chip 121, the second chip 122 and the third chip 123 may be the same. However, in some embodiments, the types and structures of the first chip 121, the second chip 122 and the third chip 123 may be partially or completely different.
In an embodiment, the chip may correspond to a memory chip, a logic chip, an analog chip, or a combination thereof. The memory chip may include dynamic random access memory (DRAM) circuits, static random access memory (SRAM) circuits, flash memory access memory circuits, magnetic random access memory (MRAM) circuits, resistive random access memory (ReRAM) circuits, ferroelectric random access memory (FeRAM) circuits, or phase change random access memory (PcRAM) circuits integrated on and/or in a semiconductor substrate. The logic chip or the analog chip may include logic circuits or analog circuits integrated on and/or in the semiconductor substrate, respectively.
The first chip 121 may be disposed on the upper surface of the substrate 110, and electrically connected to the substrate 110. The first chip 121 may be mounted on the substrate 110 by means of wire bonding. For example, a surface of the first chip 121 facing the substrate 110 may be attached to the upper surface of the substrate 110 through an adhesive layer), and a bonding pad disposed on a surface of the first chip 121 opposite to the substrate 110 may be electrically connected to an upper bonding pad 111 disposed on the upper surface of the substrate 110 through a first bonding wire 171. However, the mounting form of the first chip 121 on the substrate 110 is not limited thereto.
The second chip 122 may be disposed on the first chip 121, and may be attached to the first chip 121 through a first adhesive layer 151. A bonding pad disposed on a surface of the second chip 122 opposite to the first chip 121 may be electrically connected to the upper bonding pad 111 disposed on the upper surface of the substrate 110 through a second bonding wire 172. In a first direction (horizontal direction) substantially parallel to the upper surface of the substrate 110, both end portions of the second chip 122 may protrude outwardly with respect to the first chip 121. For example, in the first direction, a left end portion of the second chip 122 may protrude outwardly with respect to a left end portion of the first chip 121, and a right end portion of the second chip 122 may protrude outwardly with respect to a right end portion of the first chip 121. In this case, in the first direction, a length of the second chip 122 is greater than a length of the first chip 121. A portion of the second chip 122 that protrudes with respect to the first chip 121 in the first direction may be referred to as an overhanging portion. For example, with respect to the first chip 121, the second chip 122 may include two overhanging portions in the first direction. In an embodiment, the two overhanging portions of the second chip 122 may have the same length in the first direction. However, embodiments are not limited thereto, for example, the two overhanging portions of the second chip 122 may have different lengths in the first direction.
A third chip 123 may be disposed on the second chip 122, and may be attached to the second chip 122 through a second adhesive layer 152. A bonding pad disposed on a surface of the third chip 123 opposite to the second chip 122 may be electrically connected to the upper bonding pad 111 disposed on the upper surface of the substrate 110 through a third bonding wire 173. In the first direction, both end portions of the third chip 123 may protrude outwardly with respect to the second chip 122. For example, in the first direction, a left end portion of the third chip 123 may protrude outwardly with respect to a left end portion of the second chip 122, and a right end portion of the third chip 123 may protrude outwardly with respect to a right end portion of the second chip 122. In this case, in the first direction, a length of the third chip 123 is greater than a length of the second chip 122. A portion of the third chip 123 that protrudes with respect to the second chip 122 in the first direction may be referred to as an overhanging portion. For example, with respect to the second chip 122, the third chip 123 may include two overhanging portions in the first direction. In an embodiment, the two overhanging portions of the third chip 123 may have the same length in the first direction. However, embodiments are not limited thereto, for example, the two overhanging portions of the third chip 123 may have different lengths in the first direction.
In an embodiment, the bonding wires 171, 172 and 173 may be formed through a wire bonding process. However, during the wire bonding process of forming the bonding wires 172 and 173, forces will be applied to the overhanging portions of the second chip 122 and the third chip 123. Since chips are usually thin, the second chip 122 and the third chip 123 are susceptible to overhanging defects such as jitter, chip fragmentation, and non-bonding due to the overhanging portions when performing the wire bonding process.
In an embodiment, wire loops of the bonding wires 171, 172 and 173 may be encapsulated by the adhesive layers 151 and 152 and the molding layer 130. For example, the wire loop of the first bonding wire 171 may be encapsulated by the first adhesive layer 151, the wire loop of the second bonding wire 172 may be encapsulated by the second adhesive layer 152, and the wire loop of the third bonding wire 173 may be encapsulated by the molding layer 130.
In an embodiment, a first support 161 and a second support 162 may be respectively disposed on the second chip 122 and the third chip 123 to increase the mechanical strength of the second chip 122 and the third chip 123, thereby improving the overhanging problem due to the overhanging portion of the upper chip.
The first support 161 may be disposed on the second chip 122, and may be encapsulated by the second adhesive layer 152. As illustrated in
As illustrated in
The second support 162 may be disposed on the third chip 123, and may be encapsulated by the molding layer 130. As illustrated in
As illustrated in
The first support 161 and the second support 162 may have a certain rigidity, and may be formed using any applicable rigid material. For example, the rigid material may include a conductive material, a semiconductor material or an insulating material. For example, the rigid material may include silicon, a metal (such as copper and its alloy), a polymer resin (such as an epoxy resin, a rigid thin film, etc.), and the like. When the rigid material is silicon, the chip disposed below is the first support 161 and the second support 162 may be a non-functional chip. For example, when the first support 161 includes silicon, the second chip 122 is a non-functional chip.
For the subsequent wire bonding process, the bonding pads of the second chip 122 and the third chip 123 need to be exposed and not covered by the first support 161 and the second support 162. Thus, sizes of the first support 161 and the second support 162 may be less than sizes of the second chip 122 and the third chip 123 below the first support 161 and the second support 162, respectively. In addition, the support should be as large as possible to enhance support in the case of ensuring that the bonding wires are avoided. In an embodiment, for example, on a plane parallel to the upper surface of the substrate 110, areas of the first support 161 and the second support 162 may be less than areas of the second chip 122 and the third chip 123 below them.
For example, a size of the first support 161 may be disposed to be less than a size of the second chip 122 to expose the bonding pad of the second chip 122. For example, on the plane parallel to the upper surface of the substrate 110, an area of the first support 161 may be less than an area of the second chip 122. For example, as illustrated in
Similarly, a size of the second support 162 may be disposed to be less than a size of the third chip 123 to expose the bonding pad of the third chip 123. For example, on the plane parallel to the upper surface of the substrate 110, an area of the second support 162 may be less than an area of the third chip 123. For example, as illustrated in
The molding layer 130 may be disposed on the substrate 110, and may encapsulate the first chip 121, the second chip 122, the third chip 123, the first adhesive layer 151, the second adhesive layer 152, the second support 162 and the bonding wire 170 on the substrate 110 to protect internal components (e.g., chips) of the semiconductor package structure 100. In an embodiment, the molding layer 130 may include an epoxy molding compound (EMC), an Ajinomoto buildup film (ABF), FR-4, bismaleimide triazine (BT), and the like. However, embodiments are not necessarily limited thereto.
In an embodiment, the semiconductor package structure 100 may further include an external connection terminal 180 disposed on the bonding pad 112 of the substrate 110. In an embodiment, the external connection terminal 180 may be, for example, a solder ball or a solder block. The external connection terminal 180 may include a solder material. In an embodiment, the solder material may include, for example, tin (Sn), indium (In), bismuth (Bi), antimony (Sb), copper (Cu), silver (Ag), zinc (Zn), lead (Pb) and/or an alloy thereof. The external connection terminal 180 may be electrically connected to an external device.
In an embodiment, by disposing a rigid support on an upper chip, a mechanical strength of the upper chip may be increased, thereby improving the overhanging defect due to the overhanging portion and further increasing a length of the overhanging portion of the upper chip. The rigid support disposed on the upper chip may be encapsulated by the corresponding adhesive layer or molding layer, and may be disposed so that a thickness thereof in a vertical direction is less than a height of the wire loop of the corresponding bonding wire, and thus, the semiconductor package structure may not only not change the thickness of the corresponding adhesive layer or molding layer, but may also not increase the overall thickness of the semiconductor package structure.
Referring to
In an embodiment, the chips include first chips 121a and 121b, second chips 122a and 122b and third chips 123a and 123b sequentially stacked on the upper surface of the substrate 110.
The first chips 121a and 121b may be disposed on the upper surface of the substrate 110, and may be electrically connected to the substrate 110 through first bonding wires 171a and 171b, respectively.
The second chips 122a and 122b may be disposed on the first chips 121a and 121b, respectively and may be electrically connected to the substrate 110 through second bonding wires 172a and 172b, respectively. The second chips 122a and 122b may be attached to the first chips 121a and 121b through first adhesive layers 151a and 151b, respectively.
The third chips 123a and 123b may be disposed on the second chips 122a and 122b, respectively and may be electrically connected to the substrate 110 through third bonding wires 173a and 173b, respectively. The third chips 123a and 123b may be attached to the second chips 122a and 121b through second adhesive layers 152a and 152b, respectively.
In the semiconductor package structure 100a according to the embodiment illustrated in
In the semiconductor package structure 100b according to the embodiment illustrated in
During the wire bonding process of the second bonding wires 172a and 172b and the third bonding wires 173a and 173b, overhanging defects such as jitter, chip fragmentation, non-bonding and the like may occur due to the overhanging portions of the upper chips 122a and 122b as well as 123a and 123b.
In an embodiment, first supports 161a and 161b and second supports 162a and 162b may be respectively disposed on the second chips 122a and 122b and the third chips 123a and 123b to increase the mechanical strength of the second chips 122a and 122b and the third chips 123a and 123b, thereby improving the overhanging defects due to the overhanging portions of the upper chips 122a and 122b as well as 123a and 123b.
The first supports 161a and 161b may be disposed on the second chips 122a and 122b, and may be encapsulated by the second adhesive layers 152a and 152b. The wire loops of the second bonding wires 172a and 172b may be encapsulated by the second adhesive layers 152a and 152b. In an embodiment, in a thickness direction, thicknesses of the first supports 161a and 161b may be equal to or less than heights of the wire loops of the second bonding wires 172a and 172b, and the heights of the wire loops of the second bonding wires 172a and 172b may be less than thicknesses of the second adhesive layers 152a and 152b.
Similarly, the second supports 162a and 162b may be disposed on the third chips 123a and 123b, and may be encapsulated by the molding layer 130. The wire loops of the third bonding wires 173a and 173b may be encapsulated by the molding layer 130. In an embodiment, in the thickness direction, thicknesses of the second supports 162a and 162b may be equal to or less than heights of the wire loops of the third bonding wires 173a and 173b, and heights of the wire loops of the third bonding wires 173a and 173b may be less than a distance between an upper surface of the molding layer 130 and upper surfaces of the third chips 123a and 123b.
Thus, without changing the thicknesses of the second adhesive layers 152a and 152b and the molding layer 130 and without increasing the overall thickness of the semiconductor package structures 100a and 100b, the mechanical strength of the second chips 122a and 122b and the third chips 123a and 123b may be increased by disposing the rigid first supports 161a and 161b and second supports 162a and 162b, thereby the overhanging defects due to the overhanging portions of the second chips 122a and 122b and the third chips 123a and 123b may be improved.
However, embodiments are not limited thereto. The arrangement of the first chip, the second chip and the third chip may be modified and combined in various ways. For example, the left end portion of the second chip may be aligned with the left end portion of the first chip, and the right end portion of the second chip may protrude with respect to the right end portion of the first chip in the first direction. The right end portion of the third chip may protrude with respect to the right end portion of the second chip, and the left end portion of the second chip may protrude with respect to the left end portion of the third chip in the first direction.
Furthermore, according to an embodiment, the stacked number of chips may not be limited to three, and may vary. For example, the stacked number of the chips may be two or four or more.
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Accordingly, the semiconductor package structure 100 according to an embodiment may be manufactured.
However, methods of manufacturing the semiconductor package structure according to embodiments are not limited thereto, and various modifications may be made.
It should be understood that embodiments described herein should be considered in a descriptive sense only and not for purposes of limitation. Descriptions of features or aspects within each embodiment should typically be considered as available for other similar features or aspects in other embodiments.
While embodiments have been described with reference to the figures, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope as defined by the following claims and their equivalents.
| Number | Date | Country | Kind |
|---|---|---|---|
| 202311560185.7 | Nov 2023 | CN | national |
