This U.S. non-provisional patent application claims priority under 35 U.S.C. § 119 from Korean Patent Application No. 10-2023-0094555, filed on Jul. 20, 2023 in the Korean Intellectual Property Office, the contents of which are herein incorporated by reference in their entirety.
The present disclosure relates to a semiconductor package, and in particular, to a stack-type semiconductor package including a backside power delivery network (BSPDN) layer.
A semiconductor package is configured so that an integrated-circuit chip can be easily used as a part of an electronic product. Conventionally, a semiconductor package includes a printed circuit board (PCB) and a semiconductor chip die that is mounted on the PCB and is electrically connected to the PCB using bonding wires or bumps. Many studies are being conducted to improve reliability and durability of the semiconductor package.
An embodiment of the inventive concept provides a semiconductor package with increased heat-dissipation and reliability characteristics.
An embodiment of the inventive concept provides a method of increasing a yield in a process of fabricating a semiconductor package.
According to an embodiment of the inventive concept, a semiconductor package includes a logic die that includes a backside power delivery network layer, an interposer die disposed on the logic die, a plurality of memory dies stacked on the interposer die, and a mold layer that covers the interposer die and the memory dies. Each of the logic die and the interposer die has a first width.
According to an embodiment of the inventive concept, a semiconductor package includes a logic die, an interposer die disposed on the logic die, a plurality of memory dies stacked on the interposer die, a mold layer that covers the interposer die and the memory dies, and a supporting substrate disposed on the memory dies and the mold layer. The logic die includes a backside power delivery network layer, a first substrate disposed on the backside power delivery network layer, a frontside interconnection layer disposed on the first substrate, and a first penetration via that penetrates the first substrate and is connected to the backside power delivery network layer. Each of the memory dies includes second penetration vias, and the interposer die includes third penetration vias that connect the logic die to the memory dies. The backside power delivery network layer has a first thickness, and the frontside interconnection layer has a second thickness that is less than the first thickness. Each of the memory dies has a third thickness, a sum of thicknesses of the logic and interposer dies is greater than the third thickness, and a diameter of the third penetration via is greater than a diameter of the second penetration via. A number of the third penetration vias is equal to or greater than a number of the second penetration via. The mold layer includes an oxide material, and the supporting substrate includes silicon. Each of the logic and interposer dies has a first width, and the interposer die has a higher thermal conductivity than the logic and memory dies.
According to an embodiment of the inventive concept, a semiconductor package includes a package substrate, an interposer substrate disposed on the package substrate, and a first semiconductor chip and a second semiconductor chip disposed on the interposer substrate and arranged side by side in a first direction. The second semiconductor chip includes a logic die that includes a backside power delivery network layer, an interposer die disposed on the logic die, a plurality of memory dies stacked on the interposer die, and a mold layer that covers the interposer die and the memory dies. The mold layer includes an oxide material, and the interposer die has a higher thermal conductivity than the logic memory dies.
Embodiments of the inventive concepts will now be described more fully with reference to the accompanying drawings, in which embodiments are shown.
Referring to
The logic die 100 includes a backside power delivery network layer BE_P, a first substrate 110 disposed on the backside power delivery network layer BE_P, and a frontside interconnection layer BE_S disposed on the first substrate 110. The backside power delivery network layer BE_P has a first thickness T1, and the frontside interconnection layer BE_S has a second thickness T2 that is equal to or different from the first thickness T1. In an embodiment, the first thickness T1 is greater than the second thickness T2.
As shown in
The first substrate 110 is a wafer-level semiconductor substrate that is formed of a semiconductor material, such as silicon (Si). For example, the first substrate 110 is one of a single-crystalline semiconductor substrate or a silicon-on-insulator (SOI) substrate. A first penetration via VI1 that is used to electrically connect the power lines 150_P and 151 to each other penetrates the first substrate 110, a portion of the second interlayer insulating layer 120b, and a portion of the first interlayer insulating layer 120a. Thus, a voltage can be applied from the backside power delivery network layer BE_P to the second power line 151 in the second interlayer insulating layer 120b through the first penetration via VI1. A first penetration insulating layer VL1 is interposed between the first penetration via VI1 and the first substrate 110. The first penetration via VI1 is formed of or includes at least one metal, such as aluminum, copper, tungsten, ruthenium, molybdenum, or cobalt. The first penetration insulating layer VL1 is formed of or includes at least one silicon-based insulating material, such as silicon oxide, silicon nitride, or silicon oxynitride). Since the backside power delivery network layer BE_P is disposed in the logic die 100, an integration density of the semiconductor package 1000 can be increased.
Referring to
Referring to
A third penetration via VI3 is disposed in the interposer die SMI that penetrates the third substrate 310, the sixth interlayer insulating layer 330, and a portion of the fifth interlayer insulating layer 320. A third penetration insulating layer VL3 is interposed between the third penetration via VI3 and the third substrate 310. The third penetration via VI3 electrically connects the logic die 100 to the memory dies M. The third penetration via VI3 is formed of or includes at least one metal, such as copper, aluminum, or tungsten. The third penetration insulating layer VL3 is formed of or includes at least one of silicon oxide, silicon nitride, or silicon oxynitride, and may have a single- or multi-layered structure. The third penetration insulating layer VL3 includes an air gap region. A diameter of the third penetration via VI3 is greater than a diameter of the second penetration via VI2. The number of the third penetration vias VI3 is equal to or greater than the number of the second penetration vias VI2.
The first to sixth interlayer insulating layers 120a, 120b, 220, 230, 320, and 330 are formed of or include at least one of silicon oxide, silicon nitride, silicon oxynitride, or porous insulating materials, and may have a single- or multi-layered structure. The first to sixth interlayer insulating layers 120a, 120b, 220, 230, 320, and 330 are each covered with a passivation layer PV. The passivation layers PV are formed of or include at least one of silicon oxide, silicon nitride, or SiCN, and may have a single- or multi-layered structure.
The internal interconnection lines 250 and 350, the signal line 150_S, and the power lines 150_P and 151 are formed of or include at least one of copper, aluminum, tungsten, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, or iridium, and may have a single- or multi-layered structure.
First upper conductive pads UBP1 are disposed on a top surface of the logic die 100. First lower conductive pads LBP1 are disposed on a bottom surface of the logic die 100. Second upper conductive pads UBP2 are disposed on a top surface of the interposer die SMI. Second lower conductive pads LBP2 are disposed on a bottom surface of the interposer die SMI. Upper chip pads UCP are disposed on top surfaces of the first to third memory dies M. In an embodiment, the upper chip pad UCP are not provided in the fourth memory die M4. Lower chip pads LCP are disposed on bottom surfaces of the first to fourth memory dies M1 to M4. The upper conductive pads UBP1 and UBP2, the lower conductive pads LBP1 and LBP2, the upper chip pads UCP, and the lower chip pads LCP are formed of or include at least one metal, such as copper (Cu), gold (Au), nickel (Ni), tin (Sn), silver (Ag), tungsten (W), or aluminum (Al)). First outer connection members SB1 are bonded to the first lower conductive pads LBP1. The first outer connection members SB1 include at least one of copper bumps, copper pillars, or solder balls.
In an embodiment, as shown in
Referring to
The second upper conductive pads UBP2 of the interposer die SMI are in direct contact with the corresponding lower chip pads LCP of the first memory die M1. The passivation layer PV of the interposer die SMI is in direct contact with the passivation layer PV of the first memory die M1. The second upper conductive pads UBP2 and the lower chip pads LCP are formed of a same material. The second upper conductive pad UBP2 and the lower chip pad LCP, which are in contact with each other, are bonded to each other to form a single integrated object. Thus, there might be no interface between the second upper conductive pad UBP2 and the lower chip pad LCP.
The mold layer 500 covers the interposer die SMI and the memory dies M. The mold layer 500 is formed of or includes an oxide material. For example, the mold layer 500 is formed of or includes an inorganic insulating material, such as silicon oxide.
The supporting substrate 400 covers the memory dies M and the mold layer 500. The supporting substrate 400 is formed of or includes silicon. The supporting substrate 400 is a reinforcing element that prevents warpage in the semiconductor package 1000, or spreads heat for heat dissipation. In addition, the supporting substrate 400 may include a substrate and an interlayer insulating layer. However, embodiments of the inventive concept are not necessarily limited thereto, and in some embodiment, the semiconductor package is provided without the supporting substrate 400. In an embodiment, a silicon oxide layer is interposed between the supporting substrate 400 and the second substrate 210 of the fourth memory die M4.
The logic die 100 is a base die that includes a semiconductor device. In some embodiments, the logic die 100 may be referred to as an interface die, a logic die, or a master die. The die may be referred to as a chip. The logic die 100 is an interface circuit between the memory dies M and an external controller. The logic die 100 is configured to receive commands, data, and/or signals that are transmitted from the external controller, and to transmit the received commands, data, and/or signals, to the memory dies M. The logic die 100 is, for example, a chip with a logic circuit.
The first to fourth memory dies M1 to M4 are sequentially stacked. The first to fourth memory dies M1 to M4 are memory chips of the same type. The memory chip may be, for example, one of a DRAM, a NAND Flash memory, an SRAM, an MRAM, a PRAM, or an RRAM chip. Each of the first to fourth memory dies M1 to M4 has a second width W2 in a first direction X and has a third thickness T3. The first width W1 of the logic die 100 and the interposer die SMI is greater than the second width W2 of the memory dies M. A sum of thicknesses of the logic die 100 and the interposer die SMI is a fourth thickness T4, which is greater than the third thickness T3.
Referring to
Referring to
Referring to
A grinding or etch-back process is performed on a top surface of the third substrate 310 to remove a portion of the third substrate 310 and expose the third penetration insulating layer VL3. The top surface of the third substrate 310 is formed at a level that is lower than an end portion of the third penetration via VI3. For example, a thickness of the third substrate 310 is reduced by the grinding process. The third penetration via VI3 includes a protruding portion that is higher than the top surface of the third substrate 310. The sixth interlayer insulating layer 330 is formed on the top surface of the third substrate 310. A chemical-mechanical polishing (CMP) or etch-back process is performed to remove a portion of the sixth interlayer insulating layer 330 and a portion of the third penetration insulating layer VL3 and to expose the third penetration via VI3. The second upper conductive pads UBP2, the second lower conductive pads LBP2, and the passivation layer PV are formed on the sixth interlayer insulating layer 330.
Referring to
The first to fourth memory dies M1 to M4 are stacked on the chip regions DR of the interposer die wafer SMIW. The memory dies M are bonded to each other by one of a direct-bonding process or a hybrid copper bonding process. The second memory die M2 is disposed such that its active surface faces the first memory die M1. The second memory die M2 is placed such that the third interlayer insulating layer 220 is in contact with the second substrate 210 and the lower chip pads LCP are in contact with the upper chip pads UCP, and the second memory die M2 is directly bonded to the first memory die M1 by performing, for example, a thermo-compression process. The first and second memory dies M1 and M2 are directly bonded to each other by the upper chip pads UCP and the lower chip pads LCP to form an interface therebetween. The interface between the first and second memory dies M1 and M2 includes an inorganic insulating material, such as silicon oxide, that is present between the upper chip pads UCP and between the lower chip pads LCP. The above-described method is used to bond the second memory die M2 to the first memory die M1, bond the third memory die M3 to the second memory die M2, and bond the fourth memory die M4 to the third memory die M3.
The stacked memory dies M are bonded to the interposer die wafer SMIW by, for example, a thermo-compression process. In an embodiment, one of a direct-bonding process or a hybrid copper bonding process is performed to bond the first memory die M1 to the interposer die wafer SMIW. The first memory die M1 is disposed such that the active surface of the first memory die M1 faces the interposer die wafer SMIW. The first memory die M1 is placed such that the third interlayer insulating layer 220 is in contact with the third substrate 310 and the lower chip pads LCP are in contact with the second upper conductive pads UBP2, and the first memory die M1 is directly bonded to the interposer die wafer SMIW by, for example, a thermo-compression process. The interposer die wafer SMIW and the first memory die M1 are directly bonded to each other by the second upper conductive pads UBP2 and the lower chip pads LCP to form an interface therebetween. The interface between the interposer die wafer SMIW and the first memory die M1 includes an inorganic insulating material, such as silicon oxide, that is present between the second upper conductive pads UBP2 and between the lower chip pads LCP.
Referring to
Referring to
Referring to
Referring to
Referring to
Referring to
In a method of fabricating a semiconductor package according to an embodiment of the inventive concept, the backside power delivery network layer BE_P is formed in a wafer-on-wafer (WoW) manner or by applying the WOW method, which can increase the productivity and yield of the fabrication process.
In a semiconductor package 2000 according to an embodiment of the inventive concept, an interposer substrate 20 is disposed on a package substrate 10. The package substrate 10 may be, for example, a double-sided or multi-layered printed circuit board. The interposer substrate 20 is formed of or includes, for example, silicon. A first semiconductor chip CH1 and a second semiconductor chip CH2 are disposed next to each other in the first direction X on the interposer substrate 20. The interposer substrate 20 includes internal interconnection lines that connect the first semiconductor chip CH1 and the second semiconductor chip CH2 to each other. The first semiconductor chip CH1 may be an application specific integrated circuit (ASIC) chip or a system-on-chip. The first semiconductor chip CH1 may be referred to as a host or an application processor (AP). The first semiconductor chip CH1 is connected to the interposer substrate 20 through the first outer connection members SB1. The second semiconductor chip CH2 has the same or similar features as the semiconductor package 1000 described above with reference to
In a semiconductor package according to an embodiment of the inventive concept, by disposing a power delivery network on a bottom surface of a substrate, integration density can be increased. Furthermore, heat in a logic die can be effectively dissipated by placing an interposer die that has the same size as the logic die between the logic die and memory dies, and thus, heat-dissipation performance and reliability characteristics of the semiconductor package can be increased.
In a method of fabricating a semiconductor package according to an embodiment, a backside power delivery network (BSPDN) layer is formed by applying a wafer-on-wafer (WoW) method, which can increase the productivity and yield of a fabrication process.
While embodiments of the inventive concept have been particularly shown and described, it will be understood by one of ordinary skill in the art that variations in form and detail may be made therein without departing from the spirit and scope of the attached claims.
Number | Date | Country | Kind |
---|---|---|---|
10-2023-0094555 | Jul 2023 | KR | national |