Semiconductor packages can be used in electronic devices, such as mobile phones and fitness trackers to track movements and health data. As the size of electronic devices decreases, there is a need to join multiple semiconductor packages in a limited space.
Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures.
The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the process for forming a first feature over a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. As used herein, the formation of a first feature on a second feature means the first feature is formed in direct contact with the second feature. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition does not in itself dictate a relationship between the embodiments and/or configurations discussed herein.
Spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper,” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
It is noted that references in the specification to “one embodiment,” “an embodiment,” “an example embodiment,” “exemplary,” etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. Further, when a particular feature, structure or characteristic is described in connection with an embodiment, it would be within the knowledge of one skilled in the art to effect such feature, structure or characteristic in connection with other embodiments whether or not explicitly described.
It is to be understood that the phraseology or terminology herein is for the purpose of description and not of limitation, such that the terminology or phraseology of the present specification is to be interpreted by those skilled in relevant art(s) in light of the teachings herein.
In some embodiments, the terms “about” and “substantially” can indicate a value of a given quantity that varies within 5% of the value (e.g., 1%, +2%, +3%, ±4%, +5% of the value). These values are merely examples and are not intended to be limiting. The terms “about” and “substantially” can refer to a percentage of the values as interpreted by those skilled in relevant art(s) in light of the teachings herein.
The discussion of elements in
Semiconductor devices with multiple semiconductor packages can be used in electronics devices, such as mobile phones and fitness trackers to track movements and health data. A first semiconductor package can be a system-on-a-chip (SOC). The SOC can include an inertial sensor, a gyroscope sensor, a pulse sensor, other types of sensors, and combinations thereof. A second semiconductor package can be a storage device. The storage device can include a dynamic random-access memory (DRAM), a NAND flash memory, other types of memory devices, and combinations thereof. A third semiconductor package can be a power management device. Other types of electronic components can be included in the first, second, and third semiconductor packages. As the size of electronic devices (e.g., mobile phones and fitness trackers) decreases, the multiple semiconductor packages need to be joined in a limited space.
A die attach film (DAF) can be formed on the first semiconductor package. First joint pads, such as copper (Cu) pads, can be formed within the DAF. In some embodiments, bottom surfaces of the first joint pads can be buried in the DAF and not in direct contact with the first semiconductor package. Top surfaces of the first joint pads can be substantially coplanar with a top surface of the DAF. A ball grid array (BGA) can be soldered between the first joint pads and second joint pads of the second semiconductor package. The first and second semiconductor packages can be stacked vertically, such as in the z-direction, to save space. However, due to the different mechanical properties between the first joint pads and the DAF, cracks can occur at the interfaces between the first joint pads and the DAF. Furthermore, because the first joint pads are not in direct contact with the first semiconductor package and there are no portions of the DAF that are above the first joint pads, delamination of the first joint pads can occur. Cracks and delamination can reduce the reliability of the semiconductor devices with multiple semiconductor packages.
The present disclosure provides example semiconductor devices with multiple semiconductor packages with improved reliability and an example method for fabricating the same. Adhesion layers, such as titanium (Ti) and chromium (Cr) layers, can be formed in contact with a first semiconductor package. First joint pads can be formed in contact with the adhesion layers. A DAF can be formed on the first semiconductor package and the first joint pads. The DAF can have slanted sidewalls. The slanted sidewalls can cover end portions of the adhesion layers and the first joint pads. The slanted sidewalls can expose middle portions of the first joint pads. A BGA can be soldered between the exposed middle portions of the first joint pads and second joint pads of a second semiconductor package. Because of the similar mechanical properties between the first joint pads and the adhesion layers, cracks at the interfaces between the first joint pads and the adhesion layers can be reduced. The first joint pads and the adhesion layers are in direct contact with the first semiconductor package. The adhesion layers can increase the adhesion of the first joint pads to the first semiconductor package. The slanted sidewalls of the DAF covering the end portions of the first joint pads and the adhesion layers can also improve bonding robustness. Therefore, there can be reduced delamination of the first joint pads. A reduced number of cracks and reduced delamination can improve the reliability of the semiconductor devices with multiple semiconductor packages.
First semiconductor package 102 can be a SOC. First semiconductor package 102 can include an inertial sensor, a gyroscope sensor, a pulse sensor, other types of electronic sensors, and combinations thereof. First semiconductor package 102 can include transistors, resistors, capacitors, inductors, interconnect structures, other types of components and structures, and combinations thereof. Second semiconductor package 138 can be a storage device. Second semiconductor package 138 can include a DRAM, a NAND flash memory, other types of memory devices, and combinations thereof. Second semiconductor package 138 can include transistors, word lines, bit lines, resistors, capacitors, inductors, interconnect structures, other types of components and structures, and combinations thereof.
ILD layer 104 can be disposed below first semiconductor package 102. First passivation layer 106 can be disposed below ILD layer 104. Second passivation layer 108 can be disposed below first passivation layer 106. IMD layer 134 can be disposed below I/O connections 118 and I/O connection protective layer 120. ILD layer 104, first passivation layer 106, second passivation layer 108, and IMD layer 134 can include an insulating material, such as silicon oxide (SiOx), silicon nitride (SiN), silicon carbon nitride (SiCN), silicon oxycarbon nitride (SiOCN), germanium oxide (GeOx), silicon germanium oxide (SiGeOx), and combinations thereof.
Seal rings 110 can be disposed within ILD layer 104 and first passivation layer 106. Seal rings 110 can include multiple metal rings and metal support structures. Seal rings 110 can be disposed near edge portions of first semiconductor package 102. First semiconductor packages 102 can be formed in an array. After ILD layer 104, first passivation layer 106, second passivation layer 108, first RDLs 112, polyimide layers 116, I/O connections 118, I/O connection protective layers 120, adhesion layers 122, first joint pads 124, and DAF 126 are formed on first semiconductor packages 102, grooves can be formed on the array of first semiconductor packages 102 between adjacent first semiconductor packages 102 by a laser grooving process. A dicing saw can follow the grooves and dice the array of first semiconductor packages 102 into individual first semiconductor packages 102. During the laser grooving process and the mechanical dicing process, vibrations and static electrical charges can damage the electrical connections between first semiconductor packages 102 and first RDLs 112. Seal rings 110 can reduce the vibrations and release the static electrical charges, hence protecting the electrical connections between first semiconductor packages 102 and first RDLs 112.
First RDL 112 can be disposed within ILD layer 104 and first passivation layer 106. First RDL 112 can include multiple metal via structures and metal lines. I/O connections 118 can be disposed through first passivation layer 106 and second passivation layer 108. I/O connections 118 can be electrically coupled to first RDL 112. TIV structures 128 can be disposed adjacent to first semiconductor packages 102. TIV structures 128 can be electrically coupled to second RDLs 132 and second BGA 137. TIV structures 128 can electrically couple first semiconductor package 102 and second semiconductor package 138. Second RDLs 132 can be disposed within IMD layer 134. Second RDLs 132 can include multiple metal via structures and metal lines. In some embodiments, there can be one or more layers of second RDLs 132. UBM layers 135 can be disposed below IMD layer 134.
Seal rings 110, first RDL 112, I/O connections 118, TIV structures 128, second RDLs 132, and UBM layers 135 can include a suitable conductive material, such as tungsten (W), molybdenum (Mo), nickel (Ni), bismuth (Bi), scandium (Sc), Ti, Cu, cobalt (Co), silver (Ag), aluminum (Al), titanium aluminum nitride (TiAlN), tantalum carbide (TaC), tantalum carbonitride (TaCN), tantalum silicon nitride (TaSiN), manganese (Mn), zirconium (Zr), titanium nitride (TiN), tantalum nitride (TaN), ruthenium (Ru), tungsten nitride (WN), titanium carbide (TiC), titanium aluminum carbide (TiAlC), tantalum aluminum carbide (TaAlC), metal alloys, and combinations thereof.
In some embodiments, barrier layers (not shown in
Polyimide layer 116 can be disposed below second passivation layer 108. Polyimide layer 116 can provide mechanical support for I/O connections 118. Polyimide layer 116 can include polyimide and other suitable polymer materials.
I/O connection protective layer 120 can be disposed below second passivation layer 108 and polyimide layer 116. I/O connection protective layer 120 can encapsulate I/O connections 118. Molding layer 130 can be interposed between first semiconductor package 102 and TIV structures 128. Filling layer 140 can be disposed adjacent to second BGA 137 and interposed between DAF 126 and second semiconductor package 138. I/O connection protective layer 120, molding layer 130, and filling layer 140 can include an epoxy resin, a die encapsulant, and other suitable organic materials. The epoxy resin can be filled with fillers, such as silica (SiO2). The epoxy resin can have various filler sizes, filler shapes, and filler contents. In some embodiments, filling layer 140 can include an epoxy resin with smaller-sized fillers than molding layer 130.
First BGA 136 can be disposed below UBM layers 135. Second BGA 137 can be interposed between first joint pads 124 and second joint pads 125. Second BGA 137 can be interposed between TIV structures 128 and second joint pads 125. First BGA 136 and second BGA 137 can include an array of solder balls. The solder balls can include a metal alloy, such as tin (Sn) and lead (Pb).
Adhesion layers 122 can be in contact with first semiconductor package 102. Adhesion layers 122 can include Ti, Cr, and other metals that can improve adhesion. Adhesion layers 122 can have a thickness H2 between about 100 nm and about 0.5 μm, between about 50 nm and about 0.8 μm, and between about 10 nm and about 1 μm. If thickness H2 is greater than about 1 μm, the fabrication time, manufacturing cost, and device size can be too great. If thickness H2 is less than about 10 nm, adhesion layers 122 cannot improve adhesion of first joint pads 124 to first semiconductor package 102.
First joint pads 124 can be in contact with adhesion layers 122. Second joint pads 125 can be disposed below second semiconductor package 138. First joint pads 124 and second joint pads 125 can include Cu and/or other suitable conductive materials. First joint pads 124 can have a thickness H1 between about 15 μm and about 200 μm, between about 5 μm and about 250 μm, and between about 0.5 μm and about 300 μm. If thickness H1 is greater than about 300 μm, the fabrication time, manufacturing cost, and device size can be too great. If thickness H1 is less than about 0.5 μm, the solderability of first joint pads 124 can be insufficient for second BGA 137 to attach to first joint pads 124. A ratio H1/H2 between thickness H1 and thickness H2 can be between about 50 and about 100, between about 30 and about 200, and between about 10 and about 300. If the ratio H1/H2 is greater than about 300, adhesion layers 122 cannot improve adhesion of first joint pads 124 to first semiconductor package 102. If the ratio H1/H2 is less than about 10, the solderability of first joint pads 124 can be insufficient for second BGA 137 to attach to first joint pads 124.
Adhesion layers 122 and first joint pads 124 can have a width W2 between about 100 μm and about 1000 μm, between about 50 μm and about 1500 μm, and between about 20 μm and about 2000 μm. Middle portions of first joint pads 124 exposed by the slanted sidewalls of DAF 126 can have a width W1 between about 80 μm and about 800 μm, between about 40 μm and about 1400 μm, and between about 15 μm and about 1800 μm. If width W1 is greater than about 1800 μm, or if width W2 is greater than about 2000 μm, the fabrication time, manufacturing cost, and device size can be too great and the number of solder balls per unit area of second BGA 137 can be too low. If width W1 is less than about 15 μm, or if width W2 is less than about 20 μm, the solderability of first joint pads 124 can be insufficient for second BGA 137 to attach to first joint pads 124. A ratio W2/W1 between width W2 and width W1 can be between about 2 and about 5, between about 1.5 and about 8, and between about 1.2 and about 10. If the ratio W2/W1 is less than about 1.2, the slanted sidewalls of DAF 126 can cover insufficient end portions of first joint pads 124 and leave large exposed areas of the middle portions of first joint pads 124. The solder balls can spread too easily in the middle portions of first joint pads 124 with large exposed areas and can be too flat. Flat solder balls cannot connect first joint pads 124 and second joint pads 125 effectively, which can reduce reliability. If the ratio W2/W1 is greater than about 10, the solderability of first joint pads 124 can be insufficient for second BGA 137 to attach to first joint pads 124. First joint pads 124 and adhesion layers 122 are in direct contact with first semiconductor package 102. Adhesion layers 122 can increase the adhesion of first joint pads 124 to first semiconductor package 102. Furthermore, because of the similar mechanical properties between first joint pads 124 and adhesion layers 122, cracks at the interfaces between first joint pads 124 and adhesion layers 122 can be reduced. A reduced number of cracks and improved adhesion can improve the reliability of the joint between first semiconductor package 102 and second semiconductor package 138.
DAF 126 can be disposed on first semiconductor package 102 and first joint pads 124. DAF 126 can include a polymer and other suitable organic materials. DAF 126 can include slanted sidewalls. An angle 1 between the slanted sidewalls and a horizontal direction, such as the x-direction, can be between about 50° and about 60°, between about 40° and about 70°, and between about 30° and about 80°. If angle 1 is less than about 30°, the slanted sidewalls of DAF 126 can cover insufficient end portions of first joint pads 124 and leave large exposed areas of the middle portions of first joint pads 124. The solder balls can spread too easily in the middle portions of first joint pads 124 with large exposed areas and can be too flat. Flat solder balls cannot connect first joint pads 124 and second joint pads 125 effectively, which can reduce reliability. If angle 1 is greater than about 80°, the solderability of first joint pads 124 can be insufficient for second BGA 137 to attach to first joint pads 124. If angle 1 is greater than about 80°, there can also be increased delamination of first joint pads 124.
The slanted sidewalls of DAF 126 can cover end portions of first joint pads 124 and adhesion layers 122. The covered end portions of first joint pads 124 and adhesion layers 122 can have a width W3 between about 50 μm and about 500 μm, between about 25 μm and about 750 μm, and between about 10 μm and about 1000 μm. If width W3 is less than about 10 μm, first joint pads 124 can delaminate too easily. If width W3 is greater than about 1000 μm, the solderability of first joint pads 124 can be insufficient for second BGA 137 to attach to first joint pads 124. A ratio W3/W2 between width W3 and width W2 can be between about 0.1 and about 0.3, between about 0.05 and about 0.4, and between about 0.01 and about 0.45. If the ratio W3/W2 is less than about 0.01, first joint pads 124 can delaminate too easily. If the ratio W3/W2 is greater than about 0.45, the solderability of first joint pads 124 can be insufficient for second BGA 137 to attach to first joint pads 124. The slanted sidewalls of DAF 126 covering the end portions of first joint pads 124 and adhesion layers 122 can improve first joint pads 124 bonding robustness, reduce delamination of first joint pads 124, and improve the reliability of the joint between first semiconductor package 102 and second semiconductor package 138.
Referring to
Referring to
Referring to
Referring to
Referring to
Referring to
Referring to
Referring to
Referring to
Referring to
Referring to
The present disclosure provides example semiconductor devices (e.g., semiconductor devices 100, 200, and 300) with multiple semiconductor packages (e.g., first semiconductor packages 102 and 202, second semiconductor package 138, and third semiconductor package 204) with improved reliability and an example method (e.g., method 400) for fabricating the same. Adhesion layers (e.g., adhesion layers 122), such as titanium (Ti) and chromium (Cr) layers, can be formed in contact with a first semiconductor package (e.g., first semiconductor package 102). First joint pads (e.g., first joint pads 124) can be formed in contact with the adhesion layers. A DAF (e.g., DAF 126) can be formed on the first semiconductor package and the first joint pads. The DAF can have slanted sidewalls. The slanted sidewalls can cover end portions of the adhesion layers and the first joint pads. The slanted sidewalls can expose middle portions of the first joint pads. A BGA (e.g., second BGA 137) can be soldered between the exposed middle portions of the first joint pads and second joint pads (e.g., second joint pads 125) of a second semiconductor package (e.g., second semiconductor package 138). Because of the similar mechanical properties between the first joint pads and the adhesion layers, cracks at the interfaces between the first joint pads and the adhesion layers can be reduced. The first joint pads and the adhesion layers are in direct contact with the first semiconductor package. The adhesion layers can increase the adhesion of the first joint pads to the first semiconductor package. The slanted sidewalls of the DAF covering the end portions of the first joint pads and the adhesion layers can also improve bonding robustness. Therefore, there can be reduced delamination of the first joint pads. A reduced number of cracks and reduced delamination can improve the reliability of the semiconductor devices with multiple semiconductor packages.
In some embodiments, a structure includes an adhesion layer in contact with a first semiconductor package and a first joint pad in contact with the adhesion layer. The structure further includes a film layer disposed on the first semiconductor package and the first joint pad, where the film layer includes a slanted sidewall, the slanted sidewall covers an end portion of the adhesion layer and a first portion of the first joint pad, and the slanted sidewall exposes a second portion of the first joint pad. The structure further includes a solder ball attached to the second portion of the first joint pad and a second joint pad of a second semiconductor package.
In some embodiments, a structure includes a substrate including a first redistribution layer (RDL) and a first ball grid array (BGA) and an input/output (I/O) connection disposed on and electrically coupled to the first RDL. The structure further includes a second RDL disposed on and electrically coupled to the I/O connection and a system-on-a-chip (SOC) disposed on and electrically coupled to the second RDL. The structure further includes a joint section including an adhesion layer in contact with the SOC, a first joint pad in contact with the adhesion layer, and a die attach film (DAF) disposed on the SOC and covering end portions of the adhesion layer and the first joint pad. The structure further includes a second BGA attached to the first joint pad and a second joint pad of a semiconductor package.
In some embodiments, a method includes forming an adhesion layer in contact with a first semiconductor package and forming a first joint pad in contact with the adhesion layer. The method further includes forming a film layer on the first semiconductor package and the first joint pad, including forming a slanted sidewall of the film layer, covering an end portion of the adhesion layer and a first portion of the first joint pad, and exposing a second portion of the first joint pad. The method further includes forming a ball grid array (BGA) between the second portion of the first joint pad and a second joint pad of a second semiconductor package.
It is to be appreciated that the Detailed Description section, and not the Abstract of the Disclosure section, is intended to be used to interpret the claims. The Abstract of the Disclosure section may set forth one or more but not all possible embodiments of the present disclosure as contemplated by the inventor(s), and thus, are not intended to limit the subjoined claims in any way.
The foregoing disclosure outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art will appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art will also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.