Patent Application
20250015034
The semiconductor industry has experienced rapid growth due to ongoing improvements in the integration density of a variety of electrical components. To accommodate the miniaturized scale of the semiconductor device, various technologies and applications have been developed for the packaging, involving greater numbers of different components with different functions. Improvement in integration density has resulted from iterative reduction of minimum feature size, which allows more components to be integrated into a given area.
However, the manufacturing of the semiconductor device involve many steps and operations on such a small and thin semiconductor device. The manufacturing of the semiconductor device in a miniaturized scale becomes more complicated. An increase in a complexity of manufacturing the semiconductor device may cause deficiencies such as poor electrical interconnection, delamination of components, or other issues, resulting in a high yield loss of the semiconductor device. As such, there are many challenges for modifying a structure of the semiconductor devices and improving the manufacturing operations.
Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It should be noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of elements and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “over,” “upper,” “on” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
As used herein, although the terms such as “first,” “second” and “third” describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms may be only used to distinguish one element, component, region, layer or section from another. The terms such as “first,” “second” and “third” when used herein do not imply a sequence or order unless clearly indicated by the context.
Notwithstanding that the numerical ranges and parameters setting forth the broad scope of the disclosure are approximations, the numerical values set forth in the specific examples are reported as precisely as possible. Any numerical value, however, inherently contains certain errors necessarily resulting from the standard deviation found in the respective testing measurements. Also, as used herein, the terms “substantially.” “approximately” and “about” generally mean within a value or range that can be contemplated by people having ordinary skill in the art. Alternatively, the terms “substantially.” “approximately” and “about” mean within an acceptable standard error of the mean when considered by one of ordinary skill in the art. People having ordinary skill in the art can understand that the acceptable standard error may vary according to different technologies.
Other than in the operating/working examples, or unless otherwise expressly specified, all of the numerical ranges, amounts, values and percentages such as those for quantities of materials, durations of times, temperatures, operating conditions, ratios of amounts, and the likes thereof disclosed herein should be understood as modified in all instances by the terms “substantially,” “approximately” or “about.” Accordingly, unless indicated to the contrary, the numerical parameters set forth in the present disclosure and attached claims are approximations that can vary as desired. At the very least, each numerical parameter should at least be construed in light of the number of reported significant digits and by applying ordinary rounding techniques. Ranges can be expressed herein as from one endpoint to another endpoint or between two endpoints. All ranges disclosed herein are inclusive of the endpoints, unless specified otherwise.
Other features and processes may also be included. For example, testing structures may be included to aid in the verification testing of the 3D packaging or 3DIC devices. The testing structures may include, for example, test pads formed in a redistribution layer or on a substrate that allows the testing of the 3D packaging or 3DIC, the use of probes and/or probe cards, and the like. The verification testing may be performed on intermediate structures as well as the final structure. Additionally, the structures and methods disclosed herein may be used in conjunction with testing methodologies that incorporate intermediate verification of known good dies to increase the yield and decrease costs.
In the present disclosure, a semiconductor structure and a method of manufacturing a semiconductor structure are provided. The semiconductor structure includes a first die, a redistribution layer under the first die, and a second die disposed under the redistribution layer and electrically connected to the first die through the redistribution layer. A daisy chain is embedded in the redistribution layer and the second die for evaluating a reliability of a bonding between the second die and the redistribution layer. Other features may also be included. In some embodiments, the method of manufacturing the semiconductor structure includes forming the daisy chain within the redistribution layer and the second die, bonding the second die with the redistribution layer, and measuring an electrical resistance of the daisy chain. Other processes may also be included. As a result, the reliability of the bonding between the second die and the redistribution layer can be evaluated based on the electrical resistance measurement.
In some embodiments, the semiconductor structure 100 includes a first die 101. In some embodiments, the first die 101 is a logic die, which may be a central processing unit (CPU) die, a micro control unit (MCU) die, an input-output (IO) die, a baseband (BB) die, an application processor (AP) die, or the like. In some embodiments, the first die 101 is a memory die such as a dynamic random-access memory (DRAM) die or a static random-access memory (SRAM) die, or may be another type of die. The first die 101 may include active devices (not shown) such as transistors and/or diodes, and may include passive devices (not shown) such as capacitors, inductors, resistors, or the like.
In some embodiments, the first die 101 includes a first die substrate 101a, a first die pad 101b and a connector 101c. In some embodiments, the first die substrate 101a includes semiconductive material such as silicon, germanium, gallium, arsenic, or a combination thereof. In some embodiments, the first die substrate 101a is a silicon substrate. In some embodiments, the first die substrate 101a includes a back side 101d and a front side 101e opposite to the back side 101d. Several circuitries and electrical components are disposed over or at the front side 101e, while no device is disposed over or at the back side 101d.
In some embodiments, the first die pad 101b is disposed over or on the front side 101e of the first die substrate 101a. In some embodiments, the first die pad 101b is electrically connected to a circuitry external to the first die 101, such that a circuitry of the first die 101 is electrically connected to the circuitry external to the first die 101 through the first die pad 101b. The first die pad 101b is configured to electrically couple with a conductive structure. The first die pad 101b is an I/O terminal of the first die 101. In some embodiments, the first die pad 101b includes gold, silver, copper, nickel, tungsten, aluminum, palladium and/or alloys thereof.
In some embodiments, the connector 101c is disposed at the first die pad 101b. The connector 101c includes conductive material such as solder, copper, nickel, gold or etc. In some embodiments, the connector 101c is a solder ball, a ball grid array (BGA) ball, controlled collapse chip connection (C4) bump, microbump, a pillar, a post or the like. The connector 101c is configured to connect the first die 101 to an external circuitry.
In some embodiments, the semiconductor structure 100 includes a fan out (InFO) structure 102 disposed under the first die 101. In some embodiments, the fan out structure 102 includes a second die 103, a molding 104, a through via 105 and a redistribution layer (RDL) 106. The second die 103 is surrounded by the molding 104. The through via 105 extends through the molding 104 and is adjacent to the second die 103. The RDL 106 is disposed under the second die 103 and the molding 104. I/O terminals of the second die 103 are fanned out and redistributed over the second die 103 in a greater area.
In some embodiments, an interconnect layer 111 is disposed between the fan out structure 102 and the first die 101. In some embodiments, the interconnect layer 111 includes an insulative layer 111a over the second die 103 and the molding 104, a connecting member 111b surrounded by the insulative layer 111a, and a receiving member 111c disposed over the connecting member 111b and the insulative layer 111a. In some embodiments, the insulative layer 111a is disposed over the back side 103d of the second die 103 and the back side 104a of the molding 104. In some embodiments, the insulative layer 111a includes dielectric material such as silicon oxide, silicon nitride, polyimide, or the like.
In some embodiments, the connecting member 111b is disposed over and coupled with the through via 105. In some embodiments, the connecting member 111b extends through the insulative layer 111a. In some embodiments, the receiving member 111c is disposed over and coupled with the connecting member 111b. In some embodiments, the connector 101c is disposed over and coupled with the receiving member 111c, so that the first die 101 is electrically connected to the through via 105 through the interconnect layer 111. In some embodiments, the connecting member 111b and the receiving member 111c include conductive material such as copper, silver, gold or the like.
In some embodiments, the second die 103 is a system on chip (SOC) that integrates all electronic components into a single die. In some embodiments, the second die 103 is a logic die, an input-output (IO) die, an application processor (AP) die, or the like. In some embodiments, the second die 103 is a memory die such as a dynamic random-access memory (DRAM) die or a static random-access memory (SRAM) die, or may be another type of die. The second die 103 may include active devices (not shown) such as transistors and/or diodes, and may include passive devices (not shown) such as capacitors, inductors, resistors, or the like.
In some embodiments, the second die 103 includes a second die substrate 103a and a second die pad 103b. In some embodiments, the second die substrate 103a includes semiconductive material such as silicon, germanium, gallium, arsenic, or a combination thereof. In some embodiments, the second die substrate 103a is a silicon substrate. In some embodiments, the second die substrate 103a includes a back side 103d and a front side 103e opposite to the back side 103d. Several circuitries and electrical components are disposed over or at the front side 103e, while no device is disposed over or at the back side 103d.
In some embodiments, the second die pad 103b is disposed over or on the front side 103e of the second die substrate 103a. In some embodiments, the second die pad 103b is electrically connected to a circuitry external to the second die 103, such that a circuitry of the second die 103 is electrically connected to the circuitry external to the second die 103 through the second die pad 103b. The second die pad 103b is configured to electrically couple with a conductive structure. The second die pad 103b is I/O terminal of the second die 103. In some embodiments, the second die pad 103b includes gold, silver, copper, nickel, tungsten, aluminum, palladium and/or alloys thereof.
In some embodiments, the molding 104 surrounds the second die 103a. The molding 104 contacts a sidewall of the second die substrate 103a. In some embodiments, the molding 104 includes molding compound, epoxy, polymer or the like. In some embodiments, the molding 104 is configured to protect the second die 103. In some embodiments, the molding 104 includes a back side 104a and a front side 104b opposite to the back side 104a. In some embodiments, the back side 104a of the molding 104 is substantially coplanar with the back side 103d of the second die 103, and the front side 104b of the molding 104 is substantially coplanar with the front side 103e of the second die 103.
In some embodiments, the through via 105 is surrounded by the molding 104. The through via 105 extends through the molding 104. The through via 105 extends between the back side 104a and the front side 104b of the molding 104. In some embodiments, the through via 105 is a through molding via (TMV). In some embodiments, the through via 105 includes conductive material such as gold, silver, copper, nickel, tungsten, aluminum, palladium and/or alloys thereof.
In some embodiments, the RDL 106 is disposed at the front side 103e of the second die 103 and the front side 104b of the molding 104. In some embodiments, the RDL 106 re-routes a path from the second die 103 so as to redistribute I/O terminals of the second die 103 at the front side 104b of the molding 104. In some embodiments, the RDL 106 includes a dielectric layer 106a and an interconnect structure 106b surrounded by the dielectric layer 106a. In some embodiments, the dielectric layer 106a is disposed under the second die 103a and the molding 104. In some embodiments, the dielectric layer 106a is in contact with the front side 103e of the second die 103 and the front side 104b of the molding 104. In some embodiments, the dielectric layer 106a includes dielectric material such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, polymer, polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), or the like.
In some embodiments, the interconnect structure 106b includes several conductive vias 106c and several conductive members 106d. In some embodiments, the interconnect structure 106b includes conductive material such as gold, silver, copper, nickel, tungsten, aluminum, palladium and/or alloys thereof. The conductive via 106c is electrically coupled with the conductive member 106d.
In some embodiments, the conductive via 106c is partially exposed through the dielectric layer 106a and is electrically coupled with the through via 105, so that the interconnect structure 106b is electrically connected to the through via 105. In some embodiments, the conductive via 106c is partially exposed through the dielectric layer 106a and is electrically coupled with the second die pad 103b of the second die 103, so that the interconnect structure 106b is electrically connected to the second die 103. In some embodiments, the conductive member 106d laterally extends within the dielectric layer 106a.
Referring to
In some embodiments, the third conductive pad 106h is electrically coupled with the fourth conductive pad 106i. In some embodiments, the third conductive pad 106h is electrically coupled with the fourth conductive pad 106i through some of conductive members 106d. In some embodiments, the first conductive pad 106f and the second conductive pad 106g are electrically isolated from the third conductive pad 106h and the fourth conductive pad 106i. In some embodiments, the fourth conductive pad 106i is electrically connected to a power or an electrical ground. In some embodiments, a total number of the third conductive pads 106h is substantially greater than a total number of the first conductive pads 106f. In some embodiments, a ratio of the total number of the third conductive pads 106h to the total number of the first conductive pads 106f is substantially greater than 3:1.
In some embodiments, the semiconductor structure 100 includes the third die 107 disposed under the RDL 106. In some embodiments, the third die 107 includes passive devices such as capacitors, inductors, resistors, or the like. In some embodiments, the third die 107 includes several capacitors 110. In some embodiments, the third die 107 includes a third die substrate 107a, an inter-layer dielectric (ILD) layer 107f, a third die pad 107b and a fourth die pad 107c. The third die pad 107b and the fourth die pad 107 are disposed over the third die substrate 107a and surrounded by the ILD layer 107f.
In some embodiments, the third die substrate 107a includes semiconductive material such as silicon, germanium, gallium, arsenic, or a combination thereof. In some embodiments, the third die substrate 107a is a silicon substrate. In some embodiments, the third die substrate 107a includes a back side 107d and a front side 107e opposite to the back side 107d. Several circuitries and electrical components are disposed over or at the front side 107e, while no device is disposed over or at the back side 107d. The ILD layer 107f is disposed over the front side 107e. In some embodiments, the ILD layer 107f includes dielectric material such as silicon oxide, silicon oxynitride, polyimide, silicon nitride or the like.
In some embodiments, the third die pad 107b and the fourth die pad 107c are disposed over or on the front side 107e of the third die substrate 107a. In some embodiments, the third die pad 107b and the fourth die pad 107c are respectively electrically connected to the conductive via 106c and/or the conductive pad 106e within the dielectric layer 106a of the RDL 106. In some embodiments, the third die pad 107b and the fourth die pad 107c are I/O terminals of the third die 107. In some embodiments, the third die pad 107b and the fourth die pad 107c include gold, silver, copper, nickel, tungsten, aluminum, palladium and/or alloys thereof. In some embodiments, the third die pads 107b are electrically connected in series by a second interconnect member 107g extending within the third die 107. In some embodiments, the second interconnect member 107g extends within the ILD layer 107f. In some embodiments, the second interconnect member 107g extends along a periphery of the third die 107.
In some embodiments, some of the fourth die pads 107c are electrically connected in series. In some embodiments, some of the fourth die pads 107c are electrically connected in series to a power or a ground. In some embodiments, the capacitor 110 is disposed between and connected to one of the fourth die pads 107c connecting to a power and another one of the fourth die pads 107c connecting to a ground.
In some embodiments, the third die pads 107b are respectively arranged at corners of the third die 107. Referring to
In some embodiments, the third die 107 is bonded under the RDL 106 by several conductive bumps 108. The conductive bumps 108 are disposed between the RDL 106 and the third die 107. In some embodiments, the conductive bump 108 includes conductive material such as solder, copper, nickel, gold or etc. In some embodiments, the conductive bump 108 is a solder ball, a ball grid array (BGA) ball, controlled collapse chip connection (C4) bump, microbump, a pillar, a post or the like. The conductive bump 108 is configured to connect the third die 107 to an external circuitry.
In some embodiments, the conductive bumps 108 include several first conductive bumps 108a and several third conductive bumps 108c. In some embodiments, the first conductive bump 108a and the third conductive bump 108c are respectively a solder ball, microbump, a pillar, a post or the like. In some embodiments, each of the first conductive bumps 108 is electrically coupled with corresponding one of the first conductive pads 106f and corresponding one of the third die pads 107b.
In some embodiments, the first conductive bumps 108a are electrically connected in series. In some embodiments, the first conductive bumps 108a, the first conductive pads 106f, the second conductive pads 106g and the third die pads 107b are electrically connected in series as part of the daisy chain. In some embodiments, the daisy chain is configured to detect a reliability of bonding between the third die 107 and the RDL 106. In some embodiments, the daisy chain is configured to detect reliability of bonding between the third die pads 107b and the first conductive pads 106f by the first conductive bumps 108a. In some embodiments, a number of the first conductive bumps 108a is four or more. In some embodiments, the capacitors 110 are electrically isolated from the daisy chain.
In some embodiments, each of the third conductive bumps 108c is electrically coupled with corresponding one of the third conductive pads 106h and corresponding one of the fourth die pads 107c. In some embodiments, the third conductive bumps 108c, the third conductive pads 106h, the fourth conductive pads 106i and the fourth die pads 107c are electrically connected isolated from the first conductive bumps 108a, the first conductive pads 106f, the second conductive pads 106g and the third die pads 107b. In some embodiments, the third conductive bumps 108c, the third conductive pads 106h, the fourth conductive pads 106i and the fourth die pads 107c are electrically connected to a power or a ground. In some embodiments, the third die 107 is electrically connected to the second die 103 through the third conductive bumps 108c and the third conductive pads 106h.
In some embodiments, the conductive bumps 108 include several second conductive bumps 108b and several fourth conductive bumps 108d. In some embodiments, the second conductive bump 108b and the fourth conductive bump 108d are respectively a solder ball, a ball grid array (BGA) ball, controlled collapse chip connection (C4) bump, a pillar, a post or the like. The second conductive bumps 108b and the fourth conductive bumps 108d are disposed under the RDL 106 and surround the third die 107. In some embodiments, the second conductive bump 108b and the fourth conductive bump 108d are respectively substantially larger than the first conductive bump 108a. In some embodiments, the second conductive bump 108b and the fourth conductive bump 108d are respectively substantially larger than the third conductive bump 108c.
In some embodiments, each of the second conductive bumps 108b is electrically coupled with corresponding one of the second conductive pads 106g. In some embodiments, the second conductive bumps 108b are electrically connected to the first conductive bumps 108a, the first conductive pads 106f and the third die pads 107b in series to form the daisy chain. In some embodiments, a voltage is applied between the second conductive bumps 108b for detecting the reliability of the bonding between the third die pads 107b and the first conductive pads 106f by the first conductive bumps 108a. That is, the voltage is applied to the daisy chain for the detection. If the daisy chain in an open circuit state was detected, it indicates that the bonding of the third die 107 to the RDL 106 is problematic or is potentially failure. If the daisy chain in a closed circuit state was detected, it indicates that the bonding of the third die 107 to the RDL 106 is fine or is not potentially failure. In some embodiments, the detection is performed by measuring an electrical resistance of the daisy chain. If a predetermined electrical resistance is measured, it indicates that the bonding of the third die 107 to the RDL 106 is fine or is not potentially failure. Otherwise, the bonding is problematic or is potentially failure.
In some embodiments, the fourth conductive bumps 108d is electrically coupled with corresponding one of the fourth conductive pads 106i. In some embodiments, the fourth conductive bumps 108d, the fourth conductive pads 106i, the third conductive pads 106h, the third conductive bumps 108c and the fourth die pads 107c are electrically in series as a functional chain or a part of a functional chain. In some embodiments, the fourth conductive bumps 108d, the fourth conductive pads 106i, the third conductive pads 106h, the third conductive bumps 108c and the fourth die pads 107c are electrically in series to a power or a ground. In some embodiments, the fourth conductive bumps 108d, the fourth conductive pads 106i, the third conductive pads 106h, the third conductive bumps 108c and the fourth die pads 107c are electrically isolated from the daisy chain. In some embodiments, the second conductive bumps 108b and/or the fourth conductive bumps 108d are bonded on a circuit board (e.g. printed circuit board PCB, or the like).
In the present disclosure, a method of manufacturing a semiconductor structure 100 is also disclosed. In some embodiments, the semiconductor structure 100 is formed by a method 200. The method 200 includes a number of operations and the description and illustration are not deemed as a limitation as the sequence of the operations.
In operation 201, a molding 104 is formed to surround a second die 103 as shown in
In some embodiments, a through via 105 is formed within the molding 104 as shown in
In some embodiments, an interconnect layer 111 is formed over the second die 103, the molding 104 and the through via 105 as shown in
In some embodiments, the insulative layer 111a includes dielectric material such as silicon oxide, silicon nitride, polyimide, or the like. In some embodiments, the connecting member 111b and the receiving member 111c include conductive material such as copper, silver, gold or the like. In some embodiments, the insulative layer 111a is formed by deposition or any other suitable operations. In some embodiments, the connecting member 111b and the receiving member 111c are formed by electroplating or any other suitable operations.
In some embodiments, a first die 101 is bonded over the second die 103 and the molding 104 by connectors 101c as shown in
In operation 202, a redistribution layer (RDL) 106 is formed over the second die 103 and the molding 104 as shown in
In operation 203, a third die 107 is bonded over the RDL 106 by conductive bumps 108 as shown in
In some embodiments, the conductive bumps 108 includes a first conductive bump 108a and a third conductive bump 108c. In some embodiments, the first conductive bump 108a is bonded with the third die pad 107b, and the third conductive bump 108c is bonded with the fourth die pad 107c. In some embodiments, the first conductive bump 108a is disposed above and bonded with the first conductive pad 106f, and the third conductive bump 108c is disposed over and bonded with the third conductive pad 106h. In some embodiments, the third die pad 107b, the first conductive bump 108a and the first conductive pad 106f are electrically connected in series.
In some embodiments, the conductive bumps 108 includes a second conductive bump 108b and a fourth conductive bump 108d. In some embodiments, after the bonding of the third die 107 over the RDL 106, the second conductive bump 108b is bonded with the second conductive pad 106g, and the fourth conductive bump 108d is bonded with the fourth conductive pad 106i as shown in
In some embodiments, a voltage is applied between the second conductive bumps 108b for detecting the reliability of the bonding between the third die pads 107b and the first conductive pads 106f by the first conductive bumps 108a. That is, the voltage is applied to the daisy chain for the detection. In some embodiments, a first probe 112a is in contact with one of the second conductive bumps 108b, and a second probe 112b is in contact with another one of the second conductive bumps 108b as shown in
One aspect of this disclosure relates to a semiconductor structure. The semiconductor structure includes a first die; a molding surrounding the first die; a redistribution layer (RDL) disposed under the first die and the molding, and including a plurality of first conductive pads and a dielectric layer surrounding the plurality of first conductive pads; a second die disposed under the RDL, and including a plurality of first die pads over the second die; and a plurality of first conductive bumps disposed between the RDL and the second die, wherein each of the plurality of first conductive bumps is electrically coupled with corresponding one of the plurality of first die pads and corresponding one of the plurality of first conductive pads, the plurality of first die pads are respectively arranged at corners of the second die, and the plurality of first conductive bumps are electrically connected in series.
In some embodiments, the plurality of first conductive pads, the plurality of first conductive bumps and the plurality of first die pads are electrically connected in series. In some embodiments, the semiconductor structure further comprises a plurality of second conductive pads surrounded by the dielectric layer, and a plurality of second conductive bumps disposed under the RDL, wherein each of the plurality of second conductive bumps is electrically coupled with corresponding one of the plurality of second conductive pads. In some embodiments, the plurality of second conductive pads and the plurality of first conductive pads are electrically connected in series.
In some embodiments, one of the plurality of first conductive pads is connected to one of the plurality of second conductive pads by a first interconnect member extending within and surrounded by the dielectric layer. In some embodiments, one of the plurality of first die pads is connected to another one of the plurality of first die pads by a second interconnect member extending within the second die. In some embodiments, the second interconnect member extends along a periphery of the second die. In some embodiments, the second die includes a plurality of second die pads over the second die, the RDL includes a plurality of third conductive pads surrounded by the dielectric layer, and each of a plurality of third conductive bumps is electrically coupled with corresponding one of the plurality of second die pads and corresponding one of the plurality of third conductive pads.
In some embodiments, the plurality of first conductive pads, the plurality of first conductive bumps and the plurality of first die pads are electrically isolated from the plurality of third conductive pads, the plurality of third conductive bumps and the plurality of second die pads. In some embodiments, the plurality of second die pads are electrically connected in series. In some embodiments, the first die is electrically connected to the second die through the plurality of third conductive pads and the plurality of third conductive bumps.
In some embodiments, the RDL includes a plurality of fourth conductive pads surrounded by the dielectric layer, and each of a plurality of fourth conductive bumps is disposed under the RDL and is electrically coupled with corresponding one of the plurality of fourth conductive pads. In some embodiments, one of the plurality of fourth conductive pads is electrically coupled with one of the plurality of third conductive pads. In some embodiments, the plurality of fourth conductive bumps are electrically connected to a power or a ground. In some embodiments, a number of the plurality of first conductive bumps is four.
An aspect of this disclosure relates to a semiconductor structure. The semiconductor structure includes a redistribution layer (RDL) including a plurality of first conductive pads, a plurality of second conductive pads, and a dielectric layer surrounding the plurality of first conductive pads and the plurality of second conductive pads; a die disposed under the RDL, and including a plurality of die pads over the die; and a plurality of first conductive bumps disposed between the RDL and the die; and a plurality of second conductive bumps disposed under the RDL, wherein each of the plurality of first conductive bumps is electrically coupled with corresponding one of the plurality of die pads and corresponding one of the plurality of first conductive pads, each of the plurality of second conductive bumps is electrically coupled with corresponding one of the plurality of second conductive pads, the plurality of die pads are respectively arranged at corners of the die, and the plurality of first conductive pads, the plurality of first conductive bumps, the plurality of die pads, the plurality of second conductive pads and the plurality of second conductive bumps are electrically connected in series as a daisy chain.
In some embodiments, the die is a passive device and includes a plurality of capacitors electrically isolated from the daisy chain. In some embodiments, each of the plurality of first conductive bumps is smaller than each of the plurality of second conductive bumps.
An aspect of this disclosure relates to a method of manufacturing a semiconductor structure. The method includes forming a molding to surround a first die; forming a redistribution layer (RDL) over the first die and the molding, wherein the formation of the RDL includes forming a plurality of first conductive pads at least partially exposed through a dielectric layer; and bonding a second die over the RDL by a plurality of first conductive bumps correspondingly disposed on the plurality of first conductive pads, wherein the plurality of first conductive pads and the plurality of first conductive bumps are electrically connected in series.
In some embodiments, the method further includes detecting the bonding of the second die by measuring an electrical resistance between two of the plurality of first conductive pads.
The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.
