1. Field of the Invention
The present application relates to the field of electronics, and more particularly, to methods of forming electronic component packages and related structures.
2. Description of the Related Art
To form an electronic component package, an electronic component is mounted to a substrate. The substrate includes traces on the same surface of the substrate to which the electronic component is mounted. Bond wires are formed to electrically connect bond pads of the electronic component to the traces.
To protect the electronic component as well as the bond wires, the electronic component and bond wires are covered in an encapsulant. The traces extend from under the encapsulant to an exposed area of the surface of the substrate outside of the periphery of the encapsulant, i.e., not covered by the encapsulant. The traces include terminals on the exposed area of the substrate outside of and around the encapsulant.
Solder balls are formed on the terminals. These solder balls extend from the substrate to a height greater than the height of the encapsulant to allow the solder balls to be electrically connected to a larger substrate such as a printed circuit motherboard.
However, the solder balls are substantially spherical in shape. Thus, forming the solder balls with a height greater than the height of the encapsulant places fundamental restrictions on minimizing the pitch of the solder balls.
In accordance with one embodiment, a method of forming an electronic component assembly includes forming a stackable protruding via package including enclosing an electronic component and electrically conductive first traces on a first surface of a substrate in a package body, e.g., an encapsulant. Protruding via apertures are formed through the package body to expose the first traces, e.g., terminals thereof. The protruding via apertures are filled with solder to form electrically conductive vias in direct physical and electrical contact with the first traces. Via extension bumps are attached to first surfaces of the vias. The vias and the via extension bumps are reflowed to form protruding vias. The protruding vias extend from the first traces through the package body and protrude above a principal surface of the package body.
The protruding vias enable electrical connection of the stackable protruding via package to a larger substrate such as a printed circuit motherboard. Further, the protruding vias in accordance with one embodiment are formed with a minimum pitch.
In one embodiment, the method further includes stacking a second package on the stackable protruding via package. By stacking the second package on the stackable protruding via package, the occupied area on the larger substrate is minimized as compared to mounting the second package and the stackable protruding via package to the larger substrate in a side by side arrangement.
These and other features of the present invention will be more readily apparent from the detailed description set forth below taken in conjunction with the accompanying drawings.
In the following description, the same or similar elements are labeled with the same or similar reference numbers.
As an overview, referring to
Referring now to
Referring now to
Now in more detail,
Stackable protruding via package 100 further includes an electronic component 104. In one embodiment, electronic component 104 is an integrated circuit chip, e.g., an active component. However, in other embodiments, electronic component 104 is a passive component such as a capacitor, resistor, or inductor.
In accordance with this embodiment, electronic component 104 includes an active surface 106 and an opposite inactive surface 108. Electronic component 104 further includes bond pads 110 formed on active surface 106. Inactive surface 108 is mounted to upper surface 102U of substrate 102 with an adhesive 112, sometimes called a die attach adhesive.
Formed on upper surface 102U of substrate 102 are electrically conductive upper, e.g., first, traces 114, e.g., formed of copper. Bond pads 110 are electrically connected to upper traces 114, e.g., bond fingers thereof, by electrically conductive bond wires 116.
Formed on lower surface 102L of substrate 102 are lower, e.g., second, traces 118. Lower traces 118 are electrically connected to upper traces 114 by electrically conductive vias 120 extending through substrate 102 between upper surface 102U and lower surface 102L. Although not illustrated in
Although a particular electrically conductive pathway between bond pads 110 and lower traces 118 is described above, other electrically conductive pathways can be formed. For example, contact metallizations can be formed between the various electrical conductors.
Further, instead of straight though vias 120, in one embodiment, substrate 102 is a multilayer substrate and a plurality of vias and/or internal traces form the electrical interconnection between upper traces 114 and lower traces 118.
In accordance with one embodiment, one or more of upper traces 114 is not electrically connected to a lower traces 118, i.e., is electrically isolated from lower traces 118, and electrically connected to bond pads 110. To illustrate, a first upper trace 114A of the plurality of upper traces 114 is electrically isolated from lower traces 118 and electrically connected to a respective bond pad 110. In accordance with this embodiment, the respective bond pad 110 electrically connected to upper trace 114A is also electrically isolated from lower traces 118.
In accordance with one embodiment, one or more of upper traces 114 is electrically connected to both bond pads 110 and to lower traces 118. To illustrate, a second upper trace 114B of the plurality of upper traces 114 is electrically connected to a respective bond pad 110 and to one or more lower traces 118. In accordance with this embodiment, the respective bond pad 110 is electrically connected to upper trace 114B and is also electrically connected to lower traces 118.
In accordance with one embodiment, one or more of upper traces 114 is not electrically connected to a bond pad 110, i.e., is electrically isolated from bond pads 110, and electrically connected to a lower trace 118. To illustrate, a third upper trace 114C of the plurality of upper traces 114 is electrically isolated from bond pads 110 and electrically connected to lower trace(s) 118. In accordance with this embodiment, the respective lower trace(s) 118 electrically connected to upper trace 114C are electrically isolated from bond pads 110.
Although various examples of connections between bond pads 110, upper traces 114, and lower traces 118 are set forth above, in light of this disclosure, those of skill in the art will understand that any one of a number of electrical configurations are possible depending upon the particular application.
Electronic component 104, bond wires 116, and the exposed portions of upper surface 102U including upper traces 114 are enclosed, sometimes called encased, encapsulated, and/or covered, with a package body 122. Illustratively, package body 122 is a cured liquid encapsulant, molding compound, or other dielectric material. Package body 122 protects electronic component 104, bond wires 116, and the exposed portions of upper surface 102U including upper traces 114 from the ambient environment, e.g., from contact, moisture and/or shorting to other structures.
Package body 122 includes a principal surface 122P parallel to upper surface 102U of substrate 102. In accordance with this embodiment, package body 122 includes sides 122S extending perpendicularly between substrate 102 and principal surface 122P. Sides 122S are parallel to and lie in the same plane as sides 102S of substrate 102. Thus, package body 122 entirely covers upper traces 114.
Illustratively, stackable protruding via package 100 is formed simultaneously with a plurality of packages in an array or strip. The array or strip is singulated resulting in sides 122S of package body 122 parallel to and lying in the same plane as sides 102S of substrate 102.
Although the terms parallel, perpendicular, and similar terms are used herein, it is to be understood that the described features may not be exactly parallel and perpendicular, but only substantially parallel and perpendicular to within excepted manufacturing tolerances.
Stackable protruding via package 100 includes protruding via apertures 124 penetrating into package body 122 from principal surface 122P. In one embodiment, protruding via apertures 124 are formed using a laser-ablation process. More particularly, a laser is repeatedly directed at principal surface 122P perpendicularly to principal surface 122P. This laser ablates, i.e., removes, portions of package body 122 leaving protruding via apertures 124, sometimes called through holes.
Although a laser-ablation process for formation of protruding via apertures 124 is set forth above, in other embodiments, other via apertures formation techniques are used. For example, protruding via apertures 124 are formed using selective molding, milling, mechanical drilling, chemical etching and/or other via aperture formation techniques.
As illustrated in
Protruding via apertures 124 taper from principal surface 122P to upper traces 114. More particularly, the diameter of protruding via apertures 124 in a plane parallel to principal surface 122P is greatest at principal surface 122P and smallest at upper traces 114 and gradually diminishes between principal surface 122P and upper traces 114.
In another embodiment, protruding via apertures 124 have a uniform diameter, i.e., have a cylindrical shape. In yet another embodiment, protruding via apertures 124 taper from upper traces 114 to principal surface 122P. More particularly, the diameter of protruding via apertures 124 in a plane parallel to principal surface 122P is smallest at principal surface 122P and greatest at upper traces 114 and gradually increases between principal surface 122P and upper traces 114.
In one embodiment, upper traces 114 include solder terminals 115 (indicated by the dashed lines, sometimes called Solder-On-Pad or SOP) formed on upper traces 114 prior to the formation of protruding via apertures 124, i.e., prior to the formation of package body 122. Package body 122 as formed thus encloses solder terminals 115.
Protruding via apertures 124 are formed to expose solder terminals 115. In accordance with this embodiment, protruding via apertures 124 extend between principal surface 122P of package body 122 and solder terminals 115 on upper traces 114, e.g., on terminals of upper traces 114. Solder terminals 115, e.g., formed of solder, reflow along with vias 126 and via extension bumps 328 as illustrated in
As illustrated in
Vias 126 extend between upper surfaces 126U and lower surfaces 126L. In accordance with this embodiment, upper surfaces 126U have a greater area than the area of lower surfaces 126L. Accordingly, vias 126 taper from upper surfaces 126U to lower surfaces 126L. More particularly, the diameter of vias 126 in a plane parallel to principal surface 122P is greatest at upper surfaces 126U and smallest at lower surfaces 126L and gradually diminish between upper surfaces 126U and lower surfaces 126L.
In another embodiment, vias 126 have a uniform diameter, i.e., have a cylindrical shape where lower surfaces 126L are equal in area to upper surfaces 126U. In yet another embodiment, vias 126 taper from lower surfaces 126L to upper surfaces 126U. More particularly, the diameter of vias 126 in a plane parallel to principal surface 122P is smallest at upper surfaces 126U and greatest at lower surface 126L and gradually increases between upper surface 126U and lower surface 126L.
In one embodiment, via extension bumps 328 are formed of solder, e.g., are solder balls, and are attached to upper surfaces 126U of vias 126 using flux or other technique. In another embodiment, via extension bumps 328 are solder paste that is screen printed on upper surfaces 126U of vias 126.
More particularly, vias 126 and via extension bumps 328, e.g., solder, are heated to melt vias 126 and via extension bumps 328. Upon melting, vias 126 and via extension bumps 328 combine into single molten structures, e.g., molten solder. These molten structures cool and form protruding vias 430. In accordance with this embodiment, protruding vias 430 are integral, i.e., are a single unitary structure and not a plurality of different layers connected together.
Protruding vias 430 extend from upper traces 114 through package body 122 and protrude above principal surface 122P of package body 122. Protruding vias 430 completely fill protruding via apertures 124 in accordance with this embodiment.
Protruding vias 430 have exposed, e.g., first, surfaces 430U and lower, e.g., second, surfaces 430L. Exposed surfaces 430U protrude above, outward from, and beyond principal surface 122P, i.e., the plane defined thereby, of package body 122. Exposed surfaces 430U are curved and protrude outward from principal surface 122P in a convex shape. Lower surfaces 430L are parallel to and lies in the same plane as upper traces 114.
Protruding vias 430 extend between exposed surfaces 430U and lower surfaces 430L. In accordance with this embodiment, protruding vias 430 taper from exposed surfaces 430U to lower surfaces 430L. More particularly, the diameter of protruding vias 430 in a plane parallel to principal surface 122P is greatest at principal surface 122P and smallest at lower surfaces 430L and gradually diminish between principal surface 122P and lower surfaces 430L.
In another embodiment, protruding vias 430 have a uniform diameter, except for the portion of protruding vias 430 that protrude beyond principal surface 122P. In yet another embodiment, protruding vias 430 taper from lower surfaces 430L to exposed surfaces 430U. More particularly, the diameter of protruding vias 430 in a plane parallel to principal surface 122P is greatest at lower surfaces 430L and gradually decreases between lower surface 430L and principal surface 122P.
Protruding vias 430 are electrically connected to upper traces 114. As set forth above, in accordance with various embodiments, upper traces 114 are electrically connected to lower traces 118, to bond pads 110, and/or to lower traces 118 and bond pads 110. Thus, in accordance with various embodiments, at least some of protruding vias 430 are electrically connected to lower traces 118 only, to bond pads 110 only, and/or to both lower traces 118 and bond pads 110.
Protruding vias 430 extend from upper surface 102U of substrate 102 to a height H1 greater than a height H2 of principal surface 122P of package body 122 from upper surface 102U of substrate 102. This allows electrical connection of stackable protruding via package 100 to a larger substrate such as a printed circuit motherboard as discussed in greater detail below with reference to
As illustrated in
In another embodiment, terminals 534 are formed without interconnection paste 538. In accordance with this embodiment, assembly 500 is heated to reflow protruding vias 430 thereby physically and electrically connecting protruding vias 430 to terminals 534, which are formed by lands 536.
Referring now to
In one embodiment, second electronic component 604 is an integrated circuit chip, e.g., an active component. However, in other embodiments, second electronic component 604 is a passive component such as a capacitor, resistor, or inductor.
In accordance with this embodiment, second electronic component 604 includes an active surface 606 and an opposite inactive surface 608. Second electronic component 604 further includes bond pads 610 formed on active surface 606. Inactive surface 608 is mounted to active surface 106 of electronic component 104 with an adhesive 612, sometimes called a die attach adhesive. Bond pads 610 are electrically connected to upper traces 114 by electrically conductive bond wires 616.
As illustrated in
Referring now to
As also illustrated in
Referring now to
As also illustrated in
Stackable protruding via package 700 further includes a passive component 744, e.g., a capacitor, resistor, or inductor. Passive component 744 includes terminals 746 mounted to upper traces 114 with solder joints 748.
Passive component 744, solder joints 748, electronic component 104, flip chip bumps 740, and underfill 742 are encloses within package body 122.
Referring now to
In one embodiment, second electronic component 804 is an integrated circuit chip, e.g., an active component. However, in other embodiments, second electronic component 804 is a passive component such as a capacitor, resistor, or inductor.
In accordance with this embodiment, second electronic component 804 includes an active surface 806 and an opposite inactive surface 808. Second electronic component 804 further includes bond pads 810 formed on active surface 806. Inactive surface 808 is mounted to inactive surface 108 of electronic component 104 with an adhesive 812, sometimes called a die attach adhesive. Bond pads 810 are electrically connected to upper traces 114 by electrically conductive bond wires 816.
Package body 122 further encloses second electronic component 804 and bond wires 816.
For example, second package 901 is a memory package that is stacked on stackable protruding via package 100 for use in a digital still camera application. By stacking second package 901 on stackable protruding via package 100, the area occupied by stacked protruding via package 900 on the larger substrate is minimized as compared to mounting second package 901 and stackable protruding via package 100 to the larger substrate in a side by side arrangement.
Second package 901 of
In accordance with this embodiment, second package 901 is mounted to stackable protruding via package 100 with interconnection balls 950, e.g., solder. In one embodiment, interconnection balls 950 are formed on lower traces 118 (which are orientated upwards in the view of
As set forth above, lower traces 118 are electrically coupled to protruding vias 430, bond pads 110, and/or both protruding vias 430 and bond pads 110. Accordingly, lower traces 918, e.g., terminals thereof, are electrically connected to protruding vias 430, bond pads 110, and/or both protruding vias 430 and bond pads 110.
Although a particular second package 901 is set forth, in light of this disclosure, those of skill in the art will understand that any one of a number of electronic components and/or electronic component packages can be stacked on stackable protruding via package 100 in a similar manner. An example of another configuration of stacking of electronic components and electronic component packages on stackable protruding via package 100 is set forth below in reference to
Second package 1052 of
In accordance with this embodiment, second package 1052 is mounted to stackable protruding via package 100 with interconnection balls 1050, e.g., solder. Interconnection balls 1050 extend between lower traces 118 (which are orientated upwards in the view of
As set forth above, lower traces 118 are electrically coupled to protruding vias 430, bond pads 110, and/or both protruding vias 430 and bond pads 110. Accordingly, lower traces 1018A, e.g., terminals thereof, are electrically connected to protruding vias 430, bond pads 110, and/or both protruding vias 430 and bond pads 110.
Third package 1054 of
In accordance with this embodiment, third package 1054 is mounted to stackable protruding via package 100 with interconnection balls 1050, e.g., solder. Interconnection balls 1050 extend between lower traces 118 of stackable protruding via package 100 and lower traces 1018B of third package 1054.
As set forth above, lower traces 118 are electrically coupled to protruding vias 430, bond pads 110, and/or both protruding vias 430 and bond pads 110. Accordingly, lower traces 1018B, e.g., terminals thereof, are electrically connected to protruding vias 430, bond pads 110, and/or both protruding vias 430 and bond pads 110.
Passive component 1056, e.g., a capacitor, resistor, or inductor, includes terminals 1046 mounted to lower traces 118 with solder joints 1048. As set forth above, lower traces 118 are electrically coupled to protruding vias 430, bond pads 110, and/or both protruding vias 430 and bond pads 110. Accordingly, terminals 1046 of passive component 1056 are electrically connected to protruding vias 430, bond pads 110, and/or both protruding vias 430 and bond pads 110.
In stacked protruding via packages 900, 1000 of
In another embodiment, a triple stacked module, sometimes called a stacked protruding via package, is formed. For example, using two or more stackable protruding via packages similar to stackable protruding via packages 100, 600, 600A, 700, 800 of
The drawings and the forgoing description gave examples of the present invention. The scope of the present invention, however, is by no means limited by these specific examples. Numerous variations, whether explicitly given in the specification or not, such as differences in structure, dimension, and use of material, are possible. The scope of the invention is at least as broad as given by the following claims.
Number | Name | Date | Kind |
---|---|---|---|
3868724 | Perrino | Feb 1975 | A |
3916434 | Garboushian | Oct 1975 | A |
4322778 | Barbour et al. | Mar 1982 | A |
4532419 | Takeda | Jul 1985 | A |
4642160 | Burgess | Feb 1987 | A |
4645552 | Vitriol et al. | Feb 1987 | A |
4685033 | Inoue | Aug 1987 | A |
4706167 | Sullivan | Nov 1987 | A |
4716049 | Patraw | Dec 1987 | A |
4786952 | MacIver et al. | Nov 1988 | A |
4806188 | Rellick | Feb 1989 | A |
4811082 | Jacobs et al. | Mar 1989 | A |
4897338 | Spicciati et al. | Jan 1990 | A |
4905124 | Banjo et al. | Feb 1990 | A |
4964212 | Deroux-Dauphin et al. | Oct 1990 | A |
4974120 | Kodai et al. | Nov 1990 | A |
4996391 | Schmidt | Feb 1991 | A |
5021047 | Movern | Jun 1991 | A |
5072075 | Lee et al. | Dec 1991 | A |
5072520 | Nelson | Dec 1991 | A |
5081520 | Yoshii et al. | Jan 1992 | A |
5091769 | Eichelberger | Feb 1992 | A |
5108553 | Foster et al. | Apr 1992 | A |
5110664 | Nakanishi et al. | May 1992 | A |
5191174 | Chang et al. | Mar 1993 | A |
5229550 | Bindra et al. | Jul 1993 | A |
5239448 | Perkins et al. | Aug 1993 | A |
5247429 | Iwase et al. | Sep 1993 | A |
5250843 | Eichelberger | Oct 1993 | A |
5278726 | Bernardoni et al. | Jan 1994 | A |
5283459 | Hirano et al. | Feb 1994 | A |
5353498 | Fillion et al. | Oct 1994 | A |
5371654 | Beaman et al. | Dec 1994 | A |
5379191 | Carey et al. | Jan 1995 | A |
5404044 | Booth et al. | Apr 1995 | A |
5463253 | Waki et al. | Oct 1995 | A |
5474957 | Urushima | Dec 1995 | A |
5474958 | Djennas et al. | Dec 1995 | A |
5497033 | Fillion et al. | Mar 1996 | A |
5508938 | Wheeler | Apr 1996 | A |
5530288 | Stone | Jun 1996 | A |
5531020 | Durand et al. | Jul 1996 | A |
5546654 | Wojnarowski et al. | Aug 1996 | A |
5574309 | Papapietro et al. | Nov 1996 | A |
5581498 | Ludwig et al. | Dec 1996 | A |
5582858 | Adamopoulos et al. | Dec 1996 | A |
5616422 | Ballard et al. | Apr 1997 | A |
5637832 | Danner | Jun 1997 | A |
5674785 | Akram et al. | Oct 1997 | A |
5719749 | Stopperan | Feb 1998 | A |
5726493 | Yamashita et al. | Mar 1998 | A |
5739581 | Chillara | Apr 1998 | A |
5739585 | Akram et al. | Apr 1998 | A |
5739588 | Ishida et al. | Apr 1998 | A |
5742479 | Asakura | Apr 1998 | A |
5774340 | Chang et al. | Jun 1998 | A |
5784259 | Asakura | Jul 1998 | A |
5798014 | Weber | Aug 1998 | A |
5822190 | Iwasaki | Oct 1998 | A |
5826330 | Isoda et al. | Oct 1998 | A |
5835355 | Dordi | Nov 1998 | A |
5847453 | Uematsu et al. | Dec 1998 | A |
5883425 | Kobayashi | Mar 1999 | A |
5894108 | Mostafazadeh et al. | Apr 1999 | A |
5903052 | Chen et al. | May 1999 | A |
5907477 | Tuttle et al. | May 1999 | A |
5936843 | Ohshima et al. | Aug 1999 | A |
5952611 | Eng et al. | Sep 1999 | A |
6004619 | Dippon et al. | Dec 1999 | A |
6013948 | Akram et al. | Jan 2000 | A |
6021564 | Hanson | Feb 2000 | A |
6028364 | Ogino et al. | Feb 2000 | A |
6034427 | Lan et al. | Mar 2000 | A |
6035527 | Tamm | Mar 2000 | A |
6040622 | Wallace | Mar 2000 | A |
6060778 | Jeong et al. | May 2000 | A |
6069407 | Hamzehdoost | May 2000 | A |
6072243 | Nakanishi | Jun 2000 | A |
6081036 | Hirano et al. | Jun 2000 | A |
6119338 | Wang et al. | Sep 2000 | A |
6122171 | Akram et al. | Sep 2000 | A |
6127833 | Wu et al. | Oct 2000 | A |
6160705 | Stearns et al. | Dec 2000 | A |
6172419 | Kinsman | Jan 2001 | B1 |
6175087 | Keesler et al. | Jan 2001 | B1 |
6184463 | Panchou et al. | Feb 2001 | B1 |
6194250 | Melton et al. | Feb 2001 | B1 |
6204453 | Fallon et al. | Mar 2001 | B1 |
6214641 | Akram | Apr 2001 | B1 |
6235554 | Akram et al. | May 2001 | B1 |
6239485 | Peters et al. | May 2001 | B1 |
D445096 | Wallace | Jul 2001 | S |
D446525 | Okamoto et al. | Aug 2001 | S |
6274821 | Echigo et al. | Aug 2001 | B1 |
6280641 | Gaku et al. | Aug 2001 | B1 |
6316285 | Jiang et al. | Nov 2001 | B1 |
6351031 | Iijima et al. | Feb 2002 | B1 |
6353999 | Cheng | Mar 2002 | B1 |
6365975 | DiStefano et al. | Apr 2002 | B1 |
6376906 | Asai et al. | Apr 2002 | B1 |
6392160 | Andry et al. | May 2002 | B1 |
6395578 | Shin et al. | May 2002 | B1 |
6405431 | Shin et al. | Jun 2002 | B1 |
6406942 | Honda | Jun 2002 | B2 |
6407341 | Anstrom et al. | Jun 2002 | B1 |
6407930 | Hsu | Jun 2002 | B1 |
6448510 | Neftin et al. | Sep 2002 | B1 |
6451509 | Keesler et al. | Sep 2002 | B2 |
6479762 | Kusaka | Nov 2002 | B2 |
6497943 | Jimarez et al. | Dec 2002 | B1 |
6517995 | Jacobson et al. | Feb 2003 | B1 |
6534391 | Huemoeller et al. | Mar 2003 | B1 |
6544638 | Fischer et al. | Apr 2003 | B2 |
6586682 | Strandberg | Jul 2003 | B2 |
6608757 | Bhatt et al. | Aug 2003 | B1 |
6660559 | Huemoeller et al. | Dec 2003 | B1 |
6715204 | Tsukada et al. | Apr 2004 | B1 |
6727645 | Tsujimura et al. | Apr 2004 | B2 |
6730857 | Konrad et al. | May 2004 | B2 |
6734542 | Nakatani et al. | May 2004 | B2 |
6740964 | Sasaki | May 2004 | B2 |
6753612 | Adae-Amoakoh et al. | Jun 2004 | B2 |
6774748 | Ito et al. | Aug 2004 | B1 |
6787443 | Boggs et al. | Sep 2004 | B1 |
6803528 | Koyanagi | Oct 2004 | B1 |
6815709 | Clothier et al. | Nov 2004 | B2 |
6815739 | Huff et al. | Nov 2004 | B2 |
6838776 | Leal et al. | Jan 2005 | B2 |
6888240 | Towle et al. | May 2005 | B2 |
6919514 | Konrad et al. | Jul 2005 | B2 |
6921968 | Chung | Jul 2005 | B2 |
6921975 | Leal et al. | Jul 2005 | B2 |
6931726 | Boyko et al. | Aug 2005 | B2 |
6953995 | Farnworth et al. | Oct 2005 | B2 |
7015075 | Fay et al. | Mar 2006 | B2 |
7030469 | Mahadevan et al. | Apr 2006 | B2 |
7081661 | Takehara et al. | Jul 2006 | B2 |
7125744 | Takehara et al. | Oct 2006 | B2 |
7185426 | Hiner et al. | Mar 2007 | B1 |
7198980 | Jiang et al. | Apr 2007 | B2 |
7242081 | Lee | Jul 2007 | B1 |
7282394 | Cho et al. | Oct 2007 | B2 |
7285855 | Foong | Oct 2007 | B2 |
7345361 | Mallik et al. | Mar 2008 | B2 |
7372151 | Fan et al. | May 2008 | B1 |
7429786 | Karnezos et al. | Sep 2008 | B2 |
7459202 | Magera et al. | Dec 2008 | B2 |
7548430 | Huemoeller et al. | Jun 2009 | B1 |
7550857 | Longo et al. | Jun 2009 | B1 |
20020017712 | Bessho et al. | Feb 2002 | A1 |
20020061642 | Haji et al. | May 2002 | A1 |
20020066952 | Taniguchi et al. | Jun 2002 | A1 |
20020195697 | Mess et al. | Dec 2002 | A1 |
20030025199 | Wu et al. | Feb 2003 | A1 |
20030128096 | Mazzochette | Jul 2003 | A1 |
20030141582 | Yang et al. | Jul 2003 | A1 |
20030197284 | Khiang et al. | Oct 2003 | A1 |
20040063246 | Karnezos | Apr 2004 | A1 |
20040145044 | Sugaya et al. | Jul 2004 | A1 |
20040159462 | Chung | Aug 2004 | A1 |
20050139985 | Takahashi | Jun 2005 | A1 |
20050242425 | Leal et al. | Nov 2005 | A1 |
20070273049 | Khan et al. | Nov 2007 | A1 |
20070281471 | Hurwitz et al. | Dec 2007 | A1 |
20070290376 | Zhao et al. | Dec 2007 | A1 |
20080230887 | Sun et al. | Sep 2008 | A1 |
Number | Date | Country |
---|---|---|
05-109975 | Apr 1993 | JP |
05-136323 | Jun 1993 | JP |
07-017175 | Jan 1995 | JP |
08-190615 | Jul 1996 | JP |
10-334205 | Dec 1998 | JP |
Entry |
---|
IBM Technical Disclosure Bulletin, “Microstructure Solder Mask by Means of a Laser”, vol. 36, Issue 11, p. 589, Nov. 1, 1993. (NN9311589). |
Kim et al., “Application of Through Mold Via (TMV) as PoP base package”, 58th ECTC Proceedings, May 2008, Lake Buena Vista, FL, 6 pages, IEEE. |
Scanlan, “Package-on-package (PoP) with Through-mold Vias”, Advanced Packaging, Jan. 2008, 3 pages, vol. 17, Issue 1, PennWell Corporation. |
Hiner et al., “Printed Wiring Motherboard Having Bonded Interconnect Redistribution Mesa”, U.S. Appl. No. 10/992,371, filed Nov. 18, 2004. |
Scanlan et al., “Semiconductor Package Including a Top-Surface Metal Layer for Implementing Circuit Features”, U.S. Appl. No. 11/293,999, filed Dec. 5, 2005. |
Hiner et al., “Semiconductor Package Including Top-Surface Terminals for Mounting Another Semiconductor Package”, U.S. Appl. No. 11/595,411, filed Nov. 9, 2006. |
Huemoeller et al., “Build Up Motherboard Fabrication Method and Structure”, U.S. Appl. No. 11/824,395, filed Jun. 29, 2007. |
Berry et al., “Thin Stacked Interposer Package”, U.S. Appl. No. 11/865,617, filed Oct. 1, 2007. |
Longo et al., “Stacked Redistribution Layer (RDL) Die Assembly Package”, U.S. Appl. No. 12/387,672, filed May 5, 2009. |
Huemoeller et al., “Buildup Dielectric Layer Having Metallization Pattern Semiconductor Package Fabrication Method”, U.S. Appl. No. 12/387,691, filed May 5, 2009. |
Miller, Jr. et al., “Thermal Via Heat Spreader Package and Method”, U.S. Appl. No. 12/421,118, filed Apr. 9, 2009. |