1. Field of the Invention
The present application relates to the field of electronics, and more particularly, to methods of forming electronic component packages and related structures.
2. Description of the Related Art
To form an electronic component package, an electronic component is mounted to a substrate. The substrate includes traces on the same surface of the substrate to which the electronic component is mounted. Bond wires are formed to electrically connect bond pads of the electronic component to the traces.
To protect the electronic component as well as the bond wires, the electronic component and bond wires are covered in an encapsulant. The traces extend from under the encapsulant to an exposed area of the surface of the substrate outside of the periphery of the encapsulant, i.e., not covered by the encapsulant. The traces include terminals on the exposed area of the substrate outside of and around the encapsulant.
Solder balls are formed on the terminals. These solder balls extend from the substrate to a height greater than the height of the encapsulant to allow the solder balls to be electrically connected to a larger substrate such as a printed circuit motherboard.
However, the solder balls are substantially spherical in shape. Thus, forming the solder balls with a height greater than the height of the encapsulant places fundamental restrictions on minimizing the pitch of the solder balls.
In accordance with one embodiment, a stackable variable height via package includes a substrate having a first surface and terminals thereon. The terminals include a first terminal and a second terminal. Vias are on the terminals, the vias including a first via on the first terminal and a second via on the second terminal. The first via has a height from the first surface of the substrate less than a height of the second via from the first surface of the substrate. The package further includes a package body and via apertures in the package body to expose the vias.
Forming the stackable variable height via package with variable height vias readily accommodate stacking of additional packages having different types of terminals, e.g., LGA and BGA type packages, as well as variable degrees of warpage on the stackable variable height via package. Further, the vias are formed with a minimum pitch.
These and other features of the present invention will be more readily apparent from the detailed description set forth below taken in conjunction with the accompanying drawings.
In the following description, the same or similar elements are labeled with the same or similar reference numbers.
As an overview and in accordance with one embodiment, referring to
Forming stackable variable height via package 1300 with variable height vias 220, 222 readily accommodate stacking of additional packages having different types of terminals (for example, see LGA and BGA type packages 1554, 1560A, 1560B of
Now in more detail,
Referring now to
Formed on upper surface 102U of substrate 102 are electrically conductive upper terminals 104, e.g., formed of copper. Terminals 104 include a first terminal 104A and a second terminal 104B. Terminals 104 are electrically connected to electrically conductive upper, e.g., first, traces 106 on upper surface 102U in one embodiment.
In accordance with this embodiment, terminals 104 are essentially identical. More particularly, terminal 104A and terminal 104B have an equal width W1 in the direction parallel to upper surface 102U of substrate 102. In one embodiment, terminal 104A and terminal 104B have an equal surface area when viewed from above, i.e., from a direction perpendicular to upper surface 102U of substrate 102, as illustrated in
Although the terms parallel, perpendicular, and similar terms are used herein, it is to be understood that the described features may not be exactly parallel and perpendicular, but only substantially parallel and perpendicular to within excepted manufacturing tolerances.
Stackable variable height via package 100 further includes a solder mask 108, i.e., formed of a dielectric material. Solder mask 108 is patterned to form terminal openings 110 above respective terminals 104. In accordance with this embodiment, terminal openings 110 include a first terminal opening 110A above terminal 104A and a second terminal opening 110B above terminal 104B.
Terminal openings 110 have a width W2 less than width W1 of terminals 104. Accordingly, an exposed portion 112A of terminal 104A is exposed through terminal opening 110A and a covered portion 114A of terminal 104A is covered by solder mask 108. Similarly, an exposed portion 112B of terminal 104B is exposed through terminal opening 110B and a covered portion 114B of terminal 104B is covered by solder mask 108. Exposed portions 112A, 112B and covered portions 114A, 114B are collectively referred to as exposed portions 112 and covered portions 114 of terminals 104.
In one embodiment, exposed portions 112 are the central regions of terminals 104 and covered portions 114 are the peripheral regions of terminals 104. Illustratively, terminals 104 and terminal openings 110 are circular when viewed from above as illustrated in
In accordance with this embodiment, terminals 104 have a diameter equal to width W1. Further, terminal openings 110 have a diameter equal to width W2. Terminals 104 and upper traces 106 are illustrated in dashed lines in
Referring now to
In one embodiment, solder balls 116, 118 are formed of solder, i.e., are formed completely and only of solder. In another embodiment, solder balls 116, 118 are polymer core solder balls, i.e., are formed of a polymer core surrounded by solder.
Solder ball 116 has a smaller volume than solder ball 118 in accordance with this embodiment. More particularly, solder balls 116, 118 are approximate spherical. Solder ball 116 has a first diameter D1 less than a second diameter D2 of solder ball 118.
As SMD lands 112A, 112B have an equal surface area in accordance with this embodiment, the greater volume of solder ball 118 spread over SMD land 112B causes via 222 to extend higher from upper surface 102U than via 220 formed from solder ball 116 spread over SMD land 112A. More particularly, via 220 has a height H1 from upper surface 102U of substrate 102 less than a height H2 of via 222 from upper surface 102U of substrate 102.
As discussed in greater detail below, forming stackable variable height via package 100 with variable height vias, i.e., vias 220, 222, readily accommodate stacking of additional packages having different types of terminals, e.g., land grid array (LGA) and ball grid array (BGA) type packages, as well as variable degrees of warpage on stackable variable height via package 100. Further, vias 220, 222 are formed with a minimum pitch.
Referring now to
After formation of package body 224, via apertures 226 are formed in package body 224 to expose respective vias 220, 222.
In one embodiment, via apertures 226 are formed using a laser-ablation process. More particularly, a laser is repeatedly directed at principal surface 224P perpendicularly to principal surface 224P. This laser ablates, i.e., removes, portions of package body 224 leaving via apertures 226, sometimes called through holes.
Although a laser-ablation process for formation of via apertures 226 is set forth above, in other embodiments, other via aperture formation techniques are used. For example, via apertures 226 are formed using selective molding, milling, mechanical drilling, chemical etching and/or other via aperture formation techniques.
As illustrated in
Via apertures 226 taper from principal surface 124P to vias 220, 222. More particularly, the diameter of via apertures 226 in a plane parallel to principal surface 224P is greatest at the tops of via apertures 226, and smallest at the bottoms of via apertures 226 and gradually diminishes between the tops and bottoms of via apertures 226. The tops of via apertures 230 are located at principal surface 224P and the bottoms of via apertures 226 are located between principal surface 224P of package body 224 and upper surface 102U of substrate 102, i.e., at vias 220, 222, in this embodiment.
In another embodiment, via apertures 226 have a uniform diameter, i.e., have a cylindrical shape. In yet another embodiment, via apertures 226 taper from the bottoms to the tops of via aperture 226. More particularly, the diameter of via apertures 226 in a plane parallel to principal surface 224P is smallest at the tops of via apertures 226 and greatest at the bottoms of via apertures 226 and gradually increases between the tops and bottoms of via apertures 226.
Referring now to
Further, solder balls 116A, 116B are attached to SMD lands 112A, 112C, i.e., exposed portions 112A, 112C of terminals 104A, 104B. In accordance with this embodiment, solder balls 116A, 116B have equal volume and are essentially identical. More particularly, solder balls 116A, 116B are approximate spherical and have first diameter D1.
More particularly, solder ball 116A is spread over SMD land 112A and solder ball 116B is spread over SMD land 112C. As SMD land 112A has a greater surface area than SMD land 112C and solder balls 116A, 116B have an equal volume in accordance with this embodiment, via 422 extends higher from upper surface 102U of substrate 102 than via 220.
More particularly, via 220 has height H1 from upper surface 102U of substrate 102 less than a height H3 of via 422 from upper surface 102U of substrate 102. As discussed in greater detail below, forming stackable variable height via package 300 with variable height vias, e.g., vias 220, 422, readily accommodates stacking of additional packages having different types of terminals, e.g., LGA and BGA type packages, as well as variable degrees of warpage on stackable variable height via package 300.
Referring now to
After formation of package body 224, via apertures 226 are formed in package body 224 to expose respective vias 220, 422.
Referring now to
As upper surface 102U of substrate 102 is non-wettable with solder, terminal 104A including upper surface 104U and sides 104S defines the land. Stated another way, exposed portion 112D is upper surface 104U and sides 104S of terminal 104A. In accordance with this embodiment, exposed portion 112D is sometimes called a Non Solder Mask Defined (NSMD) land 112D.
Further, exposed portion 112B of terminal 104B exposed through terminal opening 110B is smaller, i.e., has a smaller surface area, than exposed portion 112D.
Further, solder balls 116A, 116B are attached to NSMD land 112D and SMD land 112B. In accordance with this embodiment, solder balls 116A, 116B have equal volume and are essentially identical. More particularly, solder balls 116A, 116B are approximate spherical and have first diameter D1.
More particularly, solder ball 116A is spread over NSMD land 112D including upper surface 104U and sides 104S of terminal 104A, and solder ball 116B is spread over SMD land 112B. As NSMD land 112D (upper surface 104U and sides 104S combined) has a greater surface area than SMD land 112B and solder balls 116A, 116B have equal volume in accordance with this embodiment, via 622 extends higher from upper surface 102U than via 620A. More particularly, via 620A has a height H4 from upper surface 102U of substrate 102 less than a height H5 of via 622 from upper surface 102U of substrate 102. As discussed in greater detail below, forming stackable variable height via package 500A with variable height vias, e.g., vias 620A, 622, readily accommodates stacking of additional packages having different types of terminals, e.g., LGA and BGA type packages, as well as variable degrees of warpage on stackable variable height via package 500A. Further, vias 620A, 622 are formed with minimum pitch.
Referring now to
After formation of package body 224, via apertures 226 are formed in package body 224 to expose respective vias 620A, 622.
Referring now to
As upper surface 102U of substrate 102 is non-wettable with solder, terminal 104A including upper surface 104U and sides 104S defines the land. Stated another way, exposed portion 112D is upper surface 104U and sides 104S of terminal 104A. In accordance with this embodiment, exposed portion 112D is sometimes called a Non Solder Mask Defined (NSMD) land 112D.
Further, upper surface 104U of terminal 104A is equal to exposed portion 112B of terminal 104B. However, considering that sides 104S of terminal 104A are also exposed, the solder wettable area of NSMD land 112D is greater than the solder wettable area of SMD land 112B.
Further, solder balls 116A, 116B are attached to NSMD land 112D and SMD land 112B. In accordance with this embodiment, solder balls 116A, 116B have equal volume and are essentially identical. More particularly, solder balls 116A, 116B are approximate spherical and have first diameter D1.
More particularly, solder ball 116A is spread over NSMD land 112D including upper surface 104U and sides 104S of terminal 104A, and solder ball 116B is spread over SMD land 112B. As NSMD land 112D (upper surface 104U and sides 104S combined) has a greater surface area than SMD land 112B and solder balls 116A, 116B have equal volume in accordance with this embodiment, via 622 extends higher from upper surface 102U than via 620B. More particularly, via 620B has a height H4B from upper surface 102U of substrate 102 less than a height H5 of via 622 from upper surface 102U of substrate 102. As discussed in greater detail below, forming stackable variable height via package 500B with variable height vias, e.g., vias 620B, 622, readily accommodates stacking of additional packages having different types of terminals, e.g., LGA and BGA type packages as well as variable degrees of warpage on stackable variable height via package 500B. Further, vias 620B, 622 are formed with minimum pitch.
Referring now to
After formation of package body 224, via apertures 226 are formed in package body 224 to expose respective vias 620B, 622.
In accordance with this embodiment, stackable variable height via package 700 is formed without solder mask 108 (see
As upper surface 102U of substrate 102 is non-wettable with solder, terminals 104A, 104B including upper surfaces 104U and sides 104S define the lands. Stated another way, exposed portions 112D, 112E are upper surfaces 104U and sides 104S of terminals 104A, 104B. In accordance with this embodiment, exposed portions 112D, 112E are sometimes called Non Solder Mask Defined (NSMD) lands 112D, 112E, respectively. Both NSMD lands 112D, 112E have an equal width W1 and thus have an equal surface area.
Further, solder balls 116, 118 are attached to NSMD lands 112D, 112E. Solder ball 116 has a smaller volume than solder ball 118 in accordance with this embodiment. More particularly, solder balls 116, 118 are approximate spherical. Solder ball 116 has first diameter D1 less than second diameter D2 of solder ball 118.
As NSMD lands 112D, 112E have an equal surface area in accordance with this embodiment, the greater volume of solder ball 118 spread over NSMD land 112E causes via 822 to extend higher from upper surface 102U than via 620A formed from solder ball 116 spread over NSMD land 112D. More particularly, via 620A has height H4 from upper surface 102U of substrate 102 less than a height H6 of via 822 from upper surface 102U of substrate 102. As discussed in greater detail below, forming stackable variable height via package 700 with variable height vias, e.g., vias 620A, 822, readily accommodate stacking of additional packages having different types of terminals, e.g., LGA and BGA type packages, as well as variable degrees of warpage on stackable variable height via package 700. Further, vias 620A, 822 are formed with a minimum pitch.
Referring now to
After formation of package body 224, via apertures 226 are formed in package body 224 to expose respective vias 620A, 822.
In accordance with this embodiment, stackable variable height via package 900 is formed without solder mask 108 (see
As upper surface 102U of substrate 102 is non-wettable with solder, terminals 104A, 104C including upper surfaces 104U and sides 104S define the lands. Stated another way, exposed portions 112D, 112F are upper surfaces 104U and sides 104S of terminals 104A, 104C. In accordance with this embodiment, exposed portions 112D, 112F are sometimes called Non Solder Mask Defined (NSMD) lands 112D, 112F, respectively.
NSMD lands 112D, 112F, i.e., terminals 104A, 104C, are formed with various widths W1, W5. More particularly, NSMD land 112F has width W5 less than width W1 of NSMD land 112D. Accordingly, NSMD land 112F is smaller, i.e., has a smaller surface area, than NSMD land 112D.
Further, solder balls 116A, 116B are attached to NSMD lands 112D, 112F, respectively. In accordance with this embodiment, solder balls 116A, 116B have equal volume and are essentially identical. More particularly, solder balls 116A, 116B are approximate spherical and have first diameter D1.
More particularly, solder ball 116A is spread over NSMD land 112D and solder ball 116B is spread over NSMD land 112F. As NSMD land 112D has a greater surface area than NSMD land 112F and solder balls 116A, 116B have equal volume in accordance with this embodiment, via 1022 extends higher from upper surface 102U than via 620A. More particularly, via 620A has height H4 from upper surface 102U of substrate 102 less than a height H7 of via 1022 from upper surface 102U of substrate 102. As discussed in greater detail below, forming stackable variable height via package 900 with variable height vias, e.g., vias 620A, 1022, readily accommodates stacking of additional packages having different types of terminals, e.g., LGA and BGA type packages, as well as variable degrees of warpage on stackable variable height via package 900.
Referring now to
After formation of package body 224, via apertures 226 are formed in package body 224 to expose respective vias 620A, 1022.
In accordance with this embodiment, vias 220, 220A formed on SMD lands 112A, 112B are identical and have a same height H1 from upper surface 102U of substrate 102. For example, instead of having different volume solder balls 116, 118 as illustrated in
Referring now to
Protruding via 1230 extends higher from upper surface 102U than via 220. More particularly, protruding via 1230 has a height H8 from upper surface 102U of substrate 102 greater than height H1 of via 220 from upper surface 102U of substrate 102. As discussed in greater detail below, forming stackable variable height via package 1100 with variable height vias, e.g., vias 220, 1230, readily accommodates stacking of additional packages having different types of terminals, e.g., LGA and BGA type packages, as well as variable degrees of warpage on stackable variable height via package 1100. Further, vias 220, 1230 are formed with a minimum pitch.
Further, height H8 of protruding via 1230 is also greater than a height H9 of principal surface 224P of package body 224 from upper surface 102U of substrate 102. Accordingly, protruding via 1230 protrudes outward beyond (above) principal surface 224P of package body 224. In contrast, height H1 of via 220 is less than height H9 of principal surface 224P such that via 220 is recessed below principal surface 224P.
Although buildup of via 220A is discussed in relation to
Further, although stackable variable height via packages 100, 300, 500A, 500B, 700, 900, 1100 are discuss and illustrated as including vias 220, 222 (
Referring now to
In accordance with this embodiment, electronic component 1432 includes an active surface 1434 and an opposite inactive surface 1436. Electronic component 1432 further includes bond pads 1438 formed on active surface 1434. Inactive surface 1436 is mounted to upper surface 102U of substrate 102 with an adhesive 1440, sometimes called a die attach adhesive.
Although electronic component 1432 is illustrated and described as being mounted to upper surface 102U of substrate 102 in a wirebond configuration, in other embodiments, electronic component 1432 is mounted to upper surface 102U of substrate 102 in a different configuration such as a flip chip configuration such as that illustrated in
Formed on upper surface 102U of substrate 102 are electrically conductive upper, e.g., first, traces 106, e.g., formed of copper. Bond pads 1438 are electrically connected to upper traces 106, e.g., bond fingers thereof, by electrically conductive bond wires 1442.
Formed on lower surface 102L of substrate 102 are lower, e.g., second, traces 1444. Lower traces 1444 are electrically connected to upper traces 106 by electrically conductive substrate vias 1446 extending through substrate 102 between upper surface 102U and lower surface 102L.
Formed on lower traces 1444 are pads 1448, e.g., lands. Formed on pads 1448 are interconnection balls 1450, e.g., solder balls in a BGA format. Although not illustrated in
Although a particular electrically conductive pathway between bond pads 1438 and interconnection balls 1450 is described above, other electrically conductive pathways can be formed. For example, contact metallizations can be formed between the various electrical conductors.
Further, instead of straight though substrate vias 1446, in one embodiment, substrate 102 is a multilayer substrate and a plurality of substrate vias and/or internal traces form the electrical interconnection between upper traces 106 and lower traces 1444.
In accordance with one embodiment, one or more of upper traces 106 is not electrically connected to lower traces 1444, i.e., is electrically isolated from lower traces 1444, and electrically connected to bond pads 1438. To illustrate, a first upper trace 106A of the plurality of upper traces 106 is electrically isolated from lower traces 1444 and electrically connected to a respective bond pad 1438. In accordance with this embodiment, the respective bond pad 1438 electrically connected to upper trace 106A is also electrically isolated from lower traces 1444.
In accordance with one embodiment, one or more of upper traces 106 is electrically connected to both bond pads 1438 and to lower traces 1444. To illustrate, instead of being electrically isolated from lower traces 1444, upper trace 106A is electrically connected to lower traces 1444 by a substrate via 1446A of the plurality of substrate vias 1446. In accordance with this embodiment, the respective bond pad 1438 is electrically connected to upper trace 106A and is also electrically connected to lower traces 1444.
Substrate via 1446A is indicated by dashed lines to signify that formation of substrate via 1446A is optional. If substrate via 1446A is not formed, upper trace 106A is electrically isolated from lower traces 1444. Conversely, if substrate via 1446A is formed, upper trace 106A is electrically connected to lower traces 1444.
In accordance with one embodiment, one or more of upper traces 106 is not electrically connected to a bond pad 1438, i.e., is electrically isolated from bond pads 1438, and is electrically connected to lower traces 1444. To illustrate, the upper trace 106 to the far left of electronic component 1432 in the view of
Although various examples of connections between bond pads 1438, upper traces 106, and lower traces 1444 are set forth above, in light of this disclosure, those of skill in the art will understand that any one of a number of electrical configurations are possible depending upon the particular application.
Upper traces 106 are electrically connected to terminals 104 on upper surface 102U of substrate 102. Variable height vias 220, 222 are formed on terminals 104. Although stackable variable height via package 1300 is discuss and illustrated as including vias 220, 222, in light of this disclosure, those of skill in the art will understand that a stackable variable height via package in accordance with various embodiments is fabricated with one or more of vias 220, 222, 422, 620A, 620B, 622, 822, 1022, 1230, and/or combinations thereof as described above.
As set forth above, in accordance with various embodiments, upper traces 106 are electrically connected to lower traces 1444, to bond pads 1438, and/or to lower traces 1444 and bond pads 1438. Thus, in accordance with various embodiments, vias 220, 222 are electrically connected to lower traces 1444 only, to bond pads 1438 only, and/or to both lower traces 1444 and bond pads 1438.
Electronic component 1432, bond wires 1442, vias 220, 222, and the exposed portions of upper surface 102U including upper traces 106 are enclosed, sometimes called encased, encapsulated, and/or covered, with package body 224. Illustratively, package body 224 is a cured liquid encapsulant, molding compound, or other dielectric material. Package body 224 protects electronic component 1432, bond wires 1442, vias 220, 222, and the exposed portions of upper surface 102U including upper traces 106 from the ambient environment, e.g., from contact, moisture and/or shorting to other structures.
To form stackable variable height via package 1300 as illustrated in
Terminals 1552 of a Land Grid Array (LGA) electronic component package 1554 are place on and in contact with protruding vias 1230. Further, interconnection balls 1556 on terminals 1558 of Ball Grid Array (BGA) electronic component packages 1560A, 1560B are placed inside of via apertures 226 on and in contact with vias 220.
Electronic component assembly 1500 is then heated to reflow vias 220, 1230 and interconnection balls 1556 thus mounting LGA electronic component package 1554 and BGA electronic component packages 1560A, 1560B to stackable variable height via package 1300 as those of skill in the art will understand in light of this disclosure.
Forming stackable variable height via package 1300 with variable height vias, e.g., vias 220, 1230, readily accommodate stacking of additional packages 1554, 1560A, 1560B having LGA and BGA types of terminals. Further, vias 220, 1230 are formed with a minimum pitch.
Electronic component assembly 1600 further includes a warped Ball Grid Array (BGA) package 1662 containing an electronic component. Warped BGA package 1662 is warped, i.e., is not completely planar. Warped BGA package 1662 is sometimes called bent, curved, and/or non-planar. More particularly, warped BGA package 1662 is bent from a hypothetical plane 1664 indicated by the dashed line. Typically, it is desirable to form a package without warpage, however, some warpage often occurs depending upon the manufacturing process used to fabricate the electronic component package.
Warped BGA package 1662 includes interconnection balls 1666 on terminals 1668 on a terminal, e.g., first, surface 1670 of warped BGA package 1662. Warped BGA package 1662 further includes a second surface 1672 opposite terminal surface 1670.
In accordance with this embodiment, warped BGA package 1662 is bent in the concave direction relative to terminal surface 1670. Stated another way, warped BGA package 1662 is concavely warped. Accordingly, the periphery P of terminal surface 1670, and in particularly the corners, are bent inward (downward in the view of
Vias 220, 222 accommodate the curvature of interconnection ball 1666 thus insuring formation of reliable interconnections therewith. In accordance with this embodiment, vias 220 are formed adjacent to periphery P, and in particular, at the corners. In contrast, vias 222, which have a greater height than vias 220, are formed adjacent to center C. Although vias 220, 222, i.e., two different height vias, are set forth, in light of this disclosure, those of skill in the art will understand that a plurality of different height vias are formed to accommodate the particular warpage of the package being mounted on stackable variable height via package 1300 in accordance with other embodiments.
Referring still to the example illustrated in
Shortened corners 1676 have a height H10 from upper surface 102U of substrate 102 less than height H9 of principal surface 224P of package body 224 from upper surface 102U of substrate 102. In one embodiment, shortened corners 1676 are formed by removal of package body 224 at corners 1378. In other embodiments, shortened corners 1676 are formed using selective molding, or other techniques.
By forming stackable variable height via package 1300 with shortened corners 1676, clearance is provided for the corners of warped BGA package 1662. The corners of warped BGA package 1662 typically have the greatest inward offset (warpage) of warped BGA package 1662. Accordingly, inadvertent and undesirable contact between the corners of warped BGA package 1662 and package body 224 is prevented thus insuring formation of reliable interconnections with warped BGA package 1662.
More particularly, interconnection balls 1666 and vias 220, 222, e.g., solder, are heated to melt interconnection balls 1666 and vias 220, 222. Upon melting, interconnection balls 1666 and vias 220, 222 combine into a single molten structures, e.g., molten solder. These molten structures cool and form solder columns 1780. In accordance with this embodiment, solder columns 1780 are integral, i.e., are single unitary structures and not a plurality of different layers connected together.
Solder columns 1780 physically and electrically connect terminals 104 of stackable variable height via package 1300 with terminals 1668 of warped BGA package 1662. Solder columns 1780 are formed with variable height to accommodate the warpage of warped BGA package 1662. More particularly, solder columns 1780A of the plurality of solder columns 1780 are formed adjacent to periphery P, and in particular, at the corners. In contrast, solder columns 1780B of the plurality of solder columns 1780, which have a greater height than solder columns 1780A, are formed adjacent to center C.
Electronic component assembly 1800 further includes a warped Ball Grid Array (BGA) package 1882. Warped BGA package 1882 is warped, i.e., is not completely planar. Warped BGA package 1882 is sometimes called bent, curved, and/or non-planar. More particularly, warped BGA package 1882 is bent from a hypothetical plane 1884.
Warped BGA package 1882 includes interconnection balls 1886 on terminals 1888 on a terminal, e.g., first, surface 1890 of warped BGA package 1882. Warped BGA package 1882 further includes a second surface 1892 opposite terminal surface 1890.
In accordance with this embodiment, warped BGA package 1882 is bent in the convex direction relative to terminal surface 1890. Stated another way, warped BGA package 1882 is convexly warped. Accordingly, the periphery P of terminal surface 1890, and in particularly the corners, are bent outward (upward in the view of
Vias 220, 1881, 222 accommodate the curvature of interconnection ball 1886 thus insuring formation of reliable interconnections therewith. In accordance with this embodiment, vias 222 are formed adjacent to periphery P, and in particular, at the corners. In contrast, vias 220, which have a lesser height than vias 222, are formed adjacent to center C. Vias 1881, which have a height between vias 222 and vias 220, are formed between vias 222 and vias 220.
In one embodiment, vias 222 are formed at the corners, vias 1881 are formed adjacent vias 222 only, and the remaining vias are vias 220. Although vias 220, 1881, 222, i.e., three different height vias, are set forth, in light of this disclosure, those of skill in the art will understand that a plurality of different height vias are formed to accommodate the particular warpage of the package being mounted on stackable variable height via package 1300 in accordance with other embodiments.
Referring still to the example illustrated in
Referring now to
Referring now to
In accordance with this embodiment, second electronic component 2002 includes an active surface 2004 and an opposite inactive surface 2006. Second electronic component 2002 further includes bond pads 2008 formed on active surface 2004. Inactive surface 2006 is mounted to active surface 1434 of first electronic component 1432 with an adhesive 2010. Bond pads 2008 are electrically connected to upper traces 106, e.g., bond fingers thereof, by electrically conductive bond wires 2012. Package body 224 further encapsulates second electronic component 2002 including bond wires 2012.
Although one example of a stacked configuration is illustrated in
The drawings and the forgoing description gave examples of the present invention. The scope of the present invention, however, is by no means limited by these specific examples. Numerous variations, whether explicitly given in the specification or not, such as differences in structure, dimension, and use of material, are possible. The scope of the invention is at least as broad as given by the following claims.
Number | Name | Date | Kind |
---|---|---|---|
3868724 | Perrino | Feb 1975 | A |
3916434 | Garboushian | Oct 1975 | A |
4322778 | Barbour et al. | Mar 1982 | A |
4532419 | Takeda | Jul 1985 | A |
4642160 | Burgess | Feb 1987 | A |
4645552 | Vitriol et al. | Feb 1987 | A |
4685033 | Inoue | Aug 1987 | A |
4706167 | Sullivan | Nov 1987 | A |
4716049 | Patraw | Dec 1987 | A |
4786952 | MacIver et al. | Nov 1988 | A |
4806188 | Rellick | Feb 1989 | A |
4811082 | Jacobs et al. | Mar 1989 | A |
4897338 | Spicciati et al. | Jan 1990 | A |
4905124 | Banjo et al. | Feb 1990 | A |
4964212 | Deroux-Dauphin et al. | Oct 1990 | A |
4974120 | Kodai et al. | Nov 1990 | A |
4996391 | Schmidt | Feb 1991 | A |
5021047 | Movern | Jun 1991 | A |
5072075 | Lee et al. | Dec 1991 | A |
5072520 | Nelson | Dec 1991 | A |
5081520 | Yoshii et al. | Jan 1992 | A |
5091769 | Eichelberger | Feb 1992 | A |
5108553 | Foster et al. | Apr 1992 | A |
5110664 | Nakanishi et al. | May 1992 | A |
5191174 | Chang et al. | Mar 1993 | A |
5229550 | Bindra et al. | Jul 1993 | A |
5239448 | Perkins et al. | Aug 1993 | A |
5247429 | Iwase et al. | Sep 1993 | A |
5250843 | Eichelberger | Oct 1993 | A |
5278726 | Bernardoni et al. | Jan 1994 | A |
5283459 | Hirano et al. | Feb 1994 | A |
5353498 | Fillion et al. | Oct 1994 | A |
5371654 | Beaman et al. | Dec 1994 | A |
5379191 | Carey et al. | Jan 1995 | A |
5404044 | Booth et al. | Apr 1995 | A |
5463253 | Waki et al. | Oct 1995 | A |
5474957 | Urushima | Dec 1995 | A |
5474958 | Djennas et al. | Dec 1995 | A |
5497033 | Fillion et al. | Mar 1996 | A |
5508938 | Wheeler | Apr 1996 | A |
5530288 | Stone | Jun 1996 | A |
5531020 | Durand et al. | Jul 1996 | A |
5546654 | Wojnarowski et al. | Aug 1996 | A |
5574309 | Papapietro et al. | Nov 1996 | A |
5581498 | Ludwig et al. | Dec 1996 | A |
5582858 | Adamopoulos et al. | Dec 1996 | A |
5616422 | Ballard et al. | Apr 1997 | A |
5637832 | Danner | Jun 1997 | A |
5674785 | Akram et al. | Oct 1997 | A |
5719749 | Stopperan | Feb 1998 | A |
5726493 | Yamashita et al. | Mar 1998 | A |
5739581 | Chillara | Apr 1998 | A |
5739585 | Akram et al. | Apr 1998 | A |
5739588 | Ishida et al. | Apr 1998 | A |
5742479 | Asakura | Apr 1998 | A |
5774340 | Chang et al. | Jun 1998 | A |
5784259 | Asakura | Jul 1998 | A |
5798014 | Weber | Aug 1998 | A |
5822190 | Iwasaki | Oct 1998 | A |
5826330 | Isoda et al. | Oct 1998 | A |
5835355 | Dordi | Nov 1998 | A |
5847453 | Uematsu et al. | Dec 1998 | A |
5883425 | Kobayashi | Mar 1999 | A |
5894108 | Mostafazadeh et al. | Apr 1999 | A |
5903052 | Chen et al. | May 1999 | A |
5907477 | Tuttle et al. | May 1999 | A |
5936843 | Ohshima et al. | Aug 1999 | A |
5952611 | Eng et al. | Sep 1999 | A |
6004619 | Dippon et al. | Dec 1999 | A |
6013948 | Akram et al. | Jan 2000 | A |
6021564 | Hanson | Feb 2000 | A |
6025648 | Takahashi et al. | Feb 2000 | A |
6028364 | Ogino et al. | Feb 2000 | A |
6034427 | Lan et al. | Mar 2000 | A |
6035527 | Tamm | Mar 2000 | A |
6040622 | Wallace | Mar 2000 | A |
6060778 | Jeong et al. | May 2000 | A |
6069407 | Hamzehdoost | May 2000 | A |
6072243 | Nakanishi | Jun 2000 | A |
6081036 | Hirano et al. | Jun 2000 | A |
6119338 | Wang et al. | Sep 2000 | A |
6122171 | Akram et al. | Sep 2000 | A |
6127833 | Wu et al. | Oct 2000 | A |
6160705 | Stearns et al. | Dec 2000 | A |
6172419 | Kinsman | Jan 2001 | B1 |
6175087 | Keesler et al. | Jan 2001 | B1 |
6184463 | Panchou et al. | Feb 2001 | B1 |
6194250 | Melton et al. | Feb 2001 | B1 |
6204453 | Fallon et al. | Mar 2001 | B1 |
6214641 | Akram | Apr 2001 | B1 |
6235554 | Akram et al. | May 2001 | B1 |
6239485 | Peters et al. | May 2001 | B1 |
D445096 | Wallace | Jul 2001 | S |
D446525 | Okamoto et al. | Aug 2001 | S |
6274821 | Echigo et al. | Aug 2001 | B1 |
6280641 | Gaku et al. | Aug 2001 | B1 |
6316285 | Jiang et al. | Nov 2001 | B1 |
6351031 | Iijima et al. | Feb 2002 | B1 |
6353999 | Cheng | Mar 2002 | B1 |
6365975 | DiStefano et al. | Apr 2002 | B1 |
6376906 | Asai et al. | Apr 2002 | B1 |
6392160 | Andry et al. | May 2002 | B1 |
6395578 | Shin et al. | May 2002 | B1 |
6405431 | Shin et al. | Jun 2002 | B1 |
6406942 | Honda | Jun 2002 | B2 |
6407341 | Anstrom et al. | Jun 2002 | B1 |
6407930 | Hsu | Jun 2002 | B1 |
6448510 | Neftin et al. | Sep 2002 | B1 |
6451509 | Keesler et al. | Sep 2002 | B2 |
6479762 | Kusaka | Nov 2002 | B2 |
6497943 | Jimarez et al. | Dec 2002 | B1 |
6517995 | Jacobson et al. | Feb 2003 | B1 |
6534391 | Huemoeller et al. | Mar 2003 | B1 |
6544638 | Fischer et al. | Apr 2003 | B2 |
6586682 | Strandberg | Jul 2003 | B2 |
6608757 | Bhatt et al. | Aug 2003 | B1 |
6660559 | Huemoeller et al. | Dec 2003 | B1 |
6715204 | Tsukada et al. | Apr 2004 | B1 |
6727645 | Tsujimura et al. | Apr 2004 | B2 |
6730857 | Konrad et al. | May 2004 | B2 |
6734542 | Nakatani et al. | May 2004 | B2 |
6740964 | Sasaki | May 2004 | B2 |
6753612 | Adae-Amoakoh et al. | Jun 2004 | B2 |
6774748 | Ito et al. | Aug 2004 | B1 |
6787443 | Boggs et al. | Sep 2004 | B1 |
6803528 | Koyanagi | Oct 2004 | B1 |
6815709 | Clothier et al. | Nov 2004 | B2 |
6815739 | Huff et al. | Nov 2004 | B2 |
6828665 | Pu et al. | Dec 2004 | B2 |
6838776 | Leal et al. | Jan 2005 | B2 |
6888240 | Towle et al. | May 2005 | B2 |
6919514 | Konrad et al. | Jul 2005 | B2 |
6921968 | Chung | Jul 2005 | B2 |
6921975 | Leal et al. | Jul 2005 | B2 |
6931726 | Boyko et al. | Aug 2005 | B2 |
6953995 | Farnworth et al. | Oct 2005 | B2 |
7015075 | Fay et al. | Mar 2006 | B2 |
7030469 | Mahadevan et al. | Apr 2006 | B2 |
7081661 | Takehara et al. | Jul 2006 | B2 |
7091619 | Aoyagi | Aug 2006 | B2 |
7125744 | Takehara et al. | Oct 2006 | B2 |
7185426 | Hiner et al. | Mar 2007 | B1 |
7198980 | Jiang et al. | Apr 2007 | B2 |
7242081 | Lee | Jul 2007 | B1 |
7282394 | Cho et al. | Oct 2007 | B2 |
7285855 | Foong | Oct 2007 | B2 |
7345361 | Mallik et al. | Mar 2008 | B2 |
7372151 | Fan et al. | May 2008 | B1 |
7429786 | Karnezos et al. | Sep 2008 | B2 |
7459202 | Magera et al. | Dec 2008 | B2 |
7548430 | Huemoeller et al. | Jun 2009 | B1 |
7550857 | Longo et al. | Jun 2009 | B1 |
7994643 | Kwon et al. | Aug 2011 | B2 |
20020017712 | Bessho et al. | Feb 2002 | A1 |
20020061642 | Haji et al. | May 2002 | A1 |
20020066952 | Taniguchi et al. | Jun 2002 | A1 |
20020195697 | Mess et al. | Dec 2002 | A1 |
20030025199 | Wu et al. | Feb 2003 | A1 |
20030128096 | Mazzochette | Jul 2003 | A1 |
20030141582 | Yang et al. | Jul 2003 | A1 |
20030197284 | Khiang et al. | Oct 2003 | A1 |
20040063246 | Karnezos | Apr 2004 | A1 |
20040145044 | Sugaya et al. | Jul 2004 | A1 |
20040159462 | Chung | Aug 2004 | A1 |
20050139985 | Takahashi | Jun 2005 | A1 |
20050242425 | Leal et al. | Nov 2005 | A1 |
20070273049 | Khan et al. | Nov 2007 | A1 |
20070281471 | Hurwitz et al. | Dec 2007 | A1 |
20070290376 | Zhao et al. | Dec 2007 | A1 |
20080230887 | Sun et al. | Sep 2008 | A1 |
20100072600 | Gerber | Mar 2010 | A1 |
Number | Date | Country |
---|---|---|
05-109975 | Apr 1993 | JP |
05-136323 | Jun 1993 | JP |
07-017175 | Jan 1995 | JP |
08-190615 | Jul 1996 | JP |
10-334205 | Dec 1998 | JP |
Entry |
---|
IBM Technical Disclosure Bulletin, “Microstructure Solder Mask by Means of a Laser”, vol. 36, Issue 11, p. 589, Nov. 1, 1993. |
Kim et al., “Application of Through Mold Via (TMV) as PoP base package”, 58th ECTC Proceedings, May 2008, Lake Buena Vista, FL, 6 pages, IEEE. |
Scanlan, “Package-on-package (PoP) with Through-mold Vias”, Advanced Packaging, Jan. 2008, 3 pages, vol. 17, Issue 1, PennWell Corporation. |
Hiner et al., “Printed Wiring Motherboard Having Bonded Interconnect Redistribution Mesa”, U.S. Appl. No. 10/992,371, filed Nov. 18, 2004. |
Scanlan et al., “Semiconductor Package Including a Top-Surface Metal Layer for Implementing Circuit Features”, U.S. Appl. No. 11/293,999, filed Dec. 5, 2005. |
Hiner et al., “Semiconductor Package Including Top-Surface Terminals for Mounting Another Semiconductor Package”, U.S. Appl. No. 11/595,411, filed Nov. 9, 2006. |
Huemoeller et al., “Build Up Motherboard Fabrication Method and Structure”, U.S. Appl. No. 11/824,395, filed Jun. 29, 2007. |
Berry et al., “Thin Stacked Interposer Package”, U.S. Appl. No. 11/865,617, filed Oct. 1, 2007. |
Longo et al., “Stacked Redistribution Layer (RDL) Die Assembly Package”, U.S. Appl. No. 12/387,672, filed May 5, 2009. |
Huemoeller et al., “Buildup Dielectric Layer Having Metallization Pattern Semiconductor Package Fabrication Method”, U.S. Appl. No. 12/387,691, filed May 5, 2009. |
Miller, Jr. et al., “Thermal Via Heat Spreader Package and Method”, U.S. Appl. No. 12/421,118, filed Apr. 9, 2009. |