Patent Application
20250142736
The present disclosure relates to component carriers and to methods of manufacturing a component carrier.
In the context of growing product functionalities of component carriers equipped with one or more electronic components and increasing miniaturization of such components as well as a rising number of components to be mounted on the component carriers such as printed circuit boards, increasingly more powerful array-like components or packages having several components are being employed, which have a plurality of contacts or connections, with ever smaller spacing between these contacts. Removal of heat generated by such components and the component carrier itself during operation becomes an increasing issue. At the same time, component carriers shall be mechanically robust and electrically reliable so as to be operable even under harsh conditions.
Manufacturing electrically conductive connection structures of a component carrier in a simple way and with high precision is still difficult.
There may be a need to form a component carrier with electrically conductive structures which can be manufactured in a simple way and with high precision.
In order to meet the need defined above, component carriers and methods of manufacturing a component carrier according to the independent claims are provided.
According to an exemplary embodiment of the disclosure, a method of manufacturing a component carrier is provided, wherein the method comprises stamping a surface profile in a design layer, forming a metallic base structure in at least one indentation of the profiled design layer at least partially by electroplating, and electroplating an electroplating structure in the at least one indentation on or above the metallic base structure.
According to another exemplary embodiment of the disclosure, a component carrier is provided which comprises a design layer having a stamped surface profile, an at least partially electroplated metallic base structure in at least one indentation of the profiled design layer, and an electroplated electroplating structure in the at least one indentation on or above the metallic base structure.
According to an exemplary embodiment of the disclosure, a method of manufacturing a component carrier is provided, wherein the method comprises arranging a design layer on an electrically conductive layer, forming, at least involving stamping (and optionally additionally etching), a surface profile with at least one indentation in the design layer so that at least one surface portion of the electrically conductive layer is exposed with respect to the design layer, and at least partially filling the at least one indentation by electroplating.
According to another exemplary embodiment of the disclosure, a component carrier is provided which comprises an electrically conductive layer, a stamped design layer arranged on the electrically conductive layer and having a surface profile with at least one indentation so that at least one surface portion of the electrically conductive layer is exposed with respect to the design layer, and an electroplated filling medium at least partially filling the at least one indentation.
In the context of the present application, the term “component carrier” may particularly denote any support structure which is capable of accommodating one or more components thereon and/or therein for providing mechanical support and/or electrical connectivity. In other words, a component carrier may be configured as a mechanical and/or electronic carrier for components. In particular, a component carrier may be one of a printed circuit board, an organic interposer, and an IC (integrated circuit) substrate. A component carrier may also be a hybrid board combining different ones of the above-mentioned types of component carriers.
In the context of the present application, the term “design layer” may denote a layer being flexibly processable for designing substantially any desired surface profile extending therein and/or therethrough. Thus, any desired wiring design may be translated into a corresponding surface profile of the design layer so that filling created indentations in the design layer with electrically conductive material may lead to the predefined wiring design. Preferably, the design layer may be an initially at least partially uncured dielectric which may be cured during and/or after forming a predefined surface profile therein. The surface profile may then be rendered permanent. Hence, the design layer may be deformable before curing and may be non-deformable after curing. Preferably, the design layer may be made of a Nanoimprint Lithography (NIL) material. The design layer may or may not form part of a readily manufactured component carrier.
In the context of the present application, the term “stamping a surface profile in the design layer” may denote the process of imprinting or embossing a predefined surface pattern in the design layer. For instance, this may be accomplished by pressing a working mold (or working stamp) in the (in particular still) deformable design layer or by guiding a working mold along the (in particular still) deformable design layer. Such a working mold may have an inverse surface profile in comparison with the surface profile of the design layer being processed. During a development and manufacturing process, first a master mold may be manufactured, for example by gray scale lithography. Then the master mold may be replicated by stamping several times into a transparent silicone material or the like, and a master working mold may be generated. Finally, working molds may be made by copying the master working mold. The working molds may be used during mass production and imprinted on panel surface.
In the context of the present application, the term “electroplating structure” may denote a metallic structure formed by electroplating. For electroplating, and in particular galvanic plating, of electrically conductive material on a seed layer formed by electroless plating, water-based solutions or electrolytes may be used which contain metal to be deposited as ions (for example as dissolved metal salts). An electric field between a first electrode (in particular an anode) and a preform of the component carrier to be manufactured as second electrode (in particular a cathode) may force (in particular positively charged) metal ions to move to the second electrode (in particular cathode) where they give up their charge and deposit themselves as metallic material on the surface of the through hole.
In the context of the present application, the term “metallic base structure” may denote electrically conductive material filling a bottom portion of an indentation. In particular, such a metallic base structure may be formed in a bottom portion of a through hole-type indentation in the profiled design layer. The metallic base structure may be formed of one or a plurality of substructures. At least part of the metallic base structure can be formed by electroplating.
In the context of the present application, the term “electroplating structure” may denote electrically conductive material filling a portion (in particular an upper portion) of an indentation in a profiled design layer on or above a metallic base structure and being electrically coupled with said metallic base structure. The electroplating structure may be formed by electroplating (in particular galvanic plating). Between the electroplating structure and the metallic base structure, a seed layer may be optionally sandwiched.
According to an exemplary embodiment of the disclosure, a method of manufacturing a component carrier (such as a printed circuit board, PCB) is provided which advantageously uses a design layer being deformed by mechanically stamping (in particular using a working mold) so that a surface profile in accordance with a wiring structure to be formed is created. One or more indentations of such a profiled design layer may then be filled partially or entirely with electrically conductive material comprising at least two separate constituents, i.e. the metallic base structure and the electroplating structure each of which being formed by a separate electroplating process. Hence, the filling of an indentation of a stamped design layer may be formed by two or more separate electroplating stages. This may ensure to properly fill, without voids, even indentations extending deep into or even through the entire design layer. Substantially void-free metal-filled indentations may lead to a high electrical reliability of the manufactured component carrier. At the same time, splitting the filling of an indentation with a metallic medium into two or more separate processes and consequently into two or more separate sub-structures may increase the freedom of design of a component carrier designer to individually select and functionalize each of the metallic base structure and electroplating structure. The described multi-filling approach may also allow the formation of very deep through connections in a stamped design layer, making it possible to create vertical through connections with very high aspect ratio.
According to an exemplary embodiment of the disclosure, a component carrier (in particular printed circuit board) manufacturing process is provided in which a design layer is imprinted or embossed by mechanically stamping (in particular using a working mold) so that a surface profile in accordance with a desired wiring structure is generated. One or more indentations of such a profiled design layer may then be configured as a through hole extending through the entire design layer to thereby expose a surface portion of an electrically conductive layer (such as a seed layer or a metal foil). Highly advantageously, an access through the profiled design layer up to the electrically conductive layer may then allow to form metal in the corresponding indentation by electroplating (in particular galvanic plating) by applying electricity to the electrically conductive layer. Advantageously, such a process is highly selective, so that an electroplating structure is only formed in through holes, not in blind holes, of the indented dielectric design layer.
In the following, further exemplary embodiments of the component carriers and the methods will be explained.
Next, advantageous material properties of the design layer will be summarized. The design layer may have one, any combination of at least two, or all of the properties mentioned in the following:
The glass temperature Tg of material (in particular of resin material) of the design layer may be in a range from 120° C. to 260° C. This may avoid undesired phase transitions of the design layer during processing and/or using the component carrier.
A value of the Young modulus below the glass temperature Tg may be in a range from 1000 MPa to 15000 MPa. A value of the Young modulus above the glass temperature Tg may be in a range from 60 MPa to 800 MPa. These properties may ensure that the material of the design layer is sufficiently mechanically strong for enabling a precise design of electrically conductive traces, vertical through connections, etc. in the design layer. At the same time, these properties may ensure that the material of the design layer has a sufficient elasticity to buffer thermal and/or mechanical stress.
A value of the coefficient of thermal expansion (CTE) below the glass temperature Tg may be in a range from 10 ppm/K to 40 ppm/K. A value of the coefficient of thermal expansion above the glass temperature Tg may be in a range from 50 ppm/K to 100 ppm/K. These values may suppress thermal stress in an interior of the component carrier.
A value of the fracture strain below the glass temperature Tg may be at least 2%. This may lead to advantageous mechanical properties of the design layer and a correspondingly manufactured component carrier.
A value of the chemical shrinkage may be not more than 3%. Consequently, shrinkage-based curing stress in an interior of the component carrier may be avoided.
A Dk value of the material of the design layer (in particular of resin thereof) may be not more than 3. A Df value of the material of the design layer (in particular of resin thereof) may be not more than 0.003. As a result, an obtained component carrier may have excellent properties in terms of high-frequency behavior.
A number of press cycles which the material of the design layer may withstand may be in a range from 1 to 10. A number of reflow tests which the material of the design layer may withstand may be at least 6. This may allow to manufacture a component carrier using a design layer with a stack thickness being selectable over a sufficiently broad range.
The material of the design layer may be characterized by a peel test on copper of at least 600 N/m. Moisture absorption by the material of the design layer may be not more than 0.1%. A desmear rate of the material of the design layer may be at least 0.006 g/min. The material of the design layer may be characterized by a UL listing (in accordance with the industrial standard IEC/DIN EN 60695-11-10 and -20 in the latest version being in force at the priority date of the present application) of V1 to V0 (which may ensure safety against flammability). The mentioned material properties may simplify processing of the design layer.
Advantageously, the design layer may comprise resin and (preferably inorganic) fillers (such as filler particles). Optionally, one or more additives may be included in the material of the design layer for functionalizing the latter.
Preferably, the inorganic fillers may be in a crystalline state. Furthermore, the inorganic fillers may be encapsulated. An average size (to be calculated according to an arithmetic average) of the inorganic fillers may be smaller than 0.1 μm. For example, the inorganic fillers may be made of fused silicon oxide. The inorganic filler particles may be plasma etchable. A weight percentage of the filler particles, in relation to an entire weight of the material of the design layer, may be up to 95 weight %.
A further constituent of the design layer may be resin. Epoxy resin, poly(p-phenylene ether) (PPE), Bisbenzocyclobutene (BCB), Polybenzoxabenzole (PBO), and/or polyimide may be used. A chloride content of the resin may be below 30 ppm. Advantageously, no salt formation should occur during the processing of the resin. Moreover, a high cross-linking capability of the resin may be advantageous. A low porosity may be preferred to avoid undesired phenomena such as cracks, migration, etc.
In an embodiment, the stamping comprises forming tapering indentations in the design layer. Correspondingly, the electroplating structure may have tapering sidewalls. Advantageously, stamping of the design layer may be accomplished by a working mold (for instance a glass plate with a surface profile on one main surface) deforming the design layer for forming a surface profile therein being inverse to a surface profile of the working mold. After the stamping process, the working mold may be removed again from the design layer. Under undesired circumstances, it may be difficult to remove the master mold from the design layer after stamping without damaging the formed surface profile due to adhesion between design layer and working mold. However, it has been surprisingly found that providing the working mold with tapering protrusions corresponding to inverse tapering indentations in the design layer significantly reduces the tendency of the working mold of adhering to the profiled design layer when removing the working mold after stamping. Furthermore, such a tapering geometry may also reduce the risk of defects in the processed design layer.
In an embodiment, the stamping comprises forming indentations of different depth and/or different length in the design layer. Correspondingly, the electroplating structure and the metallic base structure (optionally in combination with a portion of the seed layer) may form or may form part of sub-structures of different depth and/or different length in the design layer. For instance, at least one first indentation formed in the design layer may extend through the entire design layer and may thereby form a through hole. Such a through hole may, when filled with plated metal, form an electrically conductive through connection (such as a via) in the readily manufactured component carrier. For example, at least one second indentation formed in the design layer may extend through only part of the thickness of the design layer and may thereby form a blind hole. Such a blind hole may, when filled with plated metal, form a horizontally extending trace in the readily manufactured component carrier. Advantageously, a horizontal trace may have a larger length than a vertical through connection. With the described manufacturing architecture, a design layer may be formed with two or more indentations extending up to different vertical positions and/or extending along different horizontal extensions. Consequently, even complex horizontal and/or vertical wiring structures may be defined precisely and in a simple way. In particular, this may also make it possible to create three-dimensionally curved wiring structures.
In an embodiment, the stamping comprises forming trace-shaped and/or via-shaped and/or combined trace-and-via-shaped indentations in the design layer. Accordingly, the electroplating structure and the metallic base structure (optionally in combination with a portion of a seed layer) may form or form part of trace-type and/or via-type sub-structures, or a combination thereof. Highly advantageously, both electrically conductive traces and vertical through connections may be formed simultaneously and thereby quickly with miniature dimensions in a common design layer.
In an embodiment, the method comprises curing the design layer, in particular simultaneously stamping and curing the design layer. During the NIL process, the stamping and curing may occur simultaneously (once one stamps, one may expose the structure, to prevent the resist from flowing apart). During stamping, the design layer is preferably freely deformable by a mechanical impact, which allows to stamp indentations in the design layer by a working mold in accordance with a desired wiring pattern. After stamping, the created surface profile shall remain permanent at least in certain embodiments, i.e. the processed design layer shall be converted into a non-deformable state. This can be accomplished by curing the design layer. For instance, when the design layer comprises at least partly uncured resin, curing may be accomplished by the application of thermal energy and/or mechanical pressure, which may trigger curing processes such as cross-linking, polymerization, etc. Supply of curing energy may be accomplished by irradiation of the design layer with electromagnetic radiation of an electro-magnetic radiation source, preferably ultraviolet (UV) radiation. Highly advantageously, curing of the design layer may be accomplished during stamping and further advantageously by a working mold itself. For instance, a light source (such as a UV lamp) may be integrated in the working mold so that light-triggered (in particular UV-triggered) curing may be carried out during the process of stamping.
In an embodiment, the method comprises forming an electrically conductive seed layer on the stamped design layer and/or on the metallic base structure, forming a patterned electroplating protection structure on portions of the seed layer apart from indentations of the profiled design layer, and electroplating the electroplating structure selectively on or above portions of the seed layer exposed with respect to the electroplating protection structure. In the context of the present application, the term “seed layer” may denote a thin metallic layer which may be formed by electroless plating. Electroless plating may denote a formation of the seed layer by a plating process which does not involve application of electricity to a structure to be plated with the seed layer. For example, electroless plating may involve formation of a chemical metal film as the seed layer. Additionally or alternatively, electroless plating may comprise forming the seed layer by sputtering. In the context of the present application, the term “electroplating protection structure” may denote a structure made of a material on which no (or at least no noteworthy amount of) metal can be deposited by electroplating. Thus, the electroplating protection structure may be an anti-plating dielectric structure and may particularly denote an electrically insulating structure made of a material on which plating of a metal is inhibited, disabled or made impossible. This can be accomplished by providing the anti-plating dielectric structure from a non-adhesive or very poorly adhesive dielectric material with preferably hydrophobic properties on which electroplated metal does not adhere. Also, non-polarized properties of the electroplating protection structure may be advantageous. For example, the electroplating protection structure may comprise at least one of a group consisting of a release ink, polytetrafluoroethylene, and polyimide. More generally, any hydrophobic material may be appropriate for forming the electroplating protection structure. It is also possible that such a non-adhesive or poorly adhesive structure may be made of a waxy material or a suitable varnish.
According to an exemplary embodiment of the disclosure, a method of manufacturing a component carrier (such as a printed circuit board, PCB) is provided which advantageously uses a design layer being deformed by mechanically stamping (in particular using a working mold) so that a surface profile in accordance with a wiring structure to be formed can be created with high spatial resolution. After having formed a metallic seed layer on the created surface profile, an anti-plating protection structure may be formed on the seed layer (preferably only in the highest parts of the structure) so as to selectively expose one or more indentations with respect to the protection structure, whereas one or more non-stamped regions of the processed design layer apart from indentations may be covered with the protection structure. Advantageously, a subsequent electroplating process will then lead to a coverage only of an exposed region of the seed layer with electroplated metal, while no or substantially no electroplating of metal will occur on the protection structure. After a removal of the protection structure and seed layer portions beneath, a well-defined wiring pattern may be obtained in which electroplated metal is only present in the indentations, and not in regions in between. Highly advantageously, even complex wiring structures may thus be formed with very low manufacturing effort and excellent spatial accuracy. Advantageously, the provision of a patterned protection structure may prevent overplating in elevated regions of the design layer apart from the indentations during the electroplating process and may thus avoid the high effort and significant time consumption of a difficult polishing process for removing overplated metal. In particular polishing processes such as CMP (chemical mechanical polishing) are difficult to execute on a panel format, i.e. for formation of PCB-type component carriers using a design layer on panel level. Hence, manufacture of the component carriers may be carried out in a simple way and with high spatial accuracy.
In an embodiment, a continuous layer of the protection structure may be formed on the seed layer and may be subsequently patterned, for instance by lithography and etching. However, it may be preferred to form a patterned protection structure by using a simple non-selective process, as for example a flat surface being coated completely with protection ink. Thereafter, use can be made of different NIL resist heights (i.e. regions of different height of the profiled design layer) that are present after NIL imprinting (i.e. after stamping the design layer)—by coating only the top layer of the NIL imprinted resist (i.e. profiled design layer) by a short contact between the ink coated surface and the NIL resist surface. By taking this measure it may be ensured that the protection structure is formed only on the highest regions of the profiled design layer.
In an embodiment, the method comprises removing the electroplating protection structure after the electroplating. For instance, a resist layer used as electroplating protection structure may be removed after electroplating by etching or stripping.
In an embodiment, the method comprises removing portions of the seed layer which have been exposed as a result of the removing of the electroplating protection structure. Removal of the patterned electroplating protection structure after the electroplating may expose portions of the seed layer which have been initially covered by the electroplating protection structure. The latter mentioned portions of the seed layer may be subsequently removed for separating and thereby electrically decoupling individual wiring structures in the indentations.
In an embodiment, the method comprises forming the design layer on or above a carrier covered with a release layer and detaching the profiled design layer with sections of the seed layer and the electroplating structure from the carrier at the release layer. Preferably, the carrier may comprise or may consist of glass. For example, such a temporary carrier may be a support plate, for instance made of glass or FR4. Preferably, the mentioned release layer may have non-adhesive or poorly adhesive properties. Examples of materials of the release layer are a release ink, polytetrafluoroethylene, polyimide, a waxy material or a suitable varnish. This allows detaching the readily manufactured component carrier or a preform thereof from the temporary carrier at the end of a manufacturing process.
In another embodiment, the method comprises forming the design layer on the carrier, not necessarily comprising a release layer. As mentioned, the carrier may be a temporary carrier which may be removed at the end of the manufacturing process. However, alternatively, the carrier may form part of the component carrier, in which case the carrier is not removed from the design layer. Such a carrier may also be—in particular directly—connected to the design layer (i.e. may also be provided without a release layer in between). Such a carrier may be an insulating layer (e.g. comprising resin) with or without an (in particular patterned) electrically conductive wiring thereon. This electrically conductive wiring allows a direct electric connection from the carrier to the metallic base structure. A permanent carrier forming part of a component carrier according to an exemplary embodiment of the disclosure may be made preferably of glass. It is specifically preferred that such a component carrier with glass carrier is configured as an interposer. Hence, in particular when glass is used as an insulating layer or insulating carrier, it may be advantageous that an additive build-up with NIL is used for manufacturing an interposer. As interposers can be advantageously made with glass as an insulating material, the carrier structure (or further build-up structure) can be advantageously used for a NIL process.
In an embodiment, the method comprises forming a build-up based on the detached profiled design layer with sections of the seed layer and the electroplating structure. It is also possible that the method comprises forming a build-up on the profiled design layer with sections of the seed layer and the electroplating structure. Accordingly, the component carrier may comprise a build-up on one or both opposing sides of the profiled design layer with the portions of the seed layer and the electroplating structure. Hence, after or without detaching the profiled and metallized design layer from the carrier, a further build-up of the component carrier may be formed.
Preferably, the build-up comprises at least one laminated printed circuit board-type layer stack. Formation of such a build-up may involve processes such as laminating additional electrically conductive layer structures (for example copper foils) and/or electrically insulating layer structures (for instance prepreg sheets) to one or both opposing main surfaces of the separated profiled and metallized design layer. However, galvanic plating of copper layers may be preferred in certain embodiments. The readily manufactured component carrier may then be a hybrid of the profiled and metallized design layer and the PCB-type stack(s) of laminated layer structures.
In an embodiment, the method comprises applying an adhesion promoter (such as an adhesion promoting layer) on the stamped design layer before forming the electrically conductive seed layer. Such an adhesion promoter may for instance comprise silane and may be deposited as a thin layer before creating the seed layer. This may improve the interlayer adhesion of the obtained structure and may therefore suppress undesired phenomena such as delamination in the readily manufactured component carrier. Additionally or alternatively to an adhesion promoter, it is also possible to apply a barrier layer which may function as a barrier for connected materials.
In an embodiment, the method comprises removing, in particular by etching, residues of the design layer in at least one bottom region of the indentations of the profiled design layer. In particular when intending to form through holes extending through the entire design layer, it may happen that, after the stamping, a thin skin of design layer material remains at the bottom of the indentation which shall form a through hole. During forming a seed layer, such an artifact may lead to an undesired electric isolation by the remaining dielectric skin. In order to avoid such phenomena, it may be advantageous to treat the stamped design layer (in particular prior to seed layer formation) by an etching process to remove residues from indentations of the design layer after stamping.
In an embodiment, the method comprises arranging and processing the design layer on an electrically conductive layer so that at least one surface portion of the electrically conductive layer is exposed with respect to the stamped design layer. Correspondingly, the design layer of the component carrier may be arranged on an electrically conductive layer so that at least one surface portion of the electrically conductive layer is exposed with respect to the design layer at least one of the indentations. For example, such an electrically conductive layer may be a copper foil or another seed layer underneath the design layer. By exposing one or more portions of the electrically conductive layer by stamping the design layer, it is possible to easily define said one or more portions as selective surface for subsequent electroplating.
In an embodiment, the method comprises forming the metallic base structure selectively on the at least one exposed surface portion of the electrically conductive layer and in the corresponding at least one indentation of the profiled design layer. Accordingly, the component carrier may comprise the metallic base structure in a bottom of a corresponding indentation of the design layer. Thus, the one or more exposed surface portions of the electrically conductive layer may define where the metallic base structure can be formed by electroplating, in particular galvanic plating. This may be accomplished by applying an electric voltage to the electrically conductive layer in an appropriate galvanic path.
In an embodiment, the method comprises subsequently electroplating the electroplating structure on or above the metallic base structure. Correspondingly, at least a portion of the electroplating structure of the component carrier may be arranged on top of the metallic base structure. Descriptively speaking, at least one further electroplating structure may be formed as the metallic base structure by at least one further electroplating stage, in particular by galvanic plating. The separate formation of the metallic base structure and the electroplating structure may also allow to create the creation of a multi-metal structure in an indentation of the profiled design layer. Hence, it may be possible to fill an indentation with at least two different metallic materials, each of which being functionally adjustable separately.
In an embodiment, the method comprises forming the metallic base structure to comprise a bottom-sided sub-structure and a top-sided sub-structure. Correspondingly, the metallic base structure may comprise a bottom-sided sub-structure and a top-sided substructure in the readily manufactured component carrier. For reliably filling deep indentations with metallic material, it may be preferable to execute the filling process with at least two electroplating stages for forming the metallic base structure.
In an embodiment, the method comprises forming at least part of the metallic base structure by electroplating. Preferably, the metallic base structure may be formed by galvanic plating.
In an embodiment, the method comprises removing the design layer before completing manufacture of the component carrier. In such an embodiment, the design layer does not form part of the readily manufactured component carrier, i.e. may be a temporary design layer. This may be advantageous in a configuration in which highly homogeneous material properties of the component carrier, such as a printed circuit board (PCB), are desired. This may make it possible to constitute for instance the entire dielectric material of the component carrier from prepreg or FR4.
Alternatively, the design layer may remain part of the readily manufactured component carrier, i.e. may be a permanent design layer. It may then be possible to adjust the material properties of the design layer so that a component carrier with high electric, mechanical and/or thermal reliability is obtained. This may allow to suppress undesired phenomena such as warpage, delamination, and mechanical and/or thermal stress. For example, this may be accomplished by configuring the design layer with material properties as described herein.
In an embodiment, the electroplating structure and the metallic base structure form at least one sub-structure having a depth-to-diameter ratio (which may also be denoted as aspect ratio) of larger than 1, and in particular of larger than 1.5. With conventional laser drilling, the aspect ratio is strongly limited for technical reasons. However, when defining indentations by stamping a still uncured deformable design layer with a correspondingly shaped working mold, there are substantially no limits in terms of aspect ratio. Thus, indentations with an aspect ratio of more than 1, for instance as large as 2 or more, may be created in a simple and reliable way by stamping a design layer.
In an embodiment, a roughness Ra of a surface, in particular a side-wall surface, of the design layer delimiting the surface profile is not more than 100 nm, in particular not more than 50 nm. Ra denotes the arithmetic mean value of all distances of a profile from a centerline. For instance, the measurement or determination of roughness Ra may be carried out according to DIN EN ISO 4287:2010. The mentioned roughness values may lead to a low loss transmission of radio-frequency signals through the wiring structure(s), since no excessive surface roughness deteriorates signal propagation under consideration of the skin effect. According to the skin effect, an electric signal with a high-frequency, for instance in the gigahertz range, does not propagate over an entire cross-section of a conductor, but propagates substantially only within a skin-like surface portion thereof. This may conventionally cause significant signal losses with rough surfaces. Without wishing to be bound to a specific theory, it is presently believed that such signal losses may result from an additional electric resistance or impedance which the traveling radiofrequency signal suffers as a consequence of a rough surface. Advantageously, such signal losses can be prevented or at least strongly suppressed when ensuring a low roughness of electrically conductive wiring structures of a component carrier as a result of the formation of indentations in a design layer by stamping.
In an embodiment, the component carrier comprises at least one component being electrically connected to the metallic base structure and the electroplating structure. Such a component, for instance an electronic component such as a semiconductor chip, may be surface mounted on the design layer with integrated wiring structure.
In an embodiment, the component carrier further comprises a further design layer in which a further surface profile is stamped, a further at least partially electroplated metallic base structure in at least one further indentation of the profiled further design layer, and a further electroplated electroplating structure in the at least one further indentation on or above the further metallic base structure, wherein the further profiled design layer with the further metallic base structure and the further electroplating structure are arranged on the profiled design layer with the metallic base structure and the electroplating structure. Hence, a plurality of design layers, each with integrated wiring structure(s), may be vertically stacked to form more complex three-dimensional arrangements of wiring structures. Hence, this may make it possible to create even sophisticated or complex wiring architectures in the component carrier in a straightforward way. Working molds of different stacked design layers may be the same or may be different.
In an embodiment, the further metallic base structure and the further electroplating structure are connected in a landless way with the metallic base structure and the electroplating structure. Advantageously, pads between stacked design layers, each formed with integrated wiring structure(s), may be dispensable in view of the high spatial accuracy of the definition of the wiring structures by stamping using a corresponding working mold. In particular, a correspondingly formed electroplating structure may comprise three-dimensionally curved substructures.
In an embodiment, the component carrier comprises at least one component, such as an electronic component like a semiconductor chip, mounted on the design layer by a connection structure (for example by one of a solder structure and a thermal compression bonding structure) arranged between the component and the design layer. For example, the solder structure may be constituted by solder balls applied to the component or on top the design layer. As an alternative to soldering, surface mounting of one or more components may also be accomplished by sintering, gluing, etc. Also, thermal compression bonding is an option for mounting a component on the stack of the component carrier.
In an embodiment, the component carrier comprises two components arranged side-by-side on the design layer and being electrically coupled with each other by electrically conductive connection structures at and/or lateral from a protrusion of the design layer. Highly advantageously, the design layer may be synergistically used for horizontally connecting laterally adjacent components mounted on the design layer. For this purpose, the surface profile of the design layer may comprise a central protrusion protruding vertically beyond a horizontal surface of the rest of the design layer. Side portions of each of the two components to be electrically connected with each other may then be mounted on corresponding portions of the central protrusion, so that electrically conductive connection structures on the protrusion between the protrusion and each of the surface mounted components may then establish an electric coupling between the components. Additionally or alternatively, such electrically conductive connections may be formed on surface portions beneath the components and apart from the central protrusion and may extend between the design layer apart from the central protrusion and each of the components. By the described component-to-component connection architecture, a conventionally used silicon bridge may be omitted and may be replaced by a central protrusion of the design layer. This renders the interconnection within a component carrier with surface mounted components easy.
As mentioned above, at least partially filling the at least one indentation by electroplating may comprise forming a metallic base structure in the at least one indentation. Furthermore, at least partially filling the at least one indentation by electroplating may comprise electroplating an electroplating structure in the at least one indentation on or above the metallic base structure. The metallic base structure may be directly connected to the electroplating structure. Alternatively, a seed layer may be sandwiched between the metallic base structure and the electroplating structure. Thus, an electroplated filling medium in an indentation may comprise a metallic base structure and may also comprise an electroplating structure on or above the metallic base structure.
In an embodiment, the method comprises removing the electrically conductive layer and/or the design layer partially or entirely before completing manufacture of the component carrier. Thus, any of the electrically conductive layer and the design layer may or may not form, partially or entirely, part of the readily manufactured component carrier. It can be removed as a sacrificial layer or can be used, for instance in a patterned form, for contributing to the electrically conductive wiring or to the dielectric matrix of the component carrier.
Specifically, the design layer material is configured for being used for prepolymer composition, characterized in that it is used for continuous structuring and in-situ UV curing in a NIL imprint process, preferably in a roll-to-plate process, which stays in a final build-up.
Specifically, the design layer material is configured for being used as an etching production during an etching process for structuring a surface.
According to a further exemplary embodiment the design layer has an adhesion of more than 600 Nm. Adhesion is the tendency of dissimilar particles or surfaces to cling to one another. The forces that cause adhesion may be intermolecular forces responsible for the function of various kinds of stickers and sticky tape fall into the categories of chemical adhesion, dispersive adhesion, and diffusive adhesion.
According to a further exemplary embodiment the design layer comprises temperature resistance between 200° C. and 300° C., in particular 230° C. to 260° C. The design layer may be in particular a cured cross-linked resist material having the temperature resistance between 230° C. to 260° C. The higher the cross-linking, the higher the modulus-depending on used base oligomers.
According to a further exemplary embodiment, the design layer comprises material of a flame retardancy class 4 (FR4). FR4 may be a composite material composed of woven fiberglass cloth with an epoxy resin binder that is flame resistant (self-extinguishing). FR-4 glass epoxy is a high-pressure thermoset plastic laminate grade with good strength to weight ratios. With near zero water absorption, FR-4 is used as an electrical insulator possessing considerable mechanical strength.
According to a further exemplary embodiment, the design layer comprises material having a glass-transition temperature between 120° C. and 200° C., in particular between 135° C. and 170° C.
According to a further exemplary embodiment, the design layer has a (Young) modulus below a glass-transition temperature (in the fully cured stage) of 1000 MPa to 14000 MPa, in particular 5000 MPa to 13000 MPa.
According to a further exemplary embodiment, the design layer has a (Young) modulus above a glass-transition temperature (i.e. in a reflow state) of 60 MPa to 800, in particular 100 MPa to 600 MPa. The glass-liquid transition is the gradual and reversible transition in amorphous materials (or in amorphous regions within semicrystalline materials) from a hard and relatively brittle glassy state into a viscous or rubbery state as the temperature is increased. An amorphous solid that exhibits a glass transition is called a glass. The reverse transition, achieved by supercooling a viscous liquid into the glass state, is called vitrification. The glass-transition temperature Tg of a material characterizes the range of temperatures over which this glass transition occurs. It is lower than the melting temperature.
These properties may ensure that the material of the design layer is sufficiently mechanically strong for enabling a precise design of electrically conductive traces, vertical through connections, etc. in the design layer. At the same time, these properties may ensure that the material of the design layer has a sufficient elasticity to buffer thermal and/or mechanical stress.
According to a further exemplary embodiment, the design layer has a thermal expansion coefficient below a glass-transition temperature of 10 ppm/K to 40 ppm/K, in particular 20 ppm/K to 40 ppm/K. These values may suppress thermal stress in an interior of the component carrier.
According to a further exemplary embodiment, the design layer has a thermal expansion coefficient above a glass-transition temperature of 50 ppm/K to 100 ppm/K, in particular 60 ppm/K to 85 ppm/K. These values may suppress thermal stress in an interior of the component carrier. The higher the value of the thermal expansion coefficient (CTE) above Tg, the higher the reliability issue. The design layer may comprise non-woven glass fibers such that thermal expansion occurs in all directions. The thermal expansion coefficient is also driven by the amount of fillers. The thermal expansion coefficient decreases if the amount of filler increases. The design layer may have a filler content 80% filler.
According to a further exemplary embodiment, the design layer is formed with a fracture strain below a glass-transition temperature of 2%. This may lead to advantageous mechanical properties of the design layer and a correspondingly manufactured component carrier.
According to a further exemplary embodiment, the design layer is formed with a chemical shrinkage below 3%. Consequently, shrinkage-based curing stress in an interior of the component carrier may be avoided.
According to a further exemplary embodiment, the design layer is formed with a moisture absorption below 0.1%, and/or a desmear rate below 0.006 g/min of 3%.
A Dk value of the material of the design layer (in particular of resin thereof) may be not more than 3, specifically for high frequency applications. A Df value of the material of the design layer (in particular of resin thereof) may be not more than 0.003, specifically for high frequency applications. As a result, an obtained component carrier may have excellent properties in terms of high-frequency behavior. If the filler content increases, the values for Dk and Df increase as well.
A number of press cycles which the material of the design layer may withstand may be in a range from 1 to 10. A number of reflow tests which the material of the design layer may withstand may be at least 6. This may allow to manufacture a component carrier using a design layer with a stack thickness being selectable over a sufficiently broad range. The material of the design layer may be characterized by a peel test on copper of at least 600 N/m. A press cycle of the design layer may withstand from 6 up to 10 times.
A desmear rate of the material of the design layer may be at least 0.006 g/min. The material of the design layer may be characterized by a UL listing (in accordance with the industrial standard IEC/DIN EN 60695-11-10 and -20 in the latest version being in force at the priority date of the present application) of V1 to V0 (which may ensure safety against flammability). The mentioned material properties may simplify processing of the design layer. The design layer comprises aromatic hydrocarbons, such as PPE (poly(p-phenylene ether), BCB (Benzocyclobutene), Epoxy and/or halogenated polyimide. Specifically, the design layer is configured for being used in a SLID soldering process, wherein temperatures of 25° C. for 0.5 to 1 hour are applied.
According to a further exemplary embodiment, the design layer comprises a fully cured polymer based on at least one of the following group comprising epoxies, acrylates, polyphenylenether, polyimide, polyamide and polyetheretherketon, poly(p-phenylene ether) (PPE), Bisbenzocyclobutene (BCB), and/or Polybenzoxabenzole (PBO).
Specifically, a combination of the oligomers listed above may be used for a (specifically permanent) design layer (i.e. an UV-NIL resist). For example, a combination of BCB, PPE and SU8 loaded can be used with a high amount of more than 80% of encapsulated inorganic, round shape SiO2 nanofillers and a halogen-free material.
For example, BCB (Divinylsiloxane-bis-benzocyclobutene (DVS-bis-BCB, or BCB), e.g. CYCLOTENE™ DuPont Series advanced electronic resins) are photopolymers. These polymers are derived from B-staged bisbenzocyclobutene (BCB) chemistry.
For example, PPE (e.g. Sabic NORYL SA9000 resin) is a modified, low molecular weight, bi-functional oligomer based on polyphenylene ether (PPE) with vinyl end-groups (used in Megtron 6 & 7 Materials).
For example, SU-8 (e.g. Kayaku Advanced Materials SU-8) is a high contrast, epoxy-based photoresist designed for micromachining and other microelectronic applications.
A chloride content of the resin may be below 30 ppm. Specifically, the design layer may be almost free of halogens (e.g. less than 30 ppm) which are ionic and not bonded with a polymer. The halogens may be washed out with multiple water wash steps.
Advantageously, no salt formation should occur during the processing of the resin. Moreover, a high cross-linking capability of the resin may be advantageous. A low porosity may be preferred to avoid undesired phenomena such as cracks, migration, etc.
According to a further exemplary embodiment, the design layer comprises polymer- or oligomer-based building blocks, wherein at least one of the building blocks is based on one of the above-mentioned polymers.
According to a further exemplary embodiment, the design layer at least one of the building-blocks has at least one functional group covalently bond to another one of the least one building block. The covalently bound functional group is responsible for the cross-linking connection.
According to a further exemplary embodiment, the at least one functional group is selected from one of the group comprising a thiol group selected from the group of 3-mercaptopropionates, 3-mercaptoacetates, thioglycolates and alkylthiols, and/or a double bond selected from the group of acrylates, methyl acrylates, vinyl ethers, allyl ethers, propenyl ethers, alkenes, dienes, unsaturated esters and allyl triazines, allyl isocyanates and N-vinyl amides.
According to a further exemplary embodiment, the design layer comprises a prepolymer having at least one photoinitiator, contained in an amount of 0.1 wt. % to 10 wt. %, in particular 0.5 wt. % to 5 wt. %.
According to a further exemplary embodiment, the design layer is in particular a fully cured resin, wherein the design layer further comprises filler particles such as in an amount of 1 wt. % to 10 wt. %, in particular 1 wt. % to 3 wt. %.
According to a further exemplary embodiment, the filler particles comprise inorganic fillers, wherein the inorganic fillers are in a crystalline state and in particular encapsulated. The inorganic fillers may be nanofillers which can be coated to avoid agglomeration and reduce thixotropy. Porous fillers may have lower Dk because of air but they can absorb chemistry. Therefore, porous fillers have a hydrophobic silane coating as it is the case in Rogers 3000 materials, at the same time mixing of fillers in the resin matrix is easier. Halogenated organics, hydrophobic polymers and covalent bonded halogen can be used for the fillers so that a high flame retardant can be achieved. The design layer may comprise high inorganic filler with an aromatic content. The inorganic fillers may have a round smooth shape, which is better than needles shape.
According to a further exemplary embodiment the filler particles comprise a size (e.g. an average size to be calculated according to an arithmetic average) of less than 0.1 μm.
According to a further exemplary embodiment, the filler particles comprise Talcum (i.e. a layered silicate), Zeolite and/or fused SiO2. SiO2 or Zeolite nanofiller usually agglomerate but with coating this agglomeration can be reduced and also tixotrophy may be reduced.
According to a further exemplary embodiment, the filler particles are of plasma etchable material.
According to a further exemplary embodiment, the design layer comprises less than 95% (weight percentage) filler particles, in particular 80% to 95% filler particles, in relation to an entire weight of the material of the design layer. More filler particles cause less shrinking of ink during UV-curing, for example, and causes better CTE at the same time. Furthermore, better flame retardant is achieved at the same time.
In an embodiment, the component carrier comprises a stack of at least one electrically insulating layer structure and at least one electrically conductive layer structure. For example, the component carrier may be a laminate of the mentioned electrically insulating layer structure(s) and electrically conductive layer structure(s), in particular formed by applying mechanical pressure and/or thermal energy. The mentioned stack may provide a plate-shaped component carrier capable of providing a large mounting surface for further components and being nevertheless very thin and compact.
In an embodiment, the component carrier is shaped as a plate. This contributes to the compact design, wherein the component carrier nevertheless provides a large basis for mounting components thereon. In particular a naked die as an example for an electronic component can be surface mounted on a thin plate such as a printed circuit board.
In an embodiment, the component carrier is configured as one of the group consisting of a printed circuit board, a substrate (in particular an IC substrate), and an interposer.
In the context of the present application, the term “printed circuit board” (PCB) may particularly denote a plate-shaped component carrier which is formed by laminating several electrically conductive layer structures with several electrically insulating layer structures, for instance by applying pressure and/or by the supply of thermal energy. As preferred materials for PCB technology, the electrically conductive layer structures are made of copper, whereas the electrically insulating layer structures may comprise resin and/or glass fibers, so-called prepreg or FR4 material. The various electrically conductive layer structures may be connected to one another in a desired way by forming holes through the laminate, for instance by laser drilling or mechanical drilling, and by partially or fully filling them with electrically conductive material (in particular copper), thereby forming vias or any other through-hole connections. The filled hole either connects the whole stack, (through-hole connections extending through several layers or the entire stack), or the filled hole connects at least two electrically conductive layers, called via. Similarly, optical interconnections can be formed through individual layers of the stack in order to receive an electro-optical circuit board (EOCB). A printed circuit board is usually configured for accommodating one or more components on one or both opposing surfaces of the plate-shaped printed circuit board. They may be connected to the respective main surface by soldering. A dielectric part of a PCB may be composed of resin with reinforcing fibers (such as glass fibers).
In the context of the present application, the term “substrate” may particularly denote a small component carrier. A substrate may be a, in relation to a PCB, comparably small component carrier onto which one or more components may be mounted and that may act as a connection medium between one or more chip(s) and a further PCB. For instance, a substrate may have substantially the same size as a component (in particular an electronic component) to be mounted thereon (for instance in case of a Chip Scale Package (CSP)). More specifically, a substrate can be understood as a carrier for electrical connections or electrical networks as well as component carrier comparable to a printed circuit board (PCB), however with a considerably higher density of laterally and/or vertically arranged connections. Lateral connections are for example conductive paths, whereas vertical connections may be for example drill holes. These lateral and/or vertical connections are arranged within the substrate and can be used to provide electrical, thermal and/or mechanical connections of housed components or unhoused components (such as bare dies), particularly of IC chips, with a printed circuit board or intermediate printed circuit board. Thus, the term “substrate” also includes “IC substrates”. A dielectric part of a substrate may be composed of resin with reinforcing particles (such as reinforcing spheres, in particular glass spheres).
The substrate or interposer may comprise or consist of at least a layer of glass, silicon (Si) and/or a photoimageable or dry-etchable organic material like epoxy-based build-up material (such as epoxy-based build-up film) or polymer compounds (which may or may not include photo- and/or thermosensitive molecules) like polyimide or polybenzoxazole.
In an embodiment, the at least one electrically insulating layer structure comprises at least one of the group consisting of a resin or a polymer, such as epoxy resin, cyanate ester resin, benzocyclobutene resin, Melamine derivates, Polybenzoxabenzole (PBO), bismaleimide-triazine resin, polyphenylene derivate (e.g. based on polyphenylenether, PPE), polyimide (PI), polyamide (PA), liquid crystal polymer (LCP), polytetrafluoroethylene (PTFE), Bisbenzocyclobutene (BCB) and/or a combination thereof. Reinforcing structures such as webs, fibers, spheres or other kinds of filler particles, for example made of glass (multilayer glass) in order to form a composite, could be used as well. A semi-cured resin in combination with a reinforcing agent, e.g. fibers impregnated with the above-mentioned resins is called prepreg. These prepregs are often named after their properties e.g. FR4 or FR5, which describe their flame-retardant properties. Although prepreg particularly FR4 are usually preferred for rigid PCBs, other materials, in particular epoxy-based build-up materials (such as build-up films) or photoimageable dielectric materials, may be used as well. For high-frequency applications, high-frequency materials such as polytetrafluoroethylene, liquid crystal polymer and/or cyanate ester resins, may be preferred. Besides these polymers, low temperature cofired ceramics (LTCC) or other low, very low or ultra-low DK materials may be applied in the component carrier as electrically insulating structures.
In an embodiment, the at least one electrically conductive layer structure comprises at least one of the group consisting of copper, aluminum, nickel, silver, gold, palladium, tungsten and magnesium. Although copper is usually preferred, other materials or coated versions thereof are possible as well, in particular coated with supra-conductive material or conductive polymers, such as graphene or poly(3,4-ethylenedioxythiophene) (PEDOT), respectively.
The at least one component can be selected from a group consisting of an electrically non-conductive inlay, an electrically conductive inlay (such as a metal inlay, preferably comprising copper or aluminum), a heat transfer unit (for example a heat pipe), a light guiding element (for example an optical waveguide or a light conductor connection), an electronic component, or combinations thereof. An inlay can be for instance a metal block, with or without an insulating material coating (IMS-inlay), which could be surface mounted for the purpose of facilitating heat dissipation. Suitable materials are defined according to their thermal conductivity, which should be at least 2 W/mK. Such materials are often based, but not limited to metals, metal-oxides and/or ceramics as for instance copper, aluminum oxide (Al2O3) or aluminum nitride (AlN). In order to increase the heat exchange capacity, other geometries with increased surface area are frequently used as well. Furthermore, a component can be an active electronic component (having at least one p-n-junction implemented), a passive electronic component such as a resistor, an inductance, or capacitor, an electronic chip, a storage device (for instance a DRAM or another data memory), a filter, an integrated circuit (such as field-programmable gate array (FPGA), programmable array logic (PAL), generic array logic (GAL) and complex programmable logic devices (CPLDs)), a signal processing component, a power management component (such as a field-effect transistor (FET), metal-oxide-semiconductor field-effect transistor (MOSFET), complementary metal-oxide-semiconductor (CMOS), junction field-effect transistor (JFET), or insulated-gate field-effect transistor (IGFET), all based on semiconductor materials such as silicon carbide (SiC), gallium arsenide (GaAs), gallium nitride (GaN), gallium oxide (Ga2O3), indium gallium arsenide (InGaAs) and/or any other suitable inorganic compound), an optoelectronic interface element, a light emitting diode, a photocoupler, a voltage converter (for example a DC/DC converter or an AC/DC converter), a cryptographic component, a transmitter and/or receiver, an electromechanical transducer, a sensor, an actuator, a microelectromechanical system (MEMS), a microprocessor, a capacitor, a resistor, an inductance, a battery, a switch, a camera, an antenna, a logic chip, and an energy harvesting unit. However, other components may be surface mounted on the component carrier. For example, a magnetic element can be used as a component. Such a magnetic element may be a permanent magnetic element (such as a ferromagnetic element, an antiferromagnetic element, a multiferroic element or a ferrimagnetic element, for instance a ferrite core) or may be a paramagnetic element. However, the component may also be an IC substrate, an interposer, or a further component carrier, for example in a board-in-board configuration. The component may be surface mounted on the component carrier. Moreover, other components, in particular those which generate and emit electromagnetic radiation and/or are sensitive with regard to electromagnetic radiation propagating from an environment, may be used as a component.
In an embodiment, the component carrier is a laminate-type component carrier. In such an embodiment, the component carrier is a compound of multiple layer structures which are stacked and connected together by applying a pressing force and/or heat.
After processing interior layer structures of the component carrier, it is possible to cover (in particular by lamination) one or both opposing main surfaces of the processed layer structures symmetrically or asymmetrically with one or more further electrically insulating layer structures and/or electrically conductive layer structures. In other words, a build-up may be continued until a desired number of layers is obtained.
After having completed formation of a stack of electrically insulating layer structures and electrically conductive layer structures, it is possible to proceed with a surface treatment of the obtained layers structures or component carrier.
In particular, an electrically insulating solder resist may be applied to one or both opposing main surfaces of the layer stack or component carrier in terms of surface treatment. For instance, it is possible to form such a solder resist on an entire main surface and to subsequently pattern the layer of solder resist so as to expose one or more electrically conductive surface portions which shall be used for electrically coupling the component carrier to an electronic periphery. The surface portions of the component carrier remaining covered with solder resist may be efficiently protected against oxidation or corrosion, in particular surface portions containing copper.
It is also possible to apply a surface finish selectively to exposed electrically conductive surface portions of the component carrier in terms of surface treatment. Such a surface finish may be an electrically conductive cover material on exposed electrically conductive layer structures (such as pads, conductive tracks, etc., in particular comprising or consisting of copper) on a surface of a component carrier. If such exposed electrically conductive layer structures are left unprotected, then the exposed electrically conductive component carrier material (in particular copper) might oxidize, making the component carrier less reliable. A surface finish may then be formed for instance as an interface between a surface mounted component and the component carrier. The surface finish has the function to protect the exposed electrically conductive layer structures (in particular copper circuitry) and enable a joining process with one or more components, for instance by soldering. Examples for appropriate materials for a surface finish are Organic Solderability Preservative (OSP), Electroless Nickel Immersion Gold (ENIG), Electroless Nickel Immersion Palladium Immersion Gold (ENIPIG), gold (in particular hard gold), chemical tin, nickel-gold, nickel-palladium, etc.
The aspects defined above and further aspects of the disclosure are apparent from the examples of embodiment to be described hereinafter and are explained with reference to these examples of embodiment.
The illustrations in the drawings are schematically presented. In different drawings, similar or identical elements are provided with the same reference signs.
Before referring to the drawings, exemplary embodiments will be described in further detail, some basic considerations will be summarized based on which exemplary embodiments of the disclosure have been developed.
According to an exemplary embodiment of the disclosure, a Nanoimprint Lithography (NIL)-based design layer may be used as a basis for forming a wiring structure for a component carrier such as a printed circuit board. After stamping indentations in the still uncured design layer for defining the wiring structure by a working mold or the like, one or more indentations of such a profiled design layer may be filled with plural metallic constituents. More precisely, after (or during) stamping, the design layer may be cured and afterwards the metallic constituents will be formed. A bottom-sided metallic base structure may be covered by a top-sided electroplating structure with an optional seed layer therebetween. This may ensure a void-free filling or at least a filling with very low void-to-metal ratio. This may allow, in turn, to manufacture a component carrier with proper electric reliability. Moreover, constituting a filling of an indentation with at least two different separate metallic structures with individually selectable material or material composition may allow to fine-tune the properties of the metallic filling and to functionalize the wiring structures. In addition, the freedom and flexibility of material choice may be increased. Beyond this, a multi-structure metallic filling of an indentation of a profiled design layer may allow to reliably fill even very deep indentations. Highly advantageously, the metallic base structure may be formed by electroplating on a support in form of an electrically conductive layer exposed by a through hole-type indentation extending through the design layer.
A starting point of the manufacturing method according to
Referring to
In order to obtain the structure shown in
Thus, a surface profile may be stamped in the design layer 102. For this purpose, a working mold (not shown in
When there is an embedded trace, a surface finishing may be dispensable (in particular if it is covered by the NIL resist). Hence depending on the application, no solder resist or surface finishing may be needed.
As can be taken from
Advantageously, the design layer 102 may be cured simultaneously during the process of stamping. For this purpose, the working mold (preferably optically transparent, for instance made of glass, transparent, flexible, cross-linked silicone rubbers, and/or a combination of both) may be provided with a curing UV lamp configured for emitting UV radiation. More specifically, said UV lamp may emit UV radiation during imprinting indentations 108 in the design layer 102. This accelerates the manufacturing process and makes a subsequent curing procedure dispensable. As an alternative to a UV lamp, another optical emitter or a heat source may be used for curing. Such an optical emitter or heat source may be integrally formed together with the working mold or may be provided as a separate member. A device for stamping design layer 102 using a working mold is illustrated in
Under undesired circumstances it may happen that residues of the design layer 102 remain, after stamping by the working mold, in indentations 108 which shall be processed for creating a respective through hole 108′. Since this undesired phenomenon may be critical for a subsequent manufacturing process, it may be advantageously possible to remove, preferably by plasma etching, residues of the design layer 102 in at least one bottom region of the indentations 108 of the profiled design layer 102.
Referring to reference signs 154 in
As a result of the stamping, indentations 108 may be obtained which comprise through holes 108′ (which may later form metal filled vias) and blind holes 108″ (which may later form electrically conductive traces) characterized by different depths and different lengths in the design layer 102. An etching (preferably plasma etching) process may be carried out optionally to ensure that no residues of the design layer 102 remain at the bottoms of the through holes 108′.
Simultaneously with the profiling, or subsequently, the design layer 102 may be cured by subjecting the deformed design layer 102 to heat or appropriate electromagnetic radiation, such as UV radiation.
As a side remark and referring to
In the following, the manufacturing process will be further described based on the structure of
Referring to
As shown in
Referring to
Referring to
Structuring of the protection structure 106 is preferably done by the profiled design layer 102, i.e. by the previous NIL imprinting resulting in different resist heights. The protection structure 106—only of the top NIL resist layer coated with the metal seed layer 118—can be done with any non-selective, flat stamp coated with a thin film of protection ink, for example of few nanometer to few micrometer thickness. The flat, protective ink coated surface will only form contact with the highest surfaces of the profiled design layer 102 (i.e. NIL imprinted structures) on the panel. By taking this measure, it may be possible to make use of the fact that the profiled design layer 102 provides several levels of height by blocking selectively only the top layers.
Alternatively, a structuring of the protection structure 106 may be carried out by a lithography and etching process.
As explained above, the patterned protection structure 106 may advantageously avoid undesired overplating in a subsequent electroplating process and may render a complex and costly CMP process dispensable.
Referring to
It should be mentioned that a person skilled in the art is aware of the fact that, in a cross-sectional view of the structure shown in
Referring to
In an embodiment, the electroplating structure 110 may protrude beyond the design layer 102. More specifically, the NIL-pattern may protrude from the NIL-resist.
The electrically conductive wiring structures obtained as a result of the described manufacturing process are shown in a detail 158, in a detail 160 and in a detail 162 of
As illustrated in detail 158, through hole-type wiring structures 164 extending completely through profiled design layer 102 have tapering sidewalls. A bottom portion of a respective wiring structure 164 is constituted by bottom-sided portion of the metal base structure 122, wherein a top-sided portion of the metal base structure 122′ is formed directly on the bottom-sided portion 122. A remaining volume of the wiring structure 164 is lined with seed layer 118 covering a top surface of the metal base structure 122, 122′ as well as an exposed sidewall of the design layer 102. A remaining volume of the wiring structure 164 delimited by the seed layer 118 is filled with the electroplating structure 110.
As illustrated in detail 160, blind hole-type wiring structures 166 extending only partially through profiled design layer 102 have tapering sidewalls and a horizontal bottom surface. Both the latter mentioned tapering sidewalls as well as the horizontal bottom surface are lined with seed layer 118. A remaining volume of the wiring structure 166 delimited by the seed layer 118 is filled with the electroplating structure 110.
As illustrated in detail 162, through hole-type wiring structures 168 extending completely through profiled design layer 102 have tapering sidewalls with a stepped profile, a corresponding step being indicated by reference sign 170. Wiring structures 168 correspond to wiring structures 164 with the difference that the wiring structures 168 have step 170 between portions of the tapering sidewalls and therefore form a hybrid of a via-type wiring structure in a bottom portion and a trace-type wiring structure in a top portion.
As shown, fully embedded electrically conductive structures can be obtained, both of a via-type (see wiring structures 164) and of a trace-type (compare wiring structures 166), as well as a combination of both (compare wiring structures 168).
The structure shown in
Highly advantageously, the indentations 108 can be filled with two or more different metallic substructures (see reference signs 122, 122′, 118, 110) which may be made of two or more different metallic materials for fine-tuning the properties of the wiring structures 164, 166, 168. Alternatively, an entire wiring structure 164, 166, 168 may be filled with a single metallic material only, for example copper, with material interfaces in between.
As a result of the described manufacturing process, the illustrated component carrier 100 may be obtained. The component carrier 100 comprises the illustrated NIL-type and meanwhile cured design layer 102 in which a surface profile has been stamped. As shown, the electrically conductive seed layer 118 selectively lines portions of the indentations 108 of the stamped design layer 102. Furthermore, the metallic base structure 122, 122′ and the electroplating structure 110 are formed selectively in indentations 108, but not in between.
Said electroplating structure 110 forms, together with the metallic base structure 122, 122′ and assigned portions of the seed layer 118, electrically conductive sub-structures of different depth and different length in the design layer 102. More specifically, the electroplating structure 110, together with assigned portions of the seed layer 118, form trace-type wiring structures 166 (corresponding to indentations according to reference sign 108″). Via-type wiring structures 164 (corresponding to indentations according to reference sign 108′) are formed by the electroplating structure 110 together with assigned portions of the seed layer 118 and assigned portions of the metallic base structure 122, 122′. As shown in
As shown in
Furthermore, the wiring structures 164, 166, 168 have tapering sidewalls. This is a fingerprint of the tapering sidewalls of the protrusions of the working mold forming the indentations 108.
Advantageously, a roughness Ra of sidewall surfaces of the profiled design layer 102—and thus a roughness of sidewalls of electrically conductive structures defined by the seed layer 118, the metallic base structure 122, 122′ and the electroplating structure 110 being delimited by the surface profile formed in the design layer 102—may be not more than 50 nm. Also, this feature is the result of the formation of the indentations 108 by stamping using a working mold and leads to excellent high-frequency properties of the obtained component carrier 100.
Moreover, the illustrated component carrier 100 may be further processed, for instance for creating a further build-up of one or more PCB-type stacks (such as an IC substrate, an interposer or a PCB) of electrically conductive layer structures and/or electrically insulating layer structures on one or both opposing main surfaces of the design layer 102 according to
In the following, it will be described how, based on the structure shown in
Referring to
Referring to
As shown in
Referring to
Referring to
Referring to
As shown in
Referring to
Hence, component assembly and soldering may be carried out with high alignment accuracy (for instance better than 2 μm). Multi-die interconnection structures with a line space ratio L/S below 5 μm/5 μm may be possible. Thus, complex routing structures on very little space become possible.
According to
According to
In a further embodiment (not shown), at least one first pad of the pads 178 has a smaller pitch size than at least one second pad of the pads 178 having a larger pitch size, wherein the at least one first pad is electrically coupled with at least one first of the electrically conductive connection structures 180 on the design layer 102, and wherein the at least one second pad is electrically coupled with at least one second of the electrically conductive connection structures 180 on a laminated printed circuit board layer stack 131 (see
It is also possible to form a wiring structure 182 which extends partially horizontally and partially vertically between the electrically conductive connection structures 180 on the protrusion 176 and apart from the protrusion 176 on the design layer 102.
The embodiment of
According to
For instance, the shown embodiment can be implemented in terms of a chip last 3D manufacturing architecture. With three-dimensionally stamped NIL design layers 102, any slope required for any structure may be designed. Advantageously, stamping may lead to very smooth surfaces with a roughness Ra of less than 100 nm, or even of not more than 50 nm. Plated copper structures may be formed with high crystallinity and substantially without porosity.
In embodiments, one or more NIL-type design layers 102 may be further treated by three-dimensional printing. This may further extend the opportunities of NIL technology for manufacturing component carriers 100, such as printed circuit boards.
As shown, a planar uncured design layer 102 may be formed on a carrier 112 which may be transported along a support 186. Material of the design layer 102 may be applied to the carrier 112 from a reservoir 188. The working mold 152 may have a designable and preferably tapering surface profile 190 and may stamp an inverse and preferably tapering surface profile 192 in the design layer 102. For this purpose, the working mold 152 may for example rotate using rotating wheels 194 to thereby produce a continuous sheet with a stamped profiled design layer 102. By a light source 196 (such as a UV lamp), the design layer 102 may be cured during stamping.
In this embodiment, it is shown that a component carrier 100 with metal plated indentations 108 of one or more profiled design layers 102 can comprise straight or curved traces 163 of very different geometries. The illustrated possible shapes of the traces 163 are (from left to right) a cuboid shape, a convex or concave shape, a half cylindrical shape, a spherical shape, a T-shape (shown with two different aspect ratios), a combined cylindrical and frustoconical shape, and a combined rectangular and frustum shape. Creation of a huge plurality of other shapes is possible, in particular when a plurality of design layers 102 are stacked.
On a top side of said design layers 102, a first build-up 116 is formed which is composed of components 124 being surface mounted and electrically connected to the stacked profiled design layers 102 by solder structures 172 and being encapsulated in a mold compound 174.
On a bottom side of said design layers 102, a second build-up 116 is formed which comprises a laminated printed circuit board layer stack 131 (which can be, for example, a PCB, an IC substrate or an interposer). The illustrated laminated printed circuit board layer stack 131 may be composed of electrically conductive layer structures 133 and electrically insulating layer structures 135. For instance, the electrically insulating layer structures 135 may be parallel dielectric layers. For example, the electrically conductive layer structures 133 may comprise patterned copper foils (i.e. patterned metallic layers) and vertical through-connections, for example copper filled laser vias. The electrically insulating layer structures 135 may comprise a resin (such as epoxy resin), optionally comprising reinforcing particles therein (for instance glass fibers or glass spheres). For example, the electrically insulating layer structures 135 may be made of prepreg or FR4. The layer structures 133, 135 may be connected by lamination, i.e. the application of pressure and/or heat.
As shown, the integration density of wiring structures in said design layers 102 may be larger than in said laminated printed circuit board layer stack 131.
On a bottom side of the laminated printed circuit board layer stack 131, a mounting base 137 (such as a motherboard) with electrically conductive connection pads 139 may be connected mechanically and electrically by solder structures 172.
Hence,
The metallized design layers 102 form an advanced polymer substrate comprising three fan-out redistribution layers with smaller line space ratio L/S (for instance in a range from 0.5 to 5 μm/0.5 to 5 μm) on top. A larger line space ratio L/S (for instance in a range from 2 to 40 μm/2 to 40 μm, or even larger) may be provided for the substrate in form of laminated printed circuit board layer stack 131 below.
For example, the solder structures 172 may be embodied as solder balls or galvanic plated solder pillars (for instance with the composition of 66 weight % Cu, 33 weight % Sn, and less than 3 weight % Ag).
On a top side of said upper design layers 102, a first build-up 116 is formed which may be embodied as in
On a bottom side of said upper design layers 102, a second build-up 116 is formed which comprises a laminated printed circuit board layer stack 131, similar as in
On a bottom side of the laminated printed circuit board layer stack 131, lower design layers 102 are arranged.
On a bottom side of the lower design layers 102, a mounting base 137 (such as a motherboard) with one or more electrically conductive connection pads 139 may be connected mechanically and electrically by solder structures 172. Furthermore, additional components 124 may be surface mounted on a lower side of the lower design layers 102, for instance by solder structures 172. Additional electrically conductive layer structures 141 may be integrated in the mounting base 137. The solder structures 172 of
As shown, the integration density of wiring structures in each of said upper and lower design layers 102 may be larger than in said laminated printed circuit board layer stack 131.
Hence,
The upper metallized design layers 102 may form an advanced polymer substrate comprising three fan-out redistribution layers with smaller line space ratio L/S (for instance in a range from 0.5 to 5 μm/0.5 to 5 μm, or from 0.5 to 8 μm/0.5 to 8 μm) on top. A larger line space ratio L/S (for instance in a range from 5 to 15 μm/5 to 15 μm, or from 8 to 20 μm/8 to 20 μm) may be provided for the substrate in form of laminated printed circuit board layer stack 131 below.
The electrically conductive layer structures 141 of the mounting base 137 may have a line space ratio L/S (for instance in a range from 50 to 200 μm/50 to 200 μm, or even larger) being larger than the line space ratio L/S of the laminated printed circuit board plastic 131.
The lower metallized design layers 102 may have a line space ratio L/S for instance in a range from 0.5 to 5 μm/0.5 to 5 μm, or from 0.5 to 8 μm/0.5 to 8 μm.
A person skilled in the art will understand that the illustrated embodiments may omit certain features of component carriers for the sake of conciseness and for the sake of clarity. For example, further layers may be added, and finishing stages such as formation of a solder mask may be carried out although not described herein.
It should be noted that the term “comprising” does not exclude other elements or steps and the article “a” or “an” does not exclude a plurality. Also, elements described in association with different embodiments may be combined.
Implementation of the disclosure is not limited to the preferred embodiments shown in the figures and described above. Instead, a multiplicity of variants is possible which variants use the solutions shown and the principle according to the disclosure even in the case of fundamentally different embodiments.
This application is the U.S. national phase of International Application No. PCT/IB2021/062228 filed Oct. 29, 2021, the disclosure of which is hereby incorporated herein by reference.
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/IB2021/000942 | 10/29/2021 | WO |
