BACKGROUND
1. Field
The present application relates to a structure and a method for preparing a housing to accept a component for an embedded printed circuit board and for an inter-level interconnect system. The present invention in particular provides for a structure for an electrical interconnect for an embedded printed circuit board or for an embedded multilayered printed circuit board. In particular the present invention provides a mechanism for improving printed circuit board embedded component performance, ease of manufacture and the use of vertical space required for embedding components.
2. The Related Prior Art
The prior art establishes the electrical benefit of the embedded component, as documented in multiple publications from the inventors and other sources. Embedded component technology places commercially available components, such as surface mount ceramic capacitors, surface mount resistors, and surface mount inductors inside the printed circuit board and in close proximity to connecting integrated circuits or other components. This provides greater circuit density and better electrical performance due to the shorter electrical lengths.
Prior art for embedded components require that the material surrounding the components be non-circuit layers. This creates three electrical and mechanical concerns:
- 1. No electrically conductive layers may reside in the embedded component vertical region, making this vertical region wasted space in a dense pc board.
- 2. On high layer count designs, with an extremely thick vertical stack, embedded components are often not a possibility due to vertical thickness limitations in manufacturing or in application.
- 3. The wasted vertical space drives large line widths for signal traces within the pc board that connect to the embedded component. This impedes routing and signal fidelity for escapes through a via field with a tight pitch (such as a large BGA device mounted above the embedded component).
- 4. The wasted vertical space forces supply planes and ground planes to be farther away from surface devices or forces the embedded component to be further away, thus making it less effective due to longer electrical length resulting in high supply loop inductance.
- 5. It is difficult to position the very small components in the proper orientation in an embedded structure and keep them in place during the construction of the printed circuit board.
It would be desirable to provide structures that resolve the limiting concerns of the prior art by allowing the connection of power planes, ground planes, and signal layers to co-reside with the embedded component and ease orientation of the components and to keep them in place through processing.
SUMMARY
The present invention provides a structure and a method for an electrical interconnect structure for a single or multilayered printed circuit board to create a reliable high performance connection between signal traces and power/ground plane or planes that occupy the same vertical space as an embedded component such as a capacitor or a resistor. The present invention provides for a sub-lamination containing the embedded component that may have a number of metallic and non-conductive layers, as required by the application while easing the orientation and securing the component through the manufacturing process. This is a critical difference between this disclosure and prior art. The component terminals connect to these layers electrically through plating, micro-machining, and the use of conductive materials.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a first embodiment of the present invention for a single layer, two sided or subassembly of an embedded printed circuit board (PCB);
FIG. 2 is the first embodiment shown in FIG. 1 with lamination and cure of the embedded PCB or subassembly;
FIG. 3 is a second embodiment of the present invention with unclad dielectric carrier built-up on a single, or multilayer PCB;
FIG. 4 is a third embodiment of the present invention wherein internal or external layers of the carrier are connected to end points or terminals of embedded components of either a single or multilayer PCBs; and
FIG. 5 is a fourth embodiment of the present invention wherein instead of having internal or external layers connected to end points or terminals of embedded components of either a single or multilayer PCBs as in FIG. 4, adjacent vias are provided to bring the internal layer connections to the top or bottom of the dielectric material for solder, conductive paste or sinter paste bridging between the adjacent vias pad and the end point or terminals of the embedded component;
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
Referring now to the drawings of FIGS. 1-5, FIGS. 1-2 describe a first embodiment of the present invention in which a lamination adhesive or prepreg 2 is applied to a conductive foil 3 preferably a copper foil with the adhesive being partially cured as to provide adhesion to the foil but also allow it to flow again through additional lamination steps. This partial cure time, pressure and temperature will be dependent on the types of adhesive and vary from application to application but for purposes of a non-limiting example an Issola FR408 1080 prepreg requires approximately 125 pounds per square inch pressure, at 155 degrees Fahrenheit for 30 minutes. Vias 9 are formed through the adhesive 2 to expose the copper foil 3. It is understood that these vias may be formed with laser drilling, mechanically drilling, plasma etching, use of photo definable liquid dialectic or any other methods known in the art. The vias 9 are filled with conductive epoxy, sintering paste or solder paste 4. An unclad dielectric material 1 with cut outs 6 of an approximate shape, preferably slightly larger (1 to 3 mils), than the intended embedded component or components 5, with the proper orientation is/are tack bonded or laminated as shown in FIG. 2. The approximate shapes and sizes of the cut outs 6 for the present invention can vary and be any shape or preferred geometric shape including preferably but not limited to rectangular shapes. This partial cure time, pressure and temperature will be dependent on the types of adhesive and will vary with the type and thickness of the particular prepeg chosen based on the known manufacturing specifications for that chosen prepeg but by way of a non-limiting illustrative example the present invention can use but is not limited to using an Issola FR408 1080 prepreg that requires approximately 75 pounds per square inch pressure, at 150 degrees Fahrenheit for 14 minutes. The said cuts outs in the said unclad material as well as the said unclad material when bonded is/are oriented in order to locate the end points or terminals of the intended embedded components 5 to the vias 9 that are filled with paste 4.
The unclad dielectric material 1 with cutouts 6 are populated with components 5 using the cutouts 6 as a guide and a protective housing to keep the components 5 in place for the next operation. Next, another copper foil 3 is prepared similar to the first foil with conductive paste, sintering paste or solder 4 in the vias 9. It is aligned to the top of the unclad dielectric material 1 such that the vias 9 of the second foil are aligned to the end points or terminals of the opposite side of the embedded components 5 and the paste 4 is in contact with the terminals of the components 5. The second foil is then laminated to the top of the unclad material 1 through a curing process. This final cure time, temperature and pressure will be dependent on the types of adhesive but for purposes of a non-limiting example an Issola FR408 1080 prepreg requires approximately 200 PSI, at 376F for 90 minutes.
In another embodiment of the present invention as shown in FIG. 3 either or both of the foils described could be replaced with single or multilayered printed circuit boards or subassemblies. These subassemblies pads and or vias would be aligned to the end points or terminals of the embedded components 5 to provide electrical connection through the subassembly circuits and the embedded components 5.
In a third embodiment of the present invention shown in FIG. 4 the unclad dielectric material 1 could be a single or multilayered printed circuit board with internal and/or external, power, ground and signal layers and optionally through blind or buried vias. Further, these internal and or external layers may be connected to the end points or terminals of the embedded components through selective metal plating the side walls 11 of the cutouts 6 that house the embedded components 5. Alternatively as shown in the embodiment of FIG. 5 adjacent vias 12 can be provided that bring the internal layer connections to the top or bottom of the dielectric material 1 for solder, conductive paste or sinter paste 4 bridging between the adjacent vias or pads 12 and the end point or terminals of the embedded components 5. In the structure of FIG. 4 however, unlike the alternative embodiment described below for FIG. 5, the cavities or cutouts 6 for the embedded components 5 are micro-machined prior to plating. The entire cut out 6 is thus plated and completes the normal printed circuit board process for the sub-lamination. This electrically shorts all connecting points for component 5 terminals together. Prior to component 5 insertion into the cavity 6, a micro-machining step cuts away electrically conductive metal plating between the terminal connections in the printed circuit board. This electrically isolates each pad appropriately. The commercially available component 5 is then inserted into the cavity 6 and pressed flat. The sub-lamination booklet is then completed with build-up layers—first non-conductive layers, followed by a metallic pad layer, and then heat pressed and cured. The non-conductive layer was first micro-machined with openings or vias, followed by a conductive attach material being placed into these openings or vias. The component 5 thus attaches to the plated side-walls 11 and/or to outer plating (metallic pads) during the curing process of the booklet/sub-lamination whereby the conductive attached material 4 (i.e. conductive epoxies, sintered pastes, solder paste) bridge the plated side wall and end points of the component 5. In the embodiment of FIG. 4, the single or multilayer PCB1A. aligns the embedded component or components to the paste or solder 4. The structure of the embodiment of FIG. 4 of the present invention uses a printed circuit board sub-lamination created to be approximately the same thickness or slightly thinner by ˜0.001 as the targeted commercially available component. FIG. 4 shows an alternate embodiment in which the structure is nearly identical to the process for the structure in FIG. 5. The sub-lamination contains any number of metallic and non-conductive layers, as required by the application. At the ends of the terminal locations of the proposed embedded component 5, drilled and plated through vias or blind vias exist. A precision micro-drilling mechanism cuts an appropriate opening the size and shape of the component 5 to be embedded. The micro-machining method may cut in approximately half or castellate the via, leaving one-half of it intact. Alternatively, the cut out end points can come into close proximity to the vias then the commercially available component 5 is inserted into the cavity 6 and pressed flat. The sub-lamination booklet is then completed with surface build-up layers—first non-conductive layers, followed by a metallic pad layer, and then heated, pressed and cured. The non-conductive layer was first micro-machined with openings, followed by a conductive attach material being placed into these openings. The embedded component 5 thus attaches to the cut out or castellated vias 6 or to the outer plating (metallic pads) during the curing process of the booklet/sub-lamination whereby the conductive adhesive (i.e. conductive epoxies, sintered pastes, solder paste) bridge the pads and or half vias and end points of the component 5.
While presently preferred embodiments have been described for purposes of the disclosure, numerous changes in the arrangement of method steps and apparatus parts can be made by those skilled in the art. Such changes are encompassed within the spirit of the invention as defined by the appended claims.
Patent Application
20150319863
