Claims
- 1. A structure comprising:
a monocrystalline substrate; an accommodating buffer layer formed on the substrate; a template formed above the accommodating buffer layer; and a cubic boron nitride layer formed overlying the first template.
- 2. The structure of claim 1, wherein the template includes a surfactant.
- 3. The structure of claim 2, wherein the surfactant is selected from the group consisting of aluminum, indium, and gallium.
- 4. The structure of claim 1, wherein the template includes a cap layer.
- 5. The structure of claim 4, wherein the cap layer comprises at least one of As, P, Sb, and N.
- 6. The structure of claim 1, wherein the accommodating buffer layer is monocrystalline.
- 7. The structure of claim 6, further comprising an amorphous interface layer interposed between the monocrystalline substrate and the accommodating buffer layer.
- 8. The structure of claim 1, wherein the accommodating buffer layer is amorphous.
- 9. The structure of claim 1, wherein the accommodating buffer layer comprises an oxide selected from the group consisting of alkaline earth metal titanates, alkaline earth metal zirconates, alkaline earth metal hafniates, alkaline earth metal tantalates, alkaline earth metal ruthenates, and alkaline earth metal niobates.
- 11. The structure of claim 10, wherein the accommodating buffer layer comprises SrxBa1-xTiO3, where x ranges from 0 to 1.
- 12. The structure of claim 1, wherein the accommodating buffer layer comprises an oxide formed as a monocrystalline oxide and subsequently heat treated to convert the monocrystalline oxide to an amorphous oxide.
- 13. The structure of claim 1, wherein the monocrystalline substrate comprises silicon.
- 14. The structure of claim 1, wherein the accommodating buffer layer has a thickness of about 2-10 nm.
- 15. The structure of claim 1, further comprising a microelectronic device formed using the cubic boron nitride layer.
- 16. The structure of claim 1, further comprising a microelectronic device formed using the monocrystalline substrate.
- 17. A process for fabricating a structure comprising the steps of:
providing a monocrystalline substrate; epitaxially growing a monocrystalline accommodating buffer layer overlying the monocrystalline substrate; forming a first amorphous layer between the monocrystalline substrate and the monocrystalline accommodating buffer layer during the step of epitaxially growing; forming a cubic boron nitride layer above the monocrystalline accommodating buffer layer.
- 18. The process of claim 17, further comprising the step of annealing the monocrystalline accommodating buffer layer to form an amorphous accommodating buffer layer.
- 19. The process of claim 17, further comprising the step of forming a template layer on the monocrystalline accommodating buffer layer.
- 20. The process of claim 19, wherein the step of forming a template includes forming a layer comprising aluminum.
- 21. The process of claim 17, wherein the step of forming a cubic boron nitride layer includes using chemical vapor deposition techniques.
- 22. The process of claim 17, wherein the step of forming a cubic boron nitride layer includes using rf magnetron sputtering techniques.
- 23. The process of claim 17, further comprising the step of forming a microelectronic device using the cubic boron nitride layer.
- 24. The process of claim 17, further comprising the step of forming a microelectronic device using the monocrystalline substrate.
- 25. An integrated circuit comprising:
a substrate; an accommodating buffer layer overlying the substrate; a cubic boron nitride layer overlying the accommodating buffer layer; and a microelectronic device formed using the cubic boron nitride layer.
- 26. The integrated circuit of claim 25, wherein the microelectronic device includes a semiconductor device.
- 27. The integrated circuit of claim 25, further comprising a microelectronic device formed using the substrate.
CROSS REFERENCE TO RELATED APPLICATIONS
[0001] The present application is a continuation-in-part of U.S. patent application Ser. No. 09/607,207 entitled “Semiconductor Structure, Semiconductor Device, Communicating Device, Integrated Circuit, and Process for Fabricating the Same”, filed Jun. 28, 2000, by the assignee hereof.
Continuation in Parts (1)
|
Number |
Date |
Country |
Parent |
09607207 |
Jun 2000 |
US |
Child |
09824376 |
Apr 2001 |
US |