Claims
- 1. A controller adapted to generate different clock pulses for read and write operations.
- 2. The controller of claim 1, wherein at least one of said different clock pulses is based on a received signal.
- 3. The controller of claim 1, wherein at least one of said different clock pulses is extended.
- 4. The controller of claim 1 further adapted to skew at least one pre-charge signal for at least a read operation.
- 5. A memory device comprising:
at least one local memory block; and a global controller coupled to at least said local memory block and adapted to manage timing of read and write operations
- 6. The memory device of claim 5, wherein said global controller is synchronously controlled.
- 7. The memory device of claim 5, wherein said global controller is further adapted to extend a portion of a clock pulse.
- 8. The memory device of claim 5, wherein said local memory block comprises at least one memory cell.
- 9. The memory device of claim 5, wherein said local memory block comprises at least one local decoder.
- 10. The memory device of claim 5, wherein said local memory block comprises at least one local sense amp.
- 11. The memory device of claim 5, wherein said local memory block comprises at least one local controller.
- 12. A memory structure comprising:
a synchronously controlled global element comprising at least one synchronously controlled global controller adapted to extend a portion of at least one clock pulse; and a self-timed local element comprising at least one local memory block, wherein at least said local memory block is adapted to communicate with said global controller.
- 13. The memory structure device of claim 12, wherein said global element further comprises a global predecoder.
- 14. The memory structure of claim 12, wherein said global element further comprises at least one global decoder.
- 15. The memory structure of claim 12, wherein said global element comprises at least one global sense amp.
- 16. The memory structure of claim 12, wherein said local memory block comprises a plurality of memory cells.
- 17. The memory structure of claim 12, wherein said local memory block comprises at least one local decoder.
- 18. The memory structure of claim 12, wherein said local memory block comprises at least one local sense amplifier.
- 19. The memory structure of claim 12, wherein said local memory block comprises at least one local controller.
- 20. A method for processing read and write operations in a memory architecture having a synchronous global controller, the method comprising:
generating control signals; and managing timing during the read and write operations.
- 21. The method of claim 20, wherein managing said timing during the read and write operation includes skewing at least one clock pulse.
- 22. The method of claim 20, wherein the read and write operations are completed in a single cycle.
- 23. The method of claim 22, wherein said single cycle is faster than an external clock cycle.
- 24. A method for processing read and write operations in a memory architecture comprising skewing a clock pulse using a global controller.
- 25. The method of claim 24, wherein skewing said clock pulse includes extending a high portion of said clock pulse using at least one word line interfacing with said global controller.
CROSS REFERENCE TO RELATED APPLICATIONS
[0001] This application is a continuation-in-part of, and claims benefit of and priority from, application Ser. No. 10/100,757, Filed Mar. 19, 2002, titled “Synchronous Controlled, Self-Timed Local SRAM Block”, the complete subject matter of which is incorporated herein by reference in its entirety.
Continuation in Parts (1)
|
Number |
Date |
Country |
Parent |
10100757 |
Mar 2002 |
US |
Child |
10177311 |
Jun 2002 |
US |