The present disclosure relates generally to electronic packaging and, more particularly, to a technique for improving power and ground flooding.
Multilayer circuit boards were developed to overcome area limitations associated with single-layered circuit boards. A multilayer circuit board can be either single- or double-sided, and may comprise multiple signal layers on the surface of and buried within the board. Such multilayer circuit boards have allowed a significant increase in the number of electrical signals that may be routed between electronic components mounted on the same circuit board. Thus, electronic components with a large number of input/output (I/O) pins may be mounted on a single circuit board. And sophisticated micro-systems may be delivered in multi-chip packages.
As the number of pin-outs increases, often accompanied by a decrease in pin pitch, it has become more and more difficult to achieve full power and ground flooding within a package. For example, due to high pin density, space limitations can make it impossible to route a trace to a power/ground pin. Even if a trace may be routed for a power/ground connection, it is often too thin for sufficient current to flow through. A high-density package also tends to have more severe electromagnetic interference (EMI) among its components. Sufficient ground flooding of the package is usually crucial to an effective containment of EMI.
Furthermore, high-density packages with multilayer circuit boards can produce a substantial amount of heat even during normal operations. Excessive heat tends to deteriorate the performance of electronic components and shorten their lifetime. Therefore, preventative measures become necessary to help dissipate excessive heat. However, space limitations within a multilayer circuit board often hinders the implementation of heat-dissipating measures.
Referring to
One prior art solution for providing ground flooding for the ground vias is illustrated in
In view of the foregoing, it would be desirable to provide a solution for power and ground flooding in multilayer circuit boards which overcomes the above-described inadequacies and shortcomings.
A technique for improving power and ground flooding is disclosed. In one particular exemplary embodiment, the technique may be realized as a method for improving power and ground flooding in a multilayer circuit board, the multilayer circuit board having a plurality of signal layers. The method may comprise forming a plurality of electrically conductive vias, wherein each of the plurality of electrically conductive vias extends through one or more of the plurality of signal layers. The method may also comprise routing signals associated with the plurality of electrically conductive vias, thereby creating at least one power/ground flooding channel. The method may additionally comprise forming at least one power/ground connection within the at least one power/ground flooding channel.
In accordance with other aspects of this particular exemplary embodiment, the at least one power/ground flooding channel may be substantially wider than a pitch between two adjacent electrically conductive vias.
In accordance with further aspects of this particular exemplary embodiment, the step of routing signals associated with the plurality of electrically conductive vias may comprise at least two stages of channel routing process.
In accordance with additional aspects of this particular exemplary embodiment, the signals associated with the plurality of electrically conductive vias may be routed within the multilayer circuit board, to and from at least one electronic component mounted on a surface of the multilayer circuit board, or to and from a second circuit board.
In accordance with a further aspect of this particular exemplary embodiment, the at least one power/ground connection may be terminated at a power/ground plane.
In accordance with a yet further aspect of this particular exemplary embodiment, the multilayer circuit board may comprise a power/ground patch, the power/ground patch having electrical contact with a plurality of power/ground vias. And the at least one power/ground connection may provide power/ground flooding for the power/ground patch.
In accordance with a still further aspect of this particular exemplary embodiment, the method may further comprise providing thermal dissipation and/or mechanical support for the multilayer circuit board based at least in part on the at least one power/ground flooding channel.
In another particular exemplary embodiment, the technique may be realized by a multilayer circuit board with improved power and ground flooding. The multilayer circuit board may comprise a plurality of signal layers. The multilayer circuit board may also comprise a plurality of electrically conductive vias, wherein each of the plurality of electrically conductive vias extends through one or more of the plurality of signal layers. The multilayer circuit board may additionally comprise at least one power/ground flooding channel, wherein the at least one power/ground flooding channel is created by routing signals associated with the plurality of electrically conductive vias. The multilayer circuit board may further comprise at least one power/ground connection formed within the at least one power/ground flooding channel.
In accordance with other aspects of this particular exemplary embodiment, the at least one power/ground flooding channel may be substantially wider than a pitch between two adjacent electrically conductive vias.
In accordance with further aspects of this particular exemplary embodiment, the at least one power/ground flooding channel may be created based on at least two stages of channel routing process.
In accordance with additional aspects of this particular exemplary embodiment, the signals associated with the plurality of electrically conductive vias may be routed within the multilayer circuit board, to and from at least one electronic component mounted on a surface of the multilayer circuit board, or to and from a second circuit board.
In accordance with a further aspect of this particular exemplary embodiment, the at least one power/ground connection may be terminated at a power/ground plane.
In accordance with a yet further aspect of this particular exemplary embodiment, the multilayer circuit board may comprise a power/ground patch, the power/ground patch having electrical contact with a plurality of power/ground vias. And the at least one power/ground connection may provide power/ground flooding for the power/ground patch.
In accordance with a still further aspect of this particular exemplary embodiment, the multilayer circuit board may further comprise one or more thermal dissipation and/or mechanical support structures for the multilayer circuit board based at least in part on the at least one power/ground flooding channel.
The present disclosure will now be described in more detail with reference to exemplary embodiments thereof as shown in the accompanying drawings. While the present disclosure is described below with reference to exemplary embodiments, it should be understood that the present disclosure is not limited thereto. Those of ordinary skill in the art having access to the teachings herein will recognize additional implementations, modifications, and embodiments, as well as other fields of use, which are within the scope of the present disclosure as described herein, and with respect to which the present disclosure may be of significant utility.
In order to facilitate a fuller understanding of the present disclosure, reference is now made to the accompanying drawings, in which like elements are referenced with like numerals. These drawings should not be construed as limiting the present disclosure, but are intended to be exemplary only.
Referring to
In step 400, a plurality of electrically conductive vias may be formed in a multilayer circuit board. The multilayer circuit board may comprise a number of layers that are electrically isolated from one another. Different layers inside a multilayer circuit board may be adapted to different functions. For example, a multilayer circuit board may have a primary (top) layer and a secondary (bottom) layer. These layers are usually adapted to have one or more electrical components mounted thereon. Some layers are implemented primarily for routing signals other than power or ground signals, such as test signals, clock signals, etc. And some layers serve the main purpose of routing power and/or ground signals. All these layers in a multilayer circuit board may be collectively referred to as “signal layers.”
Depending on the needs for signal routing and the mounted electronic component, electrically conductive vias may be formed in the circuit board. Some vias (i.e., supervias) may be thru-holes extending from one surface of the circuit board to the opposite surface. Some vias (i.e., microvias or blind vias) may connect two or more of the signal layers without extending through the whole circuit board. Other vias, such as buried vias, may connect two or more signal layers without extending to either surface of the circuit board. Based on the type of signal associated therewith, a via may be categorized as a signal via (for signals other than power or ground) or a power/ground via (for power or ground signals), for example.
In step 402, one or more flooding paths may be identified for power/ground vias that require improved flooding. In a high-density multilayer circuit board, flooding problems may be identified for portions of the board that are affected by large current, excessive heat and/or EMI. Since power/ground flooding is typically implemented to provide sufficient contact to a power/ground plane, it may be desirable to identify flooding paths in a power/ground layer that would provide effective power/ground access to power/ground vias that require flooding. A flooding path is typically of sufficient width to accommodate placement of connections carrying large currents.
Once the flooding paths have been identified in the power/ground layer, it may be necessary to clear these paths for subsequent signal routing processes. That is, selected vias may need to be removed or relocated from the flooding paths. Thus, in step 404, signal routing channels may be created for the selected vias in some other signal layers. Creation of these via-free channels may be based on the channel routing techniques disclosed in the related patent applications which are incorporated herein in their entirety.
In step 406, signals associated with the selected vias may be routed to create via-free flooding channels in the power/ground layer. Step 406 may be another channel routing step utilizing the via-free signal routing channels created in step 404. It may be beneficial to implement two or more stages of a channel routing process, each stage creating signal routing channels for a next stage. As a result, via-free flooding channels of sufficient width may be created.
In step 408, electrical connections may be formed in the via-free flooding channels, interconnecting the power/ground vias with the power/ground plane. The electrical connections may be wires or bands formed out of highly conductive metal such as copper, aluminum, platinum or gold.
The electrical connections for power/ground flooding may, to some extent, relieve the problem of excessive heat. Optionally, in step 410, thermal dissipation measures may be provided for the multilayer circuit board based on the via-free flooding channels. For example, structures comprising thermally conductive materials may be formed in the flooding channels to help dissipate excessive heat.
As shown in
As a result of the signal routing in the first signal layer 500, additional via-free channels 602 may be created in corresponding locations in the second signal layer 600 shown in
Although
The present disclosure is not to be limited in scope by the specific embodiments described herein. Indeed, other various embodiments of and modifications to the present disclosure, in addition to those described herein, will be apparent to those of ordinary skill in the art from the foregoing description and accompanying drawings. Thus, such other embodiments and modifications are intended to fall within the scope of the following appended claims. Further, although the present disclosure has been described herein in the context of a particular implementation in a particular environment for a particular purpose, those of ordinary skill in the art will recognize that its usefulness is not limited thereto and that the present disclosure can be beneficially implemented in any number of environments for any number of purposes. Accordingly, the claims set forth below should be construed in view of the full breadth and spirit of the present disclosure as described herein.
This patent application claims priority to U.S. Provisional Patent Application No. 60/477,923, filed Jun. 13, 2003, which is hereby incorporated by reference herein in its entirety. This patent application is a continuation-in-part of U.S. patent application Ser. No. 10/101,211, filed Mar. 20, 2002, which is a continuation-in-part of U.S. patent application Ser. No. 09/651,188, filed Aug. 30, 2000, now U.S. Pat. No. 6,388,890, which claims priority to U.S. Provisional Patent Application No. 60/212,387, filed Jun. 19, 2000. All of these related patent applications are hereby incorporated by reference herein in their entirety.
Number | Name | Date | Kind |
---|---|---|---|
5006820 | Prioste et al. | Apr 1991 | A |
5281151 | Arima et al. | Jan 1994 | A |
5451721 | Tsukada et al. | Sep 1995 | A |
5544018 | Sommerfeldt et al. | Aug 1996 | A |
5686764 | Fulcher | Nov 1997 | A |
5784262 | Sherman | Jul 1998 | A |
5847936 | Forehand et al. | Dec 1998 | A |
6181004 | Koontz et al. | Jan 2001 | B1 |
6194668 | Horiuchi et al. | Feb 2001 | B1 |
6198635 | Shenoy et al. | Mar 2001 | B1 |
6232564 | Arndt et al. | May 2001 | B1 |
6256769 | Tamarkin et al. | Jul 2001 | B1 |
6271478 | Horiuchi et al. | Aug 2001 | B1 |
6310398 | Katz | Oct 2001 | B1 |
6335493 | Horiuchi et al. | Jan 2002 | B1 |
6388890 | Kwong et al. | May 2002 | B1 |
6407343 | Tanaka | Jun 2002 | B1 |
6452262 | Juneja | Sep 2002 | B1 |
6489574 | Otaki et al. | Dec 2002 | B1 |
6521846 | Freda et al. | Feb 2003 | B1 |
6707685 | Kabumoto et al. | Mar 2004 | B2 |
6720501 | Henson | Apr 2004 | B1 |
6909052 | Haug et al. | Jun 2005 | B1 |
6916995 | Seaman et al. | Jul 2005 | B2 |
20030043560 | Clarkson et al. | Mar 2003 | A1 |
Number | Date | Country |
---|---|---|
1 087 440 | Mar 2001 | EP |
2782230 | Feb 2000 | FR |
H05-54103 | Mar 1993 | JP |
H07-141409 | Jun 1995 | JP |
H10-134098 | May 1998 | JP |
H11-297885 | Oct 1999 | JP |
2001-034643 | Feb 2001 | JP |
2001-274288 | Oct 2001 | JP |
2001-351983 | Dec 2001 | JP |
Number | Date | Country | |
---|---|---|---|
20040216916 A1 | Nov 2004 | US |
Number | Date | Country | |
---|---|---|---|
60477923 | Jun 2003 | US | |
60212387 | Jun 2000 | US |
Number | Date | Country | |
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Parent | 10101211 | Mar 2002 | US |
Child | 10861387 | US | |
Parent | 09651188 | Aug 2000 | US |
Child | 10101211 | US |