Patent Application
20240222298
The demand for miniaturization of form factor and increased level of integration for high performance are driving sophisticated packaging techniques in the semiconductor industry. Die partitioning enables miniaturization of small form factor and high performance without yield issues, but such an approach requires fine die to die connections. Bridge dies that provide fine interconnects between other dies can enable lower cost packaging.
For fine bump pitches, a die first approach can be used. In a die first approach, a die is placed face up, and components such as redistribution layers are patterned directly on the die. However, any yield loss in forming the redistribution layers is costly, as it requires that the die be discarded.
In various embodiments disclosed herein, part of an integrated circuit component can be manufactured by building up components such as a redistribution layer directly on a integrated circuit die. A release layer is formed on the die before the redistribution layer. The release layer is made of components with a melting point that is above the processing temperature to make the redistribution layer and below a temperature which will damage the die. As a result, if the redistribution layer or other component built up on the die is faulty, the faulty components can be removed, and the die can be reused, increasing yield. The release layer including both conductive and dielectric parts, providing electrical connections and isolation, as required.
As used herein, the phrase “communicatively coupled” refers to the ability of a component to send a signal to or receive a signal from another component. The signal can be any type of signal, such as an input signal, an output signal, or a power signal. A component can send or receive a signal to another component to which it is communicatively coupled via a wired or wireless communication medium (e.g., conductive traces, conductive contacts, air). Examples of components that are communicatively coupled include integrated circuit dies located in the same package that communicate via an embedded bridge in a package substrate and an integrated circuit component attached to a printed circuit board that send signals to or receives signals from other integrated circuit components or electronic devices attached to the printed circuit board.
In the following description, specific details are set forth, but embodiments of the technologies described herein may be practiced without these specific details. Well-known circuits, structures, and techniques have not been shown in detail to avoid obscuring an understanding of this description. Phrases such as “an embodiment,” “various embodiments,” “some embodiments,” and the like may include features, structures, or characteristics, but not every embodiment necessarily includes the particular features, structures, or characteristics. Moreover, such phrases are not necessarily referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the knowledge of one skilled in the art to effect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described. Additionally, it should be appreciated that items included in a list in the form of “at least one A, B, and C” can mean (A); (B); (C); (A and B); (A and C); (B and C); or (A, B, and C). Similarly, items listed in the form of “at least one of A, B, or C” can mean (A); (B); (C); (A and B); (A and C); (B and C); or (A, B, and C).
Some embodiments may have some, all, or none of the features described for other embodiments. “First,” “second,” “third,” and the like describe a common object and indicate different instances of like objects being referred to. Such adjectives do not imply objects so described must be in a given sequence, either temporally or spatially, in ranking, or any other manner. “Connected” may indicate elements are in direct physical or electrical contact, and “coupled” may indicate elements co-operate or interact, but they may or may not be in direct physical or electrical contact. Furthermore, the terms “comprising,” “including,” “having,” and the like, as used with respect to embodiments of the present disclosure, are synonymous. Terms modified by the word “substantially” include arrangements, orientations, spacings, or positions that vary slightly from the meaning of the unmodified term. For example, the central axis of a magnetic plug that is substantially coaxially aligned with a through hole may be misaligned from a central axis of the through hole by several degrees. In another example, a substrate assembly feature, such as a through width, that is described as having substantially a listed dimension can vary within a few percent of the listed dimension.
It will be understood that in the examples shown and described further below, the figures may not be drawn to scale and may not include all possible layers and/or circuit components. In addition, it will be understood that although certain figures illustrate transistor designs with source/drain regions, electrodes, etc. having orthogonal (e.g., perpendicular) boundaries, embodiments herein may implement such boundaries in a substantially orthogonal manner (e.g., within +/−5 or 10 degrees of orthogonality) due to fabrication methods used to create such devices or for other reasons.
Reference is now made to the drawings, which are not necessarily drawn to scale, wherein similar or same numbers may be used to designate the same or similar parts in different figures. The use of similar or same numbers in different figures does not mean all figures including similar or same numbers constitute a single or same embodiment. Like numerals having different letter suffixes may represent different instances of similar components. The drawings illustrate generally, by way of example, but not by way of limitation, various embodiments discussed in the present document.
In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding thereof. It may be evident, however, that the novel embodiments can be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form in order to facilitate a description thereof. The intention is to cover all modifications, equivalents, and alternatives within the scope of the claims.
As used herein, the phrase “located on” in the context of a first layer or component located on a second layer or component refers to the first layer or component being directly physically attached to the second part or component (no layers or components between the first and second layers or components) or physically attached to the second layer or component with one or more intervening layers or components.
As used herein, the term “adjacent” refers to layers or components that are in physical contact with each other. That is, there is no layer or component between the stated adjacent layers or components. For example, a layer X that is adjacent to a layer Y refers to a layer that is in physical contact with layer Y.
Referring now to
The illustrative substrate 104 may be embodied as a circuit board made from ceramic, glass, and/or organic-based materials with fiberglass and resin, such as FR-4. The circuit board 104 may have any suitable length or width, such as 10-500 millimeters. The circuit board 104 may have any suitable thickness, such as 0.2-5 millimeters. The circuit board 104 may support additional components besides the die assembly 102, such as additional electronic or photonic integrated circuit components, a processor unit, a memory device, an accelerator device, etc. The substrate 104 may embodied as any other suitable material, such as silicon. The integrated circuit component 100 may include a mid-level interconnect that connects to a substrate or a second-level interconnect that connects to a board, such as a motherboard. In some embodiments, the integrated circuit component 100 may not include a separate substrate 104.
As shown in
Referring now to
The redistribution layer 212 is configured to provide electrical interconnect between various components of the integrated circuit component, such as between the dies 202, between the bridge die 216 and the dies 202, between the dies 202 and the bumps 220, etc.
Below the redistribution layer 212, in the illustrative embodiment, is a bridge layer 214. The bridge layer 214 includes a bridge die 216, which is connected to the dies 202 and other interconnects such as the bumps 220. The bridge die 216 provides interconnect circuitry for connections between the dies 202. The bridge die 216 may be embodied as, e.g., an embedded multi-die interconnect bridge (EMIB) or an omni-directional interconnect (ODI). The bridge layer 214 may also include pillars connecting the redistribution layer 212 to another interconnect layer, such as a backside redistribution layer 218. In some embodiments, a bridge die 216 or bridge layer 214 may not be included.
The backside redistribution layer 218 provides interconnects between the bridge layer 214 and solder bumps 220. The solder bumps 220 may connect to the substrate 104. It should be appreciated that, in some embodiments, some or all of the layers 212, 214, 218 may not be present, and/or additional layers may be present. For example, in one embodiment, a backside redistribution layer 218 and solder bumps 220 may be patterned directly on the release layer 211.
As discussed below in more detail, the redistribution layer 212, bridge layer 214, and backside redistribution layer 218 are all built up on the dies 202. Such an approach can improve performance, allowing for, e.g., denser interconnect connections with the dies 202. However, if one of the components of the redistribution layer 212, bridge layer 214, backside redistribution layer 218, etc., is faulty, then the die assembly 102 cannot be used. As the dies 202 are often the most costly component of the die assembly 102, reusing the dies 202 would be beneficial. In order to allow for the dies 202 to be removed from the rest of the die assembly 102 and reused, the release layer 211 is designed to allow the dies 202 to be removed from the rest of the die assembly. The illustrative release layer 211 is made of materials with a melting point between a process temperature for applying the redistribution layer 212, etc., and a temperature at which components of the die 202 may sustain damage. The maximum processing temperature for adding the redistribution layer 212, etc., may be, e.g., 250-300° C. In the illustrative embodiment, the maximum processing temperature is about 270° C. As such, both during processing and use of the integrated circuit component at temperatures below a threshold temperature of, e.g., 270-350° C., the release layer 211 secures the dies 202 to the redistribution layer 212. At temperatures above a threshold of, e.g., 270-350° C., the release layer 211 releases the dies 202 from the redistribution layer 212. The threshold temperature for releasing the release layer 211 is below a threshold temperature at which the dies 202 will be damaged, allowing the dies 200 to withstand the temperature at which the release layer 211 releases the dies 202.
In the illustrative embodiment, the conductive pads 206 of the release layer 211 are high-temperature solder, such as a tin-gold solder. The tin-gold solder may be 20% tin and 80% gold by weight. More generally, the tin-gold solder may be, e.g., 15-40% tin and 60-85% gold by weight, depending on the particular properties that are desired. The tin-gold solder may have a melting point of, e.g., 278° C. to 350° C. In the illustrative embodiment, the tin-gold solder may have a melting point of about 290° C. More generally, the conductive pads 206 of the release layer 211 may be made of any suitable material that is conductive, has a melting point (or otherwise stops adhering to the dies 202 and/or the redistribution layer 212) at a temperature between about 250° C. to 400° C.
In the illustrative embodiment, the dielectric layer 210 of the release layer 211 is a high-melting point polymer, such as polytetrafluoroethylene (PTFE), cyclobutanes, high density polyimide, etc. The dielectric layer 210 may include any suitable combination of elements, such as carbon and fluorine, carbon and nitrogen, carbon and hydrogen, carbon, oxygen, and nitrogen, and/or any suitable combination of those. The dielectric layer 210 may have a melting point (or otherwise stops adhering to the dies 202 and/or the redistribution layer 212) at a temperature between about 250° C. to 400° C. For example, in one embodiment, the dielectric layer 210 may be PTFE with a melting point of about 327° C.
Referring now to
The method 300 begins in block 302, in which one or more dies 202 are placed on a carrier 502, as shown in
A seed layer 704, such as a copper seed layer 704, is then deposited on the dies 202, as shown in
In block 310, a high-melting-point solder is deposited to form the conductive pads 206, as shown in
In block 316, a high-melting-point dielectric, such as PTFE, is deposited to form the dielectric layer 210 of the release layer 211, as shown in
Referring now to
In block 322, the backside redistribution layer 218 is deposited, as shown in
In block 328, the die assembly package 102 is tested. For example, the integrated circuit component 100 with the substrate 104 may be placed in a test stand to check for, e.g., correct operation of the various interconnects. In block 330, if the die assembly package is not faulty, the method 300 proceeds to block 332, in which further operations with the die assembly package can proceed, such as using the integrated circuit component 100, integrating the integrated circuit component 100 into another component, packaging the integrated circuit component 100 for sale, etc.
If the die assembly package 102 is faulty, the method 300 proceeds to block 334, in which the dies 202 are removed from the die assembly package 102, as shown in
In block 336, the dies 202 are prepared for repackaging, such as being polished to remove any residue from the release layer 211. The method 300 then loops back to block 306 in
Although the method 300 describes fully forming the integrated circuit component 100 before testing for faults, it should be appreciated that testing may be performed at any suitable time, such as after patterning the redistribution layer 212 and before forming the bridge layer 214.
In some embodiments, rather than a relatively thick dielectric layer 210 between the dies 202 and the redistribution layer 212 as shown in
The integrated circuit device 1900 may include one or more device layers 1904 disposed on the die substrate 1902. The device layer 1904 may include features of one or more transistors 1940 (e.g., metal oxide semiconductor field-effect transistors (MOSFETs)) formed on the die substrate 1902. The transistors 1940 may include, for example, one or more source and/or drain (S/D) regions 1920, a gate 1922 to control current flow between the S/D regions 1920, and one or more S/D contacts 1924 to route electrical signals to/from the S/D regions 1920. The transistors 1940 may include additional features not depicted for the sake of clarity, such as device isolation regions, gate contacts, and the like. The transistors 1940 are not limited to the type and configuration depicted in
Returning to
The high-k dielectric material may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that may be used in the gate dielectric include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, an annealing process may be carried out on the gate dielectric to improve its quality when a high-k material is used.
The gate electrode may be formed on the gate dielectric and may include at least one p-type work function metal or n-type work function metal, depending on whether the transistor 1940 is to be a p-type metal oxide semiconductor (PMOS) or an n-type metal oxide semiconductor (NMOS) transistor. In some implementations, the gate electrode may consist of a stack of two or more metal layers, where one or more metal layers are work function metal layers and at least one metal layer is a fill metal layer. Further metal layers may be included for other purposes, such as a barrier layer.
For a PMOS transistor, metals that may be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, conductive metal oxides (e.g., ruthenium oxide), and any of the metals discussed below with reference to an NMOS transistor (e.g., for work function tuning). For an NMOS transistor, metals that may be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide), and any of the metals discussed above with reference to a PMOS transistor (e.g., for work function tuning).
In some embodiments, when viewed as a cross-section of the transistor 1940 along the source-channel-drain direction, the gate electrode may consist of a U-shaped structure that includes a bottom portion substantially parallel to the surface of the die substrate 1902 and two sidewall portions that are substantially perpendicular to the top surface of the die substrate 1902. In other embodiments, at least one of the metal layers that form the gate electrode may simply be a planar layer that is substantially parallel to the top surface of the die substrate 1902 and does not include sidewall portions substantially perpendicular to the top surface of the die substrate 1902. In other embodiments, the gate electrode may consist of a combination of U-shaped structures and planar, non-U-shaped structures. For example, the gate electrode may consist of one or more U-shaped metal layers formed atop one or more planar, non-U-shaped layers.
In some embodiments, a pair of sidewall spacers may be formed on opposing sides of the gate stack to bracket the gate stack. The sidewall spacers may be formed from materials such as silicon nitride, silicon oxide, silicon carbide, silicon nitride doped with carbon, and silicon oxynitride. Processes for forming sidewall spacers are well known in the art and generally include deposition and etching process steps. In some embodiments, a plurality of spacer pairs may be used; for instance, two pairs, three pairs, or four pairs of sidewall spacers may be formed on opposing sides of the gate stack.
The S/D regions 1920 may be formed within the die substrate 1902 adjacent to the gate 1922 of individual transistors 1940. The S/D regions 1920 may be formed using an implantation/diffusion process or an etching/deposition process, for example. In the former process, dopants such as boron, aluminum, antimony, phosphorous, or arsenic may be ion-implanted into the die substrate 1902 to form the S/D regions 1920. An annealing process that activates the dopants and causes them to diffuse farther into the die substrate 1902 may follow the ion-implantation process. In the latter process, the die substrate 1902 may first be etched to form recesses at the locations of the S/D regions 1920. An epitaxial deposition process may then be carried out to fill the recesses with material that is used to fabricate the S/D regions 1920. In some implementations, the S/D regions 1920 may be fabricated using a silicon alloy such as silicon germanium or silicon carbide. In some embodiments, the epitaxially deposited silicon alloy may be doped in situ with dopants such as boron, arsenic, or phosphorous. In some embodiments, the S/D regions 1920 may be formed using one or more alternate semiconductor materials such as germanium or a group III-V material or alloy. In further embodiments, one or more layers of metal and/or metal alloys may be used to form the S/D regions 1920.
Electrical signals, such as power and/or input/output (I/O) signals, may be routed to and/or from the devices (e.g., transistors 1940) of the device layer 1904 through one or more interconnect layers disposed on the device layer 1904 (illustrated in
The interconnect structures 1928 may be arranged within the interconnect layers 1906-1910 to route electrical signals according to a wide variety of designs; in particular, the arrangement is not limited to the particular configuration of interconnect structures 1928 depicted in
In some embodiments, the interconnect structures 1928 may include lines 1928a and/or vias 1928b filled with an electrically conductive material such as a metal. The lines 1928a may be arranged to route electrical signals in a direction of a plane that is substantially parallel with a surface of the die substrate 1902 upon which the device layer 1904 is formed. For example, the lines 1928a may route electrical signals in a direction in and out of the page and/or in a direction across the page. The vias 1928b may be arranged to route electrical signals in a direction of a plane that is substantially perpendicular to the surface of the die substrate 1902 upon which the device layer 1904 is formed. In some embodiments, the vias 1928b may electrically couple lines 1928a of different interconnect layers 1906-1910 together.
The interconnect layers 1906-1910 may include a dielectric material 1926 disposed between the interconnect structures 1928, as shown in
A first interconnect layer 1906 (referred to as Metal 1 or “M1”) may be formed directly on the device layer 1904. In some embodiments, the first interconnect layer 1906 may include lines 1928a and/or vias 1928b, as shown. The lines 1928a of the first interconnect layer 1906 may be coupled with contacts (e.g., the S/D contacts 1924) of the device layer 1904. The vias 1928b of the first interconnect layer 1906 may be coupled with the lines 1928a of a second interconnect layer 1908.
The second interconnect layer 1908 (referred to as Metal 2 or “M2”) may be formed directly on the first interconnect layer 1906. In some embodiments, the second interconnect layer 1908 may include via 1928b to couple the lines 1928 of the second interconnect layer 1908 with the lines 1928a of a third interconnect layer 1910. Although the lines 1928a and the vias 1928b are structurally delineated with a line within individual interconnect layers for the sake of clarity, the lines 1928a and the vias 1928b may be structurally and/or materially contiguous (e.g., simultaneously filled during a dual-damascene process) in some embodiments.
The third interconnect layer 1910 (referred to as Metal 3 or “M3”) (and additional interconnect layers, as desired) may be formed in succession on the second interconnect layer 1908 according to similar techniques and configurations described in connection with the second interconnect layer 1908 or the first interconnect layer 1906. In some embodiments, the interconnect layers that are “higher up” in the metallization stack 1919 in the integrated circuit device 1900 (i.e., farther away from the device layer 1904) may be thicker that the interconnect layers that are lower in the metallization stack 1919, with lines 1928a and vias 1928b in the higher interconnect layers being thicker than those in the lower interconnect layers.
The integrated circuit device 1900 may include a solder resist material 1934 (e.g., polyimide or similar material) and one or more conductive contacts 1936 formed on the interconnect layers 1906-1910. In
In some embodiments in which the integrated circuit device 1900 is a double-sided die, the integrated circuit device 1900 may include another metallization stack (not shown) on the opposite side of the device layer(s) 1904. This metallization stack may include multiple interconnect layers as discussed above with reference to the interconnect layers 1906-1910, to provide conductive pathways (e.g., including conductive lines and vias) between the device layer(s) 1904 and additional conductive contacts (not shown) on the opposite side of the integrated circuit device 1900 from the conductive contacts 1936. These additional conductive contacts may serve as the conductive contacts 204 or 208, as appropriate.
In other embodiments in which the integrated circuit device 1900 is a double-sided die, the integrated circuit device 1900 may include one or more through silicon vias (TSVs) through the die substrate 1902; these TSVs may make contact with the device layer(s) 1904, and may provide conductive pathways between the device layer(s) 1904 and additional conductive contacts (not shown) on the opposite side of the integrated circuit device 1900 from the conductive contacts 1936. These additional conductive contacts may serve as the conductive contacts 204 or 208, as appropriate. In some embodiments, TSVs extending through the substrate can be used for routing power and ground signals from conductive contacts on the opposite side of the integrated circuit device 1900 from the conductive contacts 1936 to the transistors 1940 and any other components integrated into the die 1900, and the metallization stack 1919 can be used to route I/O signals from the conductive contacts 1936 to transistors 1940 and any other components integrated into the die 1900.
Multiple integrated circuit devices 1900 may be stacked with one or more TSVs in the individual stacked devices providing connection between one of the devices to any of the other devices in the stack. For example, one or more high-bandwidth memory (HBM) integrated circuit dies can be stacked on top of a base integrated circuit die and TSVs in the HBM dies can provide connection between the individual HBM and the base integrated circuit die. Conductive contacts can provide additional connections between adjacent integrated circuit dies in the stack. In some embodiments, the conductive contacts can be fine-pitch solder bumps (microbumps).
In some embodiments, the circuit board 2102 may be a printed circuit board (PCB) including multiple metal (or interconnect) layers separated from one another by layers of dielectric material and interconnected by electrically conductive vias. The individual metal layers comprise conductive traces. Any one or more of the metal layers may be formed in a desired circuit pattern to route electrical signals (optionally in conjunction with other metal layers) between the components coupled to the circuit board 2102. In other embodiments, the circuit board 2102 may be a non-PCB substrate. In some embodiments the circuit board 2102 may be, for example, the circuit board 104. The integrated circuit device assembly 2100 illustrated in
The package-on-interposer structure 2136 may include an integrated circuit component 2120 coupled to an interposer 2104 by coupling components 2118. The coupling components 2118 may take any suitable form for the application, such as the forms discussed above with reference to the coupling components 2116. Although a single integrated circuit component 2120 is shown in
The integrated circuit component 2120 may be a packaged or unpacked integrated circuit product that includes one or more integrated circuit dies (e.g., the die 1802 of
In embodiments where the integrated circuit component 2120 comprises multiple integrated circuit dies, they dies can be of the same type (a homogeneous multi-die integrated circuit component) or of two or more different types (a heterogeneous multi-die integrated circuit component). A multi-die integrated circuit component can be referred to as a multi-chip package (MCP) or multi-chip module (MCM).
In addition to comprising one or more processor units, the integrated circuit component 2120 can comprise additional components, such as embedded DRAM, stacked high bandwidth memory (HBM), shared cache memories, input/output (I/O) controllers, or memory controllers. Any of these additional components can be located on the same integrated circuit die as a processor unit, or on one or more integrated circuit dies separate from the integrated circuit dies comprising the processor units. These separate integrated circuit dies can be referred to as “chiplets”. In embodiments where an integrated circuit component comprises multiple integrated circuit dies, interconnections between dies can be provided by the package substrate, one or more silicon interposers, one or more silicon bridges embedded in the package substrate (such as Intel® embedded multi-die interconnect bridges (EMIBs)), or combinations thereof.
Generally, the interposer 2104 may spread connections to a wider pitch or reroute a connection to a different connection. For example, the interposer 2104 may couple the integrated circuit component 2120 to a set of ball grid array (BGA) conductive contacts of the coupling components 2116 for coupling to the circuit board 2102. In the embodiment illustrated in
In some embodiments, the interposer 2104 may be formed as a PCB, including multiple metal layers separated from one another by layers of dielectric material and interconnected by electrically conductive vias. In some embodiments, the interposer 2104 may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, an epoxy resin with inorganic fillers, a ceramic material, or a polymer material such as polyimide. In some embodiments, the interposer 2104 may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group III-V and group IV materials. The interposer 2104 may include metal interconnects 2108 and vias 2110, including but not limited to through hole vias 2110-1 (that extend from a first face 2150 of the interposer 2104 to a second face 2154 of the interposer 2104), blind vias 2110-2 (that extend from the first or second faces 2150 or 2154 of the interposer 2104 to an internal metal layer), and buried vias 2110-3 (that connect internal metal layers).
In some embodiments, the interposer 2104 can comprise a silicon interposer. Through silicon vias (TSV) extending through the silicon interposer can connect connections on a first face of a silicon interposer to an opposing second face of the silicon interposer. In some embodiments, an interposer 2104 comprising a silicon interposer can further comprise one or more routing layers to route connections on a first face of the interposer 2104 to an opposing second face of the interposer 2104.
The interposer 2104 may further include embedded devices 2114, including both passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices such as radio frequency devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices may also be formed on the interposer 2104. The package-on-interposer structure 2136 may take the form of any of the package-on-interposer structures known in the art.
The integrated circuit device assembly 2100 may include an integrated circuit component 2124 coupled to the first face 2140 of the circuit board 2102 by coupling components 2122. The coupling components 2122 may take the form of any of the embodiments discussed above with reference to the coupling components 2116, and the integrated circuit component 2124 may take the form of any of the embodiments discussed above with reference to the integrated circuit component 2120.
The integrated circuit device assembly 2100 illustrated in
Additionally, in various embodiments, the electrical device 2200 may not include one or more of the components illustrated in
The electrical device 2200 may include one or more processor units 2202 (e.g., one or more processor units). As used herein, the terms “processor unit”, “processing unit” or “processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory. The processor unit 2202 may include one or more digital signal processors (DSPs), application-specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), general-purpose GPUs (GPGPUs), accelerated processing units (APUs), field-programmable gate arrays (FPGAs), neural network processing units (NPUs), data processor units (DPUs), accelerators (e.g., graphics accelerator, compression accelerator, artificial intelligence accelerator), controller cryptoprocessors (specialized processors that execute cryptographic algorithms within hardware), server processors, controllers, or any other suitable type of processor units. As such, the processor unit can be referred to as an XPU (or xPU).
The electrical device 2200 may include a memory 2204, which may itself include one or more memory devices such as volatile memory (e.g., dynamic random access memory (DRAM), static random-access memory (SRAM)), non-volatile memory (e.g., read-only memory (ROM), flash memory, chalcogenide-based phase-change non-voltage memories), solid state memory, and/or a hard drive. In some embodiments, the memory 2204 may include memory that is located on the same integrated circuit die as the processor unit 2202. This memory may be used as cache memory (e.g., Level 1 (L1), Level 2 (L2), Level 3 (L3), Level 4 (L4), Last Level Cache (LLC)) and may include embedded dynamic random access memory (eDRAM) or spin transfer torque magnetic random access memory (STT-MRAM).
In some embodiments, the electrical device 2200 can comprise one or more processor units 2202 that are heterogeneous or asymmetric to another processor unit 2202 in the electrical device 2200. There can be a variety of differences between the processing units 2202 in a system in terms of a spectrum of metrics of merit including architectural, microarchitectural, thermal, power consumption characteristics, and the like. These differences can effectively manifest themselves as asymmetry and heterogeneity among the processor units 2202 in the electrical device 2200.
In some embodiments, the electrical device 2200 may include a communication component 2212 (e.g., one or more communication components). For example, the communication component 2212 can manage wireless communications for the transfer of data to and from the electrical device 2200. The term “wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a nonsolid medium. The term “wireless” does not imply that the associated devices do not contain any wires, although in some embodiments they might not.
The communication component 2212 may implement any of a number of wireless standards or protocols, including but not limited to Institute for Electrical and Electronic Engineers (IEEE) standards including Wi-Fi (IEEE 802.11 family), IEEE 802.16 standards (e.g., IEEE 802.16-2005 Amendment), Long-Term Evolution (LTE) project along with any amendments, updates, and/or revisions (e.g., advanced LTE project, ultra mobile broadband (UMB) project (also referred to as “3GPP2”), etc.). IEEE 802.16 compatible Broadband Wireless Access (BWA) networks are generally referred to as WiMAX networks, an acronym that stands for Worldwide Interoperability for Microwave Access, which is a certification mark for products that pass conformity and interoperability tests for the IEEE 802.16 standards. The communication component 2212 may operate in accordance with a Global System for Mobile Communication (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network. The communication component 2212 may operate in accordance with Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication component 2212 may operate in accordance with Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution-Data Optimized (EV-DO), and derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The communication component 2212 may operate in accordance with other wireless protocols in other embodiments. The electrical device 2200 may include an antenna 2222 to facilitate wireless communications and/or to receive other wireless communications (such as AM or FM radio transmissions).
In some embodiments, the communication component 2212 may manage wired communications, such as electrical, optical, or any other suitable communication protocols (e.g., IEEE 802.3 Ethernet standards). As noted above, the communication component 2212 may include multiple communication components. For instance, a first communication component 2212 may be dedicated to shorter-range wireless communications such as Wi-Fi or Bluetooth, and a second communication component 2212 may be dedicated to longer-range wireless communications such as global positioning system (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others. In some embodiments, a first communication component 2212 may be dedicated to wireless communications, and a second communication component 2212 may be dedicated to wired communications.
The electrical device 2200 may include battery/power circuitry 2214. The battery/power circuitry 2214 may include one or more energy storage devices (e.g., batteries or capacitors) and/or circuitry for coupling components of the electrical device 2200 to an energy source separate from the electrical device 2200 (e.g., AC line power).
The electrical device 2200 may include a display device 2206 (or corresponding interface circuitry, as discussed above). The display device 2206 may include one or more embedded or wired or wirelessly connected external visual indicators, such as a heads-up display, a computer monitor, a projector, a touchscreen display, a liquid crystal display (LCD), a light-emitting diode display, or a flat panel display.
The electrical device 2200 may include an audio output device 2208 (or corresponding interface circuitry, as discussed above). The audio output device 2208 may include any embedded or wired or wirelessly connected external device that generates an audible indicator, such speakers, headsets, or earbuds.
The electrical device 2200 may include an audio input device 2224 (or corresponding interface circuitry, as discussed above). The audio input device 2224 may include any embedded or wired or wirelessly connected device that generates a signal representative of a sound, such as microphones, microphone arrays, or digital instruments (e.g., instruments having a musical instrument digital interface (MIDI) output). The electrical device 2200 may include a Global Navigation Satellite System (GNSS) device 2218 (or corresponding interface circuitry, as discussed above), such as a Global Positioning System (GPS) device. The GNSS device 2218 may be in communication with a satellite-based system and may determine a geolocation of the electrical device 2200 based on information received from one or more GNSS satellites, as known in the art.
The electrical device 2200 may include an other output device 2210 (or corresponding interface circuitry, as discussed above). Examples of the other output device 2210 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device.
The electrical device 2200 may include an other input device 2220 (or corresponding interface circuitry, as discussed above). Examples of the other input device 2220 may include an accelerometer, a gyroscope, a compass, an image capture device (e.g., monoscopic or stereoscopic camera), a trackball, a trackpad, a touchpad, a keyboard, a cursor control device such as a mouse, a stylus, a touchscreen, proximity sensor, microphone, a bar code reader, a Quick Response (QR) code reader, electrocardiogram (ECG) sensor, PPG (photoplethysmogram) sensor, galvanic skin response sensor, any other sensor, or a radio frequency identification (RFID) reader.
The electrical device 2200 may have any desired form factor, such as a hand-held or mobile electrical device (e.g., a cell phone, a smart phone, a mobile internet device, a music player, a tablet computer, a laptop computer, a 2-in-1 convertible computer, a portable all-in-one computer, a netbook computer, an ultrabook computer, a personal digital assistant (PDA), an ultra mobile personal computer, a portable gaming console, etc.), a desktop electrical device, a server, a rack-level computing solution (e.g., blade, tray or sled computing systems), a workstation or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a stationary gaming console, smart television, a vehicle control unit, a digital camera, a digital video recorder, a wearable electrical device or an embedded computing system (e.g., computing systems that are part of a vehicle, smart home appliance, consumer electronics product or equipment, manufacturing equipment). In some embodiments, the electrical device 2200 may be any other electronic device that processes data. In some embodiments, the electrical device 2200 may comprise multiple discrete physical components. Given the range of devices that the electrical device 2200 can be manifested as in various embodiments, in some embodiments, the electrical device 2200 can be referred to as a computing device or a computing system.
Illustrative examples of the technologies disclosed herein are provided below. An embodiment of the technologies may include any one or more, and any combination of, the examples described below.
Example 1 includes an integrated circuit component comprising one or more dies comprising a plurality of contact pads; a redistribution layer comprising a plurality of contact pads; and a release layer comprising a plurality of conductive pads, wherein individual conductive pads of the plurality of conductive pads connect one of the plurality of contact pads of the one or more dies to one of the plurality of contact pads of the redistribution layer; and a dielectric layer, wherein, below a first threshold temperature, the release layer secures the one or more dies to the redistribution layer, wherein the first threshold temperature is at least 280° C., wherein, above a second threshold temperature, the release layer is to release the one or more dies from the redistribution layer, wherein the one or more dies are able to withstand a temperature at the second threshold temperature.
Example 2 includes the subject matter of Example 1, and wherein the plurality of conductive pads of the release layer comprise gold and tin.
Example 3 includes the subject matter of any of Examples 1 and 2, and wherein the plurality of conductive pads of the release layer comprise at least 75% gold by weight and at least 15% tin by weight.
Example 4 includes the subject matter of any of Examples 1-3, and wherein the plurality of conductive pads of the release layer comprises a solder with a melting point between 290° C. and 350° C.
Example 5 includes the subject matter of any of Examples 1-4, and wherein the dielectric layer of the release layer comprises a polymer.
Example 6 includes the subject matter of any of Examples 1-5, and wherein the dielectric layer of the release layer has a melting point between 290° C. and 350° C.
Example 7 includes the subject matter of any of Examples 1-6, and wherein the dielectric layer of the release layer comprises polytetrafluoroethylene (PTFE).
Example 8 includes the subject matter of any of Examples 1-7, and wherein the dielectric layer of the release layer comprises one or more cyclobutanes.
Example 9 includes the subject matter of any of Examples 1-8, and wherein the dielectric layer of the release layer comprises polyimide.
Example 10 includes the subject matter of any of Examples 1-9, and wherein individual contact pads of the plurality of contact pads of the redistribution layer comprise a first side and a second side opposite the first side, wherein, for individual contact pads of the plurality of contact pads of the redistribution layer, the first side is adjacent a conductive pad of the plurality of conductive pads, wherein, for individual contact pads of the plurality of contact pads of the redistribution layer, the second side is at least partially covered by the dielectric layer.
Example 11 includes the subject matter of any of Examples 1-10, and wherein the dielectric layer has a thickness less than 5 micrometers.
Example 12 includes the subject matter of any of Examples 1-11, and further including a bridge die coupled to the redistribution layer; a backside redistribution layer coupled to the bridge die; and one or more solder balls coupled to the backside redistribution layer.
Example 13 includes the subject matter of any of Examples 1-12, and wherein the redistribution layer is a backside redistribution layer, further comprising one or more solder balls coupled to the backside redistribution layer.
Example 14 includes an integrated circuit component comprising one or more dies; a redistribution layer; and a release layer means comprising means for electrically connecting the one or more dies to the redistribution layer; and means for electrically isolating at least part of the one or more dies from at least part of the redistribution layer, wherein, below a first threshold temperature, the release layer means secures the one or more dies to the redistribution layer, wherein the first threshold temperature is at least 280° C., wherein, above a second threshold temperature, the release layer means is to release the one or more dies from the redistribution layer, wherein the one or more dies are able to withstand a temperature at the second threshold temperature.
Example 15 includes the subject matter of Example 14, and wherein the means for electrically connecting the one or more dies to the redistribution layer comprise gold and tin.
Example 16 includes the subject matter of any of Examples 14 and 15, and wherein the means for electrically connecting the one or more dies to the redistribution layer comprise at least 75% gold by weight and at least 15% tin by weight.
Example 17 includes the subject matter of any of Examples 14-16, and wherein the means for electrically connecting the one or more dies to the redistribution layer comprises a solder with a melting point between 290° C. and 350° C.
Example 18 includes the subject matter of any of Examples 14-17, and wherein the means for electrically isolating at least part of the one or more dies from at least part of the redistribution layer comprises a polymer.
Example 19 includes the subject matter of any of Examples 14-18, and wherein the means for electrically isolating at least part of the one or more dies from at least part of the redistribution layer has a melting point between 290° C. and 350° C.
Example 20 includes the subject matter of any of Examples 14-19, and wherein the means for electrically isolating at least part of the one or more dies from at least part of the redistribution layer comprises polytetrafluoroethylene (PTFE).
Example 21 includes the subject matter of any of Examples 14-20, and wherein means for electrically isolating at least part of the one or more dies from at least part of the redistribution layer comprises one or more cyclobutanes.
Example 22 includes the subject matter of any of Examples 14-21, and wherein the means for electrically isolating at least part of the one or more dies from at least part of the redistribution layer comprises polyimide.
Example 23 includes the subject matter of any of Examples 14-22, and wherein the means for electrically connecting the one or more dies to the redistribution layer comprises a plurality of conductive pads, wherein the redistribution layer comprises a plurality of contact pads, wherein the plurality of contact pads of the redistribution layer comprise a first side and a second side opposite the first side, wherein, for individual contact pads of the plurality of contact pads of the redistribution layer, the first side is adjacent a conductive pad of the plurality of conductive pads, wherein, for individual contact pads of the plurality of contact pads of the redistribution layer, the second side is at least partially covered by the means for electrically isolating at least part of the one or more dies from at least part of the redistribution layer.
Example 24 includes the subject matter of any of Examples 14-23, and wherein the means for electrically isolating at least part of the one or more dies from at least part of the redistribution layer has a thickness less than 5 micrometers.
Example 25 includes the subject matter of any of Examples 14-24, and further including a bridge die coupled to the redistribution layer; a backside redistribution layer coupled to the bridge die; and one or more solder balls coupled to the backside redistribution layer.
Example 26 includes the subject matter of any of Examples 14-25, and wherein the redistribution layer is a backside redistribution layer, further comprising one or more solder balls coupled to the backside redistribution layer.
Example 27 includes a method comprising forming a release layer on one or more dies; forming a redistribution layer on the release layer; determining that the redistribution layer is faulty; in response to a determination that the redistribution layer is faulty, heating up the release layer above a threshold temperature; and removing the one or more dies from the redistribution layer while the release layer is above the threshold temperature.
Example 28 includes the subject matter of Example 27, and further including forming a second release layer on one or more dies after removing the one or more dies from the redistribution layer; forming a second redistribution layer on the second release layer; and determining that the second redistribution layer is not faulty.
Example 29 includes the subject matter of any of Examples 27 and 28, and wherein forming the redistribution layer on the release layer comprises heating up the one or more dies and the release layer to a temperature of over 260° C.
Example 30 includes the subject matter of any of Examples 27-29, and wherein forming the release layer comprises forming a seed layer of copper on the one or more dies; depositing a lamination layer on the seed layer; patterning the lamination layer to form a plurality of holes in the lamination layer; depositing a plurality of conductive pads in the plurality of holes, wherein the plurality of conductive pads have a melting point of at least 280° C.; and depositing a plurality of copper pads on the plurality of conductive pads.
Example 31 includes the subject matter of any of Examples 27-30, and further including depositing a dielectric layer on the one or more dies; and thinning the dielectric layer to expose the plurality of copper pads.
Example 32 includes the subject matter of any of Examples 27-31, and further including depositing a dielectric layer on the one or more dies and the plurality of copper pads, wherein the dielectric layer has a thickness less than five micrometers; and laser drilling or dry etching the dielectric layer to expose the plurality of copper pads.
Example 33 includes the subject matter of any of Examples 27-32, and wherein plurality of conductive pads of the release layer comprise gold and tin.
Example 34 includes the subject matter of any of Examples 27-33, and wherein the plurality of conductive pads of the release layer comprise at least 75% gold by weight and at least 15% tin by weight.
Example 35 includes the subject matter of any of Examples 27-34, and wherein plurality of conductive pads of the release layer comprises a solder with a melting point between 290° C. and 350° C.
Example 36 includes the subject matter of any of Examples 27-35, and wherein a dielectric layer of the release layer comprises a polymer.
Example 37 includes the subject matter of any of Examples 27-36, and wherein a dielectric layer of the release layer has a melting point between 290° C. and 350° C.
Example 38 includes the subject matter of any of Examples 27-37, and wherein a dielectric layer of the release layer comprises polytetrafluoroethylene (PTFE).
Example 39 includes the subject matter of any of Examples 27-38, and wherein a dielectric layer of the release layer comprises one or more cyclobutanes.
Example 40 includes the subject matter of any of Examples 27-39, and wherein a dielectric layer of the release layer comprises polyimide.
Example 41 includes the subject matter of any of Examples 27-40, and wherein a plurality of contact pads of the redistribution layer comprise a first side and a second side opposite the first side, wherein, for individual contact pads of the plurality of contact pads of the redistribution layer, the first side is adjacent a conductive pad of a plurality of conductive pads of the release layer, wherein, for individual contact pads of the plurality of contact pads of the redistribution layer, the second side is at least partially covered by a dielectric layer of the release layer.
Example 42 includes the subject matter of any of Examples 27-41, and wherein the dielectric layer has a thickness less than 5 micrometers.
Example 43 includes the subject matter of any of Examples 27-42, and further including a bridge die coupled to the redistribution layer; a backside redistribution layer coupled to the bridge die; and one or more solder balls coupled to the backside redistribution layer.
Example 44 includes the subject matter of any of Examples 27-43, and wherein the redistribution layer is a backside redistribution layer, wherein one or more solder balls are coupled to the backside redistribution layer.
