Patent Application
20220375939
Embedded memory is important to the performance of modern system-on-a-chip (SoC) technology. Low power and high density embedded memory is used in many different computer products and further improvements are always desirable.
Embodiments will be readily understood by the following detailed description in conjunction with the accompanying drawings. To facilitate this description, like reference numerals designate like structural elements. Embodiments are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings.
Overview
The systems, methods and devices of this disclosure each have several innovative aspects, no single one of which is solely responsible for all of the desirable attributes disclosed herein. Details of one or more implementations of the subject matter described in this specification are set forth in the description below and the accompanying drawings.
For purposes of illustrating IC devices and assemblies with TFT memory and glass support at the back as described herein, it might be useful to first understand phenomena that may come into play in certain IC arrangements. The following foundational information may be viewed as a basis from which the present disclosure may be properly explained. Such information is offered for purposes of explanation only and, accordingly, should not be construed in any way to limit the broad scope of the present disclosure and its potential applications.
Some memory devices may be considered “standalone” devices in that they are included in a chip that does not also include compute logic (where, as used herein, the term “compute logic devices” or simply “compute logic” or “logic devices,” refers to devices, e.g., transistors, for performing computing/processing operations). Other memory devices may be included in a chip along with compute logic and may be referred to as “embedded” memory devices. Using embedded memory to support compute logic may improve performance by bringing the memory and the compute logic closer together and eliminating interfaces that increase latency. Various embodiments of the present disclosure relate to embedded memory arrays, as well as corresponding methods and devices.
Some embodiments of the present disclosure may refer to dynamic random-access memory (DRAM) and in particular, embedded DRAM (eDRAM), because this type of memory has been introduced in the past to address the limitation in density and standby power of some other types of memory devices. However, embodiments of the present disclosure may be equally applicable to memory cells implemented other technologies. Thus, in general, memory cells described herein may be implemented as eDRAM cells, spin-transfer torque random-access memory (STTRAM) cells, resistive random-access memory (RRAM) cells, or any other nonvolatile memory cells.
A memory cell, e.g., an eDRAM cell, may include a capacitor for storing a bit value, or a memory state (e.g., logical “1” or “0”) of the cell, and an access transistor controlling access to the cell (e.g., access to write information to the cell or access to read information from the cell). Such a memory cell may be referred to as a “1T-1C memory cell,” highlighting the fact that it uses one transistor (i.e., “1T” in the term “1T-1C memory cell”) and one capacitor (i.e., “1C” in the term “1T-1C memory cell”). The capacitor of a 1T-1C memory cell may be coupled to one source/drain (S/D) region/terminal of the access transistor (e.g., to the source region of the access transistor), while the other S/D region of the access transistor may be coupled to a bitline (BL), and a gate terminal of the transistor may be coupled to a word-line (WL). Since such a memory cell can be fabricated with as little as a single access transistor, it can provide higher density and lower standby power versus some other types of memory in the same process technology, e.g., static random-access memory (SRAM).
Various memory cells have, conventionally, been implemented with access transistors being front end of line (FEOL), logic-process based, transistors implemented in an upper-most layer of a semiconductor substrate (i.e., frontend transistors). Inventors of the present disclosure realized that using conventional FEOL transistors as access transistors of memory cells (e.g., as access transistors of 1T-1C memory cells) creates several challenges.
One challenge relates to the leakage of an access transistor, i.e., current flowing between the source and the drain of a transistor when the transistor is in an “off” state. Since reducing leakage of logic transistors in the scaled technology is difficult, implementing 1T-1C memory in advanced technology nodes (e.g., 10 nanometer (nm), 7 nm, 5 nm, and beyond) can be challenging. In particular, given a certain access transistor leakage, capacitance of the capacitor of a 1T-1C memory cell should be large enough so that sufficient charge can be stored on the capacitor to meet the corresponding refresh times. However, continuous desire to decrease size of electronic components dictates that the macro area of memory arrays continues to decrease, placing limitations on how large the top area (i.e., the footprint) of a given capacitor is allowed to be, which means that capacitors need to be taller in order to have both sufficiently small footprint area and sufficiently large capacitance. As the capacitor dimensions continue to scale, this in turn creates a challenge for etching the openings for forming the capacitors as tall capacitors with small footprint areas require higher aspect ratio openings, something which is not easy to achieve.
Another challenge associated with the use of logic transistors in 1T-1C memory cells relates to the location of the capacitors such memory cells. Namely, it may be desirable to provide capacitors in metal layers close to their corresponding access transistors. Since logic transistors are implemented as FEOL transistors provided directly on the semiconductor substrate, the corresponding capacitors of 1T-1C memory cells then have to be embedded in lower metal layers in order to be close enough to the logic access transistors. As the pitches of lower metal layers aggressively scale in advanced technology nodes, embedding the capacitors in the lower metal layers poses significant challenges to the scaling of 1T-1C based memory.
Yet another challenge resides in that, given a usable surface area of a substrate, there are only so many FEOL transistors that can be formed in that area, placing a significant limitation on the density of memory cells of a memory array.
Embodiments of the present disclosure may improve on at least some of the challenges and issues described above. In contrast to the conventional memory approaches with FEOL transistors as described above, various embodiments of the present disclosure provide memory cells, arrays, and associated methods and devices, which use TFTs as access transistors of at least some of the memory cells. A TFT is a special kind of a FET made by depositing a thin film of an active semiconductor material, as well as a dielectric layer and metallic contacts, over a supporting layer that may be a non-conducting layer. At least a portion of the active semiconductor material forms a channel of the TFT. This is different from conventional, non-TFT, frontend transistors where the active semiconductor channel material is typically a part of a semiconductor substrate, e.g., a part of a silicon wafer. Using TFTs as access transistors of memory cells provides several advantages and enables unique architectures that were not possible with conventional, frontend transistors.
One advantage is that a TFT may have substantially lower leakage than a frontend transistor, allowing to relax the demands on the large capacitance placed on a capacitor of a 1T-1C memory cell. In other words, using a lower leakage TFT in a 1T-1C memory cell allows the memory cell to use a capacitor with lower capacitance and smaller aspect ratio while still meeting the same data retention requirements of other approaches, alleviating the scaling challenges of capacitors.
In addition, access TFTs may be moved to the back end of line (BEOL) layers (also referred to as “backend”) of an advanced complementary metal-oxide-semiconductor (CMOS) process, which means that their corresponding capacitors can be implemented in the upper metal layers with correspondingly thicker interlayer dielectric (ILD) and larger metal pitch to achieve higher capacitance. This eases the integration challenge introduced by embedding the capacitors. Furthermore, when at least some access transistors are implemented in the backend layers as TFTs, at least portions of different memory cells may be provided in different layers above a substrate, thus enabling a stacked architecture of memory arrays. In this context, the term “above” refers to being further away from the substrate or the FEOL of an IC assembly or device (e.g., the IC assembly 100 shown in
Memory cells/arrays implemented using TFTs are referred to, in general, as “TFT memory.” Embodiments of the present disclosure set forth two designs in which TFTs may be used to implement backend TFT memory: nanoribbon-based TFT memory and TFT memory using transistors with back-side contacts. However, other types of TFT memory are also within the scope of the present disclosure. Besides recognizing that TFT memory has advantages over conventional frontend transistor memory, embodiments of the present disclosure are further based on recognition that TFT memory may be further improved by reducing various parasitic effects. In particular, embodiments of the present disclosure are based on recognition that using a glass support structure at the back side of an IC structure with TFT memory in the backend may advantageously reduce parasitic effects of FEOL devices (e.g., frontend transistors) in the IC structure, e.g., compared to using a silicon-based (Si) support structure at the back. As used herein, the term “glass support structure” refers to any non-semiconductor support structure that has a dielectric constant lower than that of Si, e.g., lower than about 11. In some embodiments, such a glass support structure may include any type of glass materials, since glass has dielectric constants in a range between about 5 and 10.5. However, in some embodiments, what is described herein as a glass support structure may include materials other than glass, e.g., mica, as long as those materials have sufficiently low dielectric constants. Arranging a support structure with a dielectric constant lower than that of Si at the back of an IC structure may advantageously decrease various parasitic effects associated with the FEOL/frontend devices of the IC structure, since such parasitic effects are typically proportional to the dielectric constant of the surrounding medium.
In the following, some descriptions may refer to a particular S/D region or contact being either a source region/contact or a drain region/contact. However, unless specified otherwise, which region/contact of a transistor is considered to be a source region/contact and which region/contact is considered to be a drain region/contact is not important because, as is common in the field of FETs, designations of source and drain are often interchangeable. Therefore, descriptions of some illustrative embodiments of the source and drain regions/contacts provided herein are applicable to embodiments where the designation of source and drain regions/contacts may be reversed.
While some descriptions provided herein may refer to transistors being top-gated transistors, embodiments of the present disclosure are not limited to only this design and include transistors of various other architectures, or a mixture of different architectures. For example, in various embodiments, various TFTs described herein may include bottom-gated transistors, top-gated transistors, FinFETs, nanowire transistors, planar transistors, etc., all of which being within the scope of the present disclosure. Furthermore, although descriptions of the present disclosure may refer to logic devices or memory cells provided in a given layer, each layer of the IC devices described herein may also include other types of devices besides logic or memory devices described herein. For example, any of the memory layers described herein may also include logic circuits, and vice versa.
Furthermore, in the following detailed description, various aspects of the illustrative implementations will be described using terms commonly employed by those skilled in the art to convey the substance of their work to others skilled in the art.
For example, a term “interconnect” may be used to describe any element formed of an electrically conductive material for providing electrical connectivity to one or more components associated with an IC or/and between various such components. In general, the “interconnect” may refer to both conductive lines/wires (also sometimes referred to as “lines” or “metal lines” or “trenches”) and conductive vias (also sometimes referred to as “vias” or “metal vias”). In general, a term “conductive line” may be used to describe an electrically conductive element isolated by a dielectric material typically comprising an interlayer low-k dielectric that is provided within the plane of an IC chip. Such conductive lines are typically arranged in several levels, or several layers, of metallization stacks. On the other hand, the term “conductive via” may be used to describe an electrically conductive element that interconnects two or more conductive lines of different levels of a metallization stack. To that end, a via may be provided substantially perpendicularly to the plane of an IC chip or a support structure over which an IC structure is provided and may interconnect two conductive lines in adjacent levels or two conductive lines in not adjacent levels. A term “metallization stack” may be used to refer to a stack of one or more interconnects for providing connectivity to different circuit components of an IC chip.
In another example, the terms “package” and “IC package” are synonymous, as are the terms “die” and “IC die,” the term “insulating” means “electrically insulating,” the term “conducting” means “electrically conducting,” unless otherwise specified. Although certain elements may be referred to in the singular herein, such elements may include multiple sub-elements. For example, “an electrically conductive material” may include one or more electrically conductive materials. If used, the terms “oxide,” “carbide,” “nitride,” etc. refer to compounds containing, respectively, oxygen, carbon, nitrogen, etc., the term “high-k dielectric” refers to a material having a higher dielectric constant than silicon oxide, while the term “low-k dielectric” refers to a material having a lower dielectric constant than silicon oxide. Furthermore, the term “connected” may be used to describe a direct electrical or magnetic connection between the things that are connected, without any intermediary devices, while the term “coupled” may be used to describe either a direct electrical or magnetic connection between the things that are connected, or an indirect connection through one or more passive or active intermediary devices. The term “circuit” may be used to describe one or more passive and/or active components that are arranged to cooperate with one another to provide a desired function. The terms “substantially,” “close,” “approximately,” “near,” and “about,” generally refer to being within +/−20% of a target value based on the context of a particular value as described herein or as known in the art. Similarly, terms indicating orientation of various elements, e.g., “coplanar,” “perpendicular,” “orthogonal,” “parallel,” or any other angle between the elements, generally refer to being within +/−5-20% of a target value based on the context of a particular value as described herein or as known in the art.
For the purposes of the present disclosure, the phrase “A and/or B” means (A), (B), or (A and B). For the purposes of the present disclosure, the phrase “A, B, and/or C” means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C). The term “between,” when used with reference to measurement ranges, is inclusive of the ends of the measurement ranges. As used herein, the notation “A/B/C” means (A), (B), and/or (C).
The description may use the phrases “in an embodiment” or “in embodiments,” which may each refer to one or more of the same or different embodiments. Furthermore, the terms “comprising,” “including,” “having,” and the like, as used with respect to embodiments of the present disclosure, are synonymous. The disclosure may use perspective-based descriptions such as “above,” “below,” “top,” “bottom,” and “side”; such descriptions are used to facilitate the discussion and are not intended to restrict the application of disclosed embodiments. The accompanying drawings are not necessarily drawn to scale. Unless otherwise specified, the use of the ordinal adjectives “first,” “second,” and “third,” etc., to describe a common object, merely indicate that different instances of like objects are being referred to and are not intended to imply that the objects so described must be in a given sequence, either temporally, spatially, in ranking or in any other manner.
In the following detailed description, reference is made to the accompanying drawings that form a part hereof, and in which is shown, by way of illustration, embodiments that may be practiced. It is to be understood that other embodiments may be utilized, and structural or logical changes may be made without departing from the scope of the present disclosure. Therefore, the following detailed description is not to be taken in a limiting sense. For convenience, if a collection of drawings designated with different letters are present, e.g.,
In the drawings, some schematic illustrations of example structures of various devices and assemblies described herein may be shown with precise right angles and straight lines, but it is to be understood that such schematic illustrations may not reflect real-life process limitations which may cause the features to not look so “ideal” when any of the structures described herein are examined using e.g., scanning electron microscopy (SEM) images or transmission electron microscope (TEM) images. In such images of real structures, possible processing defects could also be visible, e.g., not-perfectly straight edges of materials, tapered vias or other openings, inadvertent rounding of corners or variations in thicknesses of different material layers, occasional screw, edge, or combination dislocations within the crystalline region, and/or occasional dislocation defects of single atoms or clusters of atoms. There may be other defects not listed here but that are common within the field of device fabrication.
Various devices and assemblies illustrated in the present drawings do not represent an exhaustive set of IC devices with TFT memory and glass support at the back as described herein, but merely provide examples of such devices. In particular, the number and positions of various elements shown in the present drawings is purely illustrative and, in various other embodiments, other numbers of these elements, provided in other locations relative to one another may be used in accordance with the general architecture considerations described herein. Further, the present drawings are intended to show relative arrangements of the elements therein, and the devices and assemblies of these figures may include other elements that are not specifically illustrated (e.g., various interfacial layers). Similarly, although particular arrangements of materials are discussed with reference to the present drawings, intermediate materials may be included in the IC devices and assemblies of these figures. Still further, although some elements of the various cross-sectional views are illustrated in the present drawings as being planar rectangles or formed of rectangular solids, this is simply for ease of illustration, and embodiments of these assemblies may be curved, rounded, or otherwise irregularly shaped as dictated by, and sometimes inevitable due to, the manufacturing processes used to fabricate semiconductor device assemblies. Inspection of layout and mask data and reverse engineering of parts of a device to reconstruct the circuit using e.g., optical microscopy, TEM, or SEM, and/or inspection of a cross-section of a device to detect the shape and the location of various device elements described herein using, e.g., Physical Failure Analysis (PFA) would allow determination of presence of the IC devices with TFT memory and glass support at the back as described herein.
Various operations may be described as multiple discrete actions or operations in turn in a manner that is most helpful in understanding the claimed subject matter. However, the order of description should not be construed as to imply that these operations are necessarily order dependent. In particular, these operations may not be performed in the order of presentation. Operations described may be performed in a different order from the described embodiment. Various additional operations may be performed, and/or described operations may be omitted in additional embodiments.
Various IC assemblies with TFT memory and glass support at the back as described herein may be implemented in, or associated with, one or more components associated with an IC or/and may be implemented between various such components. In various embodiments, components associated with an IC include, for example, transistors, diodes, power sources, resistors, capacitors, inductors, sensors, transceivers, receivers, antennas, etc. Components associated with an IC may include those that are mounted on IC or those connected to an IC. The IC may be either analog or digital and may be used in a number of applications, such as microprocessors, optoelectronics, logic blocks, audio amplifiers, etc., depending on the components associated with the IC. The IC may be employed as part of a chipset for executing one or more related functions in a computer.
Example IC Device with Glass Support at the Back
Implementations of the present disclosure may be formed or carried out on the glass support structure 110, which may be, e.g., a glass substrate, a glass die, a glass wafer or a glass chip. In some embodiments, the glass support structure 110 may include a glass material. Examples of glass materials include silicon oxide materials, possibly doped with elements and compounds such as boron, carbon, aluminum, hafnium oxide, e.g., in doping concentrations of between about 0.01% and 10%. In other embodiments, the glass support structure 110 may include other solid materials having a dielectric constant lower than that of Si, e.g., lower than about 10.5. In some embodiments, the glass support structure 110 may include mica. A thickness of the glass support structure 110 may be of any value for the glass support structure 110 to provide mechanical stability for the IC device 100 and, possibly, to support inclusion of various devices for further reducing the parasitic effects in the IC device. In some embodiments, the glass support structure 110 may have a thickness between about 0.2 micrometer (micron) and 1000 micron, e.g., between about 0.5 and 5 micron, or between about 1 and 3 micron. Although a few examples of materials from which the glass support structure 110 may be formed are described here, any material with sufficiently low dielectric constant that may serve as a foundation upon which a semiconductor device implementing any of the TFT memories as described herein may be provided falls within the spirit and scope of the present disclosure.
The first and second memory layers 130, 140 may, together, be seen as forming a TFT memory array 190. As such, the memory array 190 may include TFTs (e.g., access transistors of memory cells as described herein), capacitors, as well as wordlines (e.g., row selectors) and bitlines (e.g., column selectors), making up memory cells. In some embodiments, the memory array 190 may include only the first memory layer 130, but not the second memory layer 140. In other embodiments, the memory array 190 may include more than two memory layers stacked in different layers above one another. On the other hand, the FEOL layer 120 may be a compute logic layer in that it may include various logic layers, circuits, and devices (e.g., logic transistors) to drive and control a logic IC. For example, the logic devices of the compute logic layer 120 may form a memory peripheral circuit 180 to control (e.g., access (read/write), store, refresh) the memory cells of the memory array 190.
In some embodiments, the FEOL layer 120 may be provided in a FEOL and in one or more lowest BEOL layers (i.e., in one or more BEOL layers which are closest to the glass support structure 110), while the first memory layer 130 and the second memory layer 140 may be seen as provided in respective BEOL layers. Various BEOL layers may be (or may include) metal layers. Various metal layers of the BEOL may be used to interconnect the various inputs and outputs of the logic devices in the FEOL layer 120 and/or of the memory cells in the memory layers 130, 140. Generally speaking, each of the metal layers of the BEOL may include a via portion and a trench/interconnect portion. The trench portion of a metal layer is configured for transferring signals and power along electrically conductive (e.g., metal) lines (also sometimes referred to as “trenches”) extending in the x-y plane (e.g., in the x or y directions), while the via portion of a metal layer is configured for transferring signals and power through electrically conductive vias extending in the z-direction, e.g., to any of the adjacent metal layers above or below. Accordingly, vias connect metal structures (e.g., metal lines or vias) from one metal layer to metal structures of an adjacent metal layer. While referred to as “metal” layers, various layers of the BEOL may include only certain patterns of conductive metals, e.g., copper (Cu), aluminum (Al), tungsten (W), or cobalt (Co), or metal alloys, or more generally, patterns of an electrically conductive material, formed in an insulating medium such as an ILD. The insulating medium may include any suitable ILD materials such as silicon oxide, carbon-doped silicon oxide, silicon carbide, silicon nitride, aluminum oxide, and/or silicon oxynitride.
In other embodiments of the IC device 100, compute logic devices may be provided in a layer above the memory layers 130, 140, in between memory layers 130, 140, or combined with the memory layers 130, 140. Nanoribbon-based transistors with independent gate control as described herein may either be used as standalone transistors (e.g., the transistors of the FEOL 120) or included as a part of a memory cell (e.g., the access transistors of the memory cells of the memory layers 130, 140), and may be included in various regions/locations in the IC device 100.
The power and signal interconnect layer 150 may include one or more electrical interconnects configured to provide power and/or signals to/from various components of the IC device 100 (e.g., to the devices in the FEOL device layer 120 and/or to the memory cells in the TFT memory 190).
The illustration of
Example 1T-1C Memory Cell
As shown, the 1T-1C cell 200 may include an access transistor 210 and a capacitor 220. The access transistor 210 has a gate terminal, a source terminal, and a drain terminal, indicated in the example of
As shown in
Each of the BL 240, the WL 250, and the PL 260, as well as intermediate elements coupling these lines to various terminals described herein, may be formed of any suitable electrically conductive material, which may include an alloy or a stack of multiple electrically conductive materials. In some embodiments, such electrically conductive materials may include one or more metals or metal alloys, with metals such as ruthenium, palladium, platinum, cobalt, nickel, hafnium, zirconium, titanium, tantalum, and aluminum. In some embodiments, such electrically conductive materials may include one or more electrically conductive alloys oxides or carbides of one or more metals.
In some embodiments, the access transistor 210 may be a TFT. As described above, in some embodiments, the access transistor 210 may be a nanoribbon-based transistor (or, simply, a nanoribbon transistor, e.g., a nanowire transistor). Such embodiments are described in greater detail below with reference to
Example TFT Memory with Nanoribbon Transistors
As used herein, the term “nanoribbon” refers to an elongated semiconductor structure having a long axis parallel to a support structure (e.g., a substrate, a chip, or a wafer) over which a memory device is provided. In some settings, the term “nanoribbon” has been used to describe an elongated semiconductor structure that has a rectangular transverse cross-section (i.e., a cross-section in a plane perpendicular to the longitudinal axis of the structure), while the term “nanowire” has been used to describe a similar structure but with a circular transverse cross-section. In the present disclosure, the term “nanoribbon” is used to describe both such nanoribbons and such nanowires, as well as elongated semiconductor structures with a longitudinal axis parallel to the support structures and with having transverse cross-sections of any geometry (e.g., oval, or a polygon with rounded corners).
In a nanoribbon transistor, a gate stack that may include a stack of one or more gate electrode metals and, optionally, a stack of one or more gate dielectrics may be provided around a portion of an elongated semiconductor structure called “nanoribbon”, forming a gate on all sides of the nanoribbon. The portion of the nanoribbon around which the gate stack wraps around is referred to as a “channel” or a “channel portion.” A semiconductor material of which the channel portion of the nanoribbon is formed is commonly referred to as a “channel material.” A source region and a drain region are provided on the opposite ends of the nanoribbon, on either side of the gate stack, forming, respectively, a source and a drain of such a transistor. Wrap-around or all-around gate transistors, such as nanoribbon and nanowire transistors, may provide advantages compared to other transistors having a non-planar architecture, such as FinFETs.
The arrangement shown in
Turning to the details of
The nanoribbon 304 may take the form of a nanowire or nanoribbon, for example. Although the nanoribbon 304 illustrated in
In some embodiments, the channel material of the nanoribbon 304 may be composed of semiconductor material systems including, for example, N-type or P-type materials systems. In some embodiments, the channel material of the nanoribbon 304 may include a high mobility oxide semiconductor material, such as tin oxide, antimony oxide, indium oxide, indium tin oxide, titanium oxide, zinc oxide, indium zinc oxide, gallium oxide, titanium oxynitride, ruthenium oxide, or tungsten oxide. In some embodiments, the channel material of the nanoribbon 304 may include a combination of semiconductor materials. In some embodiments, the channel material of the nanoribbon 304 may include a monocrystalline semiconductor, such as silicon (Si) or germanium (Ge). In some embodiments, the channel material of the nanoribbon 304 may include a compound semiconductor with a first sub-lattice of at least one element from group III of the periodic table (e.g., Al, Ga, In), and a second sub-lattice of at least one element of group V of the periodic table (e.g., P, As, Sb).
For some example N-type transistor embodiments (i.e., for the embodiments where the transistor 310 is an N-type metal-oxide-semiconductor (NMOS)), the channel material of the nanoribbon 304 may advantageously include a III-V material having a high electron mobility, such as, but not limited to InGaAs, InP, InSb, and InAs. For some such embodiments, the channel material of the nanoribbon 304 may be a ternary III-V alloy, such as InGaAs, GaAsSb, InAsP, or InPSb. For some InxGa1-xAs fin embodiments, In content (x) may be between 0.6 and 0.9, and may advantageously be at least 0.7 (e.g., In0.7Ga0.3As). In some embodiments with highest mobility, the channel material of the nanoribbon 304 may be an intrinsic III-V material, i.e., a III-V semiconductor material not intentionally doped with any electrically active impurity. In alternate embodiments, a nominal impurity dopant level may be present within the channel material of the nanoribbon 304, for example to further fine-tune a threshold voltage Vt, or to provide HALO pocket implants, etc. Even for impurity-doped embodiments however, impurity dopant level within the channel material of the nanoribbon 304 may be relatively low, for example below 1015 dopant atoms per cubic centimeter (cm−3), and advantageously below 1013 cm−3.
For some example P-type transistor embodiments (i.e., for the embodiments where the transistor 310 is a P-type metal-oxide-semiconductor (PMOS)), the channel material of the nanoribbon 304 may advantageously be a group IV material having a high hole mobility, such as, but not limited to Ge or a Ge-rich SiGe alloy. For some example embodiments, the channel material of the nanoribbon 304 may have a Ge content between 0.6 and 0.9, and advantageously may be at least 0.7. In some embodiments with highest mobility, the channel material of the nanoribbon 304 may be intrinsic III-V (or IV for P-type devices) material and not intentionally doped with any electrically active impurity. In alternate embodiments, one or more a nominal impurity dopant level may be present within the channel material of the nanoribbon 304, for example to further set a threshold voltage (Vt), or to provide HALO pocket implants, etc. Even for impurity-doped embodiments however, impurity dopant level within the channel portion is relatively low, for example below 1015 cm−3, and advantageously below 1013 cm−3.
In some embodiments, the channel material of the nanoribbon 304 may be a thin-film material, such as a high mobility oxide semiconductor material, such as tin oxide, antimony oxide, indium oxide, indium tin oxide, titanium oxide, zinc oxide, indium zinc oxide, indium gallium zinc oxide (IGZO), gallium oxide, titanium oxynitride, ruthenium oxide, or tungsten oxide. In general, if the transistor formed in the nanoribbon is a TFT, the channel material of the nanoribbon 304 may include one or more of tin oxide, cobalt oxide, copper oxide, antimony oxide, ruthenium oxide, tungsten oxide, zinc oxide, gallium oxide, titanium oxide, indium oxide, titanium oxynitride, indium tin oxide, indium zinc oxide, nickel oxide, niobium oxide, copper peroxide, IGZO, indium telluride, molybdenite, molybdenum diselenide, tungsten diselenide, tungsten disulfide, N- or P-type amorphous or polycrystalline silicon, germanium, indium gallium arsenide, silicon germanium, gallium nitride, aluminum gallium nitride, indium phosphite, and black phosphorus, each of which may possibly be doped with one or more of gallium, indium, aluminum, fluorine, boron, phosphorus, arsenic, nitrogen, tantalum, tungsten, and magnesium, etc. In some embodiments, the channel material of the nanoribbon 304 may have a thickness between about 5 and 75 nanometers, including all values and ranges therein. In some embodiments, a thin-film channel material may be deposited at relatively low temperatures, which allows depositing the channel material within the thermal budgets imposed on back end fabrication to avoid damaging other components, e.g., front end components such as the logic devices.
A gate stack 306 including a gate electrode material 308 and, optionally, a gate dielectric material 312, may wrap entirely or almost entirely around a portion of the nanoribbon 304 as shown in
The gate electrode material 308 may include at least one P-type work function metal or N-type work function metal, depending on whether the access transistor 310 is a PMOS transistor or an NMOS transistor (P-type work function metal used as the gate electrode material 308 when the access transistor 310 is a PMOS transistor and N-type work function metal used as the gate electrode material 308 when the access transistor 310 is an NMOS transistor). For a PMOS transistor, metals that may be used for the gate electrode material 308 may include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides (e.g., ruthenium oxide). For an NMOS transistor, metals that may be used for the gate electrode material 308 include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide). In some embodiments, the gate electrode material 308 may include a stack of two or more metal layers, where one or more metal layers are work function metal layers and at least one metal layer is a fill metal layer. Further layers may be included next to the gate electrode material 308 for other purposes, such as to act as a diffusion barrier layer or/and an adhesion layer.
In some embodiments, the gate dielectric material 312 may include one or more high-k dielectrics including any of the materials discussed herein with reference to the insulator material that may surround portions of the memory cell 300. In some embodiments, an annealing process may be carried out on the gate dielectric material 312 during manufacture of the access transistor 310 to improve the quality of the gate dielectric material 312. The gate dielectric material 312 may have a thickness that may, in some embodiments, be between about 0.5 nanometers and 3 nanometers, including all values and ranges therein (e.g., between about 1 and 3 nanometers, or between about 1 and 2 nanometers). In some embodiments, the gate stack 306 may be surrounded by a gate spacer, not shown in
As further shown in
The S/D regions 314 of the transistor 310 may generally be formed using either an implantation/diffusion process or an etching/deposition process. In the former process, dopants such as boron, aluminum, antimony, phosphorous, or arsenic may be ion-implanted into the nanoribbon 304 to form the source and drain regions. An annealing process that activates the dopants and causes them to diffuse further into the nanoribbon 304 may follow the ion implantation process. In the latter process, portions of the nanoribbon 304 may first be etched to form recesses at the locations of the future S/D regions 314. An epitaxial deposition process may then be carried out to fill the recesses with material that is used to fabricate the S/D regions 314. In some implementations, the S/D regions 314 may be fabricated using a silicon alloy such as silicon germanium or silicon carbide. In some implementations the epitaxially deposited silicon alloy may be doped in situ with dopants such as boron, arsenic, or phosphorous. In further embodiments, the S/D regions 314 may be formed using one or more alternate semiconductor materials such as germanium or a group III-V material or alloy. And in further embodiments, one or more layers of metal and/or metal alloys may be used to form the S/D regions 314.
In some embodiments, the access transistor 310 may have a gate length (i.e., a distance between the first and second S/D regions 314), a dimension measured along the nanoribbon 304, between about 5 and 40 nanometers, including all values and ranges therein (e.g., between about 22 and 35 nanometers, or between about 20 and 30 nanometers). In some embodiments, an area of a transversal cross-section of the nanoribbon 304 may be between about 25 and 10000 square nanometers, including all values and ranges therein (e.g., between about 25 and 1000 square nanometers, or between about 25 and 500 nanometers).
Although not specifically shown in
In some embodiments, the capacitor dielectric 330 may include any of the insulator materials described herein, e.g., any of the high-k or low-k dielectric materials described herein. In some embodiments, the capacitor dielectric 330 may be replaced with, or complemented with a layer of a ferroelectric material (i.e., in some embodiments, a ferroelectric material may be provided between the two electrodes of the capacitor 320 or 220). Such a ferroelectric material may include one or more materials which exhibit sufficient ferroelectric behavior even at thin dimensions. Some examples of such materials known at the moment include hafnium zirconium oxide (HfZrO, also referred to as HZO), silicon-doped (Si-doped) hafnium oxide, germanium-doped (Ge-doped) hafnium oxide, aluminum-doped (Al-doped) hafnium oxide, and yttrium-doped (Y-doped) hafnium oxide. However, in other embodiments, any other materials which exhibit ferroelectric behavior at thin dimensions may be used to replace, or to complement, the capacitor dielectric 330 and are within the scope of the present disclosure. The ferroelectric material included in the capacitor 220/320 may have a thickness that may, in some embodiments, be between about 0.5 nanometers and 10 nanometers, including all values and ranges therein (e.g., between about 1 and 8 nanometers, or between about 0.5 and 5 nanometers). Although not specifically shown in
In other embodiments (not specifically shown in the figures), the capacitor 320 may be a three-dimensional capacitor having a shape other than a rectangular prism, e.g., a cylindrical capacitor. In various embodiments, the substantially cylindrical and rectangular prism shapes of the capacitor 320 may include further modifications, e.g., the rectangular prism may have rounded corners.
Below, an example arrangement in which a plurality of nanoribbon-based 1T-1C memory cells 200/300 may be arranged to form a memory array is described with reference to
The memory arrangement 480 is an example of the IC device 100, where, e.g., each of the nanoribbons 304 of the memory arrangement 480 may be considered to belong to a different one of the memory layers 130, 140, etc. The memory arrangement 480 illustrates an example where two 1T-1C memory cells as described herein (e.g., as described with reference to
As shown in
When the nanoribbons 304 extend in a direction substantially parallel to the glass support structure 110, the shared BLs, e.g., the BL 440, may then extend in a direction substantially perpendicular to the glass support structure 110. Gate contacts 452 may also extend in a direction substantially perpendicular to the glass support structure 110. In some embodiments, for a set of access transistors stacked above one another, the gate contacts 452 may be arranged in a staircase-like manner (e.g., as can be seen for the gate contacts 452-11, 452-21, 452-31, and 452-41, shown in
In some embodiments, each of the capacitors 420 may include a pair of capacitor electrodes 326, 328, separated by a capacitor dielectric 330, as described above, where one of the capacitor electrodes (e.g., the capacitor electrode 326) is coupled to the first S/D region of a corresponding access transistor of a given memory cell. As described above, the other one of the capacitor electrodes (e.g., the capacitor electrode 328) may be coupled to a PL, e.g., the PL 260 (although this is not specifically shown in
The memory arrangement 480 illustrates how nanoribbon-based memory, e.g., DRAM, may be created in a NAND-like fashion where access transistors of multiple memory cells can be created in parallel. The topology illustrated in
Example TFT Memory with Transistors with Back-Side Contacts
Conventional FEOL transistors have both source and drain contacts on one side of the transistor, usually on the side facing away from the substrate. In contrast to the approaches of building logic and memory devices with such conventional FEOL transistors, some embodiments of the present disclosure provide transistors having one S/D contact on one side and another S/D contact on the other side. One side of a transistor may be referred to as a “front side” while the other side may be referred to as a “back side,” where, in general, in the context of the present disclosure, a “side” of a transistor refers to a region or a layer either above or below a layer of the channel material of the transistor. Thus, transistors described herein may have one of the S/D contacts on the front side (such contacts referred to as “front-side contacts”) and the other one of their S/D contacts on the back side (such contacts referred to as “back-side contacts”). In further embodiments, both S/D contacts of at least some of the transistors used in IC assemblies described herein may be on the back side of the transistor. In the following, transistors having one front-side and one back-side S/D contacts, as well as transistors having two back-side S/D contacts, may be simply referred to as “transistors with back-side contacts.”
Turning to the details of
As further shown in
In stark contrast to conventional implementations where both S/D contacts are typically provided on a single side of a transistor, typically on the front side, e.g., where the gate stack 506 is provided, the two S/D contacts 516 of the transistor 510 are provided on different sides. Namely, as shown in
Although not specifically shown in
Example Fabrication Method
Implementing glass support in the back may be particularly advantageous for TFT memory arrays implemented in backend. IC devices with TFT memory and glass support at the back, as described herein, may be fabricated using any suitable techniques, e.g., subtractive, additive, damascene, dual damascene, etc. Some of such technique may include suitable deposition and patterning techniques. As used herein, “patterning” may refer to forming a pattern in one or more materials using any suitable techniques (e.g., applying a resist, patterning the resist using lithography, and then etching the one or more material using dry etching, wet etching, or any appropriate technique).
The semiconductor support structure 622 may be a semiconductor substrate composed of semiconductor material systems including, for example, N-type or P-type materials systems. In one implementation, the semiconductor support structure 622 may be a crystalline substrate formed using a bulk silicon or a silicon-on-insulator (SOI) substructure. In other implementations, the semiconductor support structure 622 may be formed using alternate materials, which may or may not be combined with silicon, that include, but are not limited to, germanium, silicon germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, aluminum gallium arsenide, aluminum arsenide, indium aluminum arsenide, aluminum indium antimonide, indium gallium arsenide, gallium nitride, indium gallium nitride, aluminum indium nitride or gallium antimonide, or other combinations of group III-V materials (i.e., materials from groups III and V of the periodic system of elements), group II-VI (i.e., materials from groups II and IV of the periodic system of elements), or group IV materials (i.e., materials from group IV of the periodic system of elements). In some embodiments, the semiconductor support structure 622 may be non-crystalline. In some embodiments, the semiconductor support structure 622 may be a printed circuit board (PCB) substrate. Although a few examples of materials from which the semiconductor support structure 622 may be formed are described here, any material that may serve as a foundation upon which IC devices with FEOL devices and TFT memory as described herein may be built falls within the spirit and scope of the present disclosure. In various embodiments, the channel material of the FEOL devices 624 of the FEOL layer 120 may include, or may be formed upon, any such substrate material of the semiconductor support structure 622. The FEOL devices 624 may include any FEOL transistors such as FinFETs, planar transistors, nanoribbon transistors, nanowire transistors, etc.
As shown in
The fabrication method may then proceed with flipping the IC device 600C upside down so that further fabrication processes may be performed on the back side. A result of this is shown with an IC device 600D of
In some embodiments, no deliberately added adhesive bonding material may be used, in which case the layer labeled “662” in
The fabrication method may then proceed with flipping the IC device 600G upside down so that further fabrication processes may be performed on the back side. A result of this is shown with an IC device 600H of
In some embodiments, the glass support structure 660/110 may further include various devices to help improve signal integrity (e.g., in terms of signal-to-noise ratio, peak current, voltage droop, ground bounce or variations, etc.) of the signals and power communicated/provided to/from/between the FEOL devices and/or the TFT memory. Some examples of such embodiments are shown in
In some embodiments, the devices 710 may be thin-film devices 710. In various embodiments, the thin-film devices 710 may be two-terminal devices such as thin-film resistors, thin-film capacitors, and thin-film inductors, configured to improve the signal quality and integrity within the IC device 700. As shown in
Example Electronic Devices
IC devices with TFT memory and glass support at the back as disclosed herein may be included in any suitable electronic device.
The package substrate 2252 may be formed of a dielectric material (e.g., a ceramic, a buildup film, an epoxy film having filler particles therein, etc.), and may have conductive pathways extending through the dielectric material between the face 2272 and the face 2274, or between different locations on the face 2272, and/or between different locations on the face 2274.
The package substrate 2252 may include conductive contacts 2263 that are coupled to conductive pathways 2262 through the package substrate 2252, allowing circuitry within the dies 2256 and/or the interposer 2257 to electrically couple to various ones of the conductive contacts 2264 (or to other devices included in the package substrate 2252, not shown).
The IC package 2200 may include an interposer 2257 coupled to the package substrate 2252 via conductive contacts 2261 of the interposer 2257, first-level interconnects 2265, and the conductive contacts 2263 of the package substrate 2252. The first-level interconnects 2265 illustrated in
The IC package 2200 may include one or more dies 2256 coupled to the interposer 2257 via conductive contacts 2254 of the dies 2256, first-level interconnects 2258, and conductive contacts 2260 of the interposer 2257. The conductive contacts 2260 may be coupled to conductive pathways (not shown) through the interposer 2257, allowing circuitry within the dies 2256 to electrically couple to various ones of the conductive contacts 2261 (or to other devices included in the interposer 2257, not shown). The first-level interconnects 2258 illustrated in
In some embodiments, an underfill material 2266 may be disposed between the package substrate 2252 and the interposer 2257 around the first-level interconnects 2265, and a mold compound 2268 may be disposed around the dies 2256 and the interposer 2257 and in contact with the package substrate 2252. In some embodiments, the underfill material 2266 may be the same as the mold compound 2268. Example materials that may be used for the underfill material 2266 and the mold compound 2268 are epoxy mold materials, as suitable. Second-level interconnects 2270 may be coupled to the conductive contacts 2264. The second-level interconnects 2270 illustrated in
The dies 2256 may take the form of any of the embodiments of the IC devices with TFT memory and glass support at the back discussed herein. In embodiments in which the IC package 2200 includes multiple dies 2256, the IC package 2200 may be referred to as a multi-chip package (MCP). The dies 2256 may include circuitry to perform any desired functionality. For example, one or more of the dies 2256 may be logic dies (e.g., silicon-based dies), and one or more of the dies 2256 may be memory dies (e.g., high bandwidth memory), including embedded logic and memory devices as described herein. In some embodiments, any of the dies 2256 may include one or more IC devices with TFT memory and glass support at the back, e.g., as discussed above; in some embodiments, at least some of the dies 2256 may not include any of the IC devices with TFT memory and glass support at the back.
The IC package 2200 illustrated in
In some embodiments, the circuit board 2302 may be a PCB including multiple metal layers separated from one another by layers of dielectric material and interconnected by electrically conductive vias. Any one or more of the metal layers may be formed in a desired circuit pattern to route electrical signals (optionally in conjunction with other metal layers) between the components coupled to the circuit board 2302. In other embodiments, the circuit board 2302 may be a non-PCB substrate.
The IC device assembly 2300 illustrated in
The package-on-interposer structure 2336 may include an IC package 2320 coupled to an interposer 2304 by coupling components 2318. The coupling components 2318 may take any suitable form for the application, such as the forms discussed above with reference to the coupling components 2316. The IC package 2320 include one or more IC devices with TFT memory and glass support at the back as described herein. Although a single IC package 2320 is shown in
The interposer 2304 may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide. In some implementations, the interposer 2304 may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group III-V and group IV materials. The interposer 2304 may include metal interconnects 2308 and vias 2310, including but not limited to through-silicon vias (TSVs) 2306. The interposer 2304 may further include embedded devices 2314, including both passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) protection devices, and memory devices. More complex devices such as radio frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices may also be formed on the interposer 2304. The package-on-interposer structure 2336 may take the form of any of the package-on-interposer structures known in the art.
The IC device assembly 2300 may include an IC package 2324 coupled to the first face 2340 of the circuit board 2302 by coupling components 2322. The coupling components 2322 may take the form of any of the embodiments discussed above with reference to the coupling components 2316, and the IC package 2324 may take the form of any of the embodiments discussed above with reference to the IC package 2320.
The IC device assembly 2300 illustrated in
A number of components are illustrated in
Additionally, in various embodiments, the computing device 2400 may not include one or more of the components illustrated in
The computing device 2400 may include a processing device 2402 (e.g., one or more processing devices). As used herein, the term “processing device” or “processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory. The processing device 2402 may include one or more digital signal processors (DSPs), application-specific ICs (ASICs), central processing units (CPUs), graphics processing units (GPUs), cryptoprocessors (specialized processors that execute cryptographic algorithms within hardware), server processors, or any other suitable processing devices. The computing device 2400 may include a memory 2404, which may itself include one or more memory devices such as volatile memory (e.g., DRAM), nonvolatile memory (e.g., read-only memory (ROM)), flash memory, solid state memory, and/or a hard drive. In some embodiments, the memory 2404 may include memory that shares a die with the processing device 2402. This memory may be used as cache memory and may include one or more IC devices with TFT memory and glass support at the back as described herein.
In some embodiments, the computing device 2400 may include a communication chip 2412 (e.g., one or more communication chips). For example, the communication chip 2412 may be configured for managing wireless communications for the transfer of data to and from the computing device 2400. The term “wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a nonsolid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not.
The communication chip 2412 may implement any of a number of wireless standards or protocols, including but not limited to Institute for Electrical and Electronic Engineers (IEEE) standards including Wi-Fi (IEEE 602.11 family), IEEE 602.16 standards (e.g., IEEE 602.16-2005 Amendment), Long-Term Evolution (LTE) project along with any amendments, updates, and/or revisions (e.g., advanced LTE project, ultramobile broadband (UMB) project (also referred to as “3GPP2”), etc.). IEEE 602.16 compatible Broadband Wireless Access (BWA) networks are generally referred to as WiMAX networks, an acronym that stands for Worldwide Interoperability for Microwave Access, which is a certification mark for products that pass conformity and interoperability tests for the IEEE 602.16 standards. The communication chip 2412 may operate in accordance with a Global System for Mobile Communication (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network. The communication chip 2412 may operate in accordance with Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication chip 2412 may operate in accordance with Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution-Data Optimized (EV-DO), and derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The communication chip 2412 may operate in accordance with other wireless protocols in other embodiments. The computing device 2400 may include an antenna 2422 to facilitate wireless communications and/or to receive other wireless communications (such as AM or FM radio transmissions).
In some embodiments, the communication chip 2412 may manage wired communications, such as electrical, optical, or any other suitable communication protocols (e.g., the Ethernet). As noted above, the communication chip 2412 may include multiple communication chips. For instance, a first communication chip 2412 may be dedicated to shorter-range wireless communications such as Wi-Fi or Bluetooth, and a second communication chip 2412 may be dedicated to longer-range wireless communications such as global positioning system (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others. In some embodiments, a first communication chip 2412 may be dedicated to wireless communications, and a second communication chip 2412 may be dedicated to wired communications.
The computing device 2400 may include battery/power circuitry 2414. The battery/power circuitry 2414 may include one or more energy storage devices (e.g., batteries or capacitors) and/or circuitry for coupling components of the computing device 2400 to an energy source separate from the computing device 2400 (e.g., AC line power).
The computing device 2400 may include a display device 2406 (or corresponding interface circuitry, as discussed above). The display device 2406 may include any visual indicators, such as a heads-up display, a computer monitor, a projector, a touchscreen display, a liquid crystal display (LCD), a light-emitting diode display, or a flat panel display, for example.
The computing device 2400 may include an audio output device 2408 (or corresponding interface circuitry, as discussed above). The audio output device 2408 may include any device that generates an audible indicator, such as speakers, headsets, or earbuds, for example.
The computing device 2400 may include an audio input device 2418 (or corresponding interface circuitry, as discussed above). The audio input device 2418 may include any device that generates a signal representative of a sound, such as microphones, microphone arrays, or digital instruments (e.g., instruments having a musical instrument digital interface (MIDI) output).
The computing device 2400 may include a GPS device 2416 (or corresponding interface circuitry, as discussed above). The GPS device 2416 may be in communication with a satellite-based system and may receive a location of the computing device 2400, as known in the art.
The computing device 2400 may include an other output device 2410 (or corresponding interface circuitry, as discussed above). Examples of the other output device 2410 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device.
The computing device 2400 may include an other input device 2420 (or corresponding interface circuitry, as discussed above). Examples of the other input device 2420 may include an accelerometer, a gyroscope, a compass, an image capture device, a keyboard, a cursor control device such as a mouse, a stylus, a touchpad, a bar code reader, a Quick Response (QR) code reader, any sensor, or a radio frequency identification (RFID) reader.
The computing device 2400 may have any desired form factor, such as a handheld or mobile computing device (e.g., a cell phone, a smart phone, a mobile internet device, a music player, a tablet computer, a laptop computer, a netbook computer, an ultrabook computer, a personal digital assistant (PDA), an ultramobile personal computer, etc.), a desktop computing device, a server or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a vehicle control unit, a digital camera, a digital video recorder, or a wearable computing device. In some embodiments, the computing device 2400 may be any other electronic device that processes data.
The following paragraphs provide various examples of the embodiments disclosed herein.
Example 1 provides an IC device that includes a support structure of a non-semiconductor material having a dielectric constant that is smaller than a dielectric constant of silicon (e.g., a glass wafer); a frontend layer, including a plurality of frontend devices; and a backend layer, including a memory array with memory cells including TFTs, one or more of the memory cells coupled to one or more of the plurality of frontend devices, where the frontend layer is between the support structure and the backend layer.
Example 2 provides the IC device according to example 1, where the support structure includes a two-terminal thin-film device coupled to two or more of interconnects of the frontend layer, interconnects of the backend layer, the plurality of frontend devices, the memory cells.
Example 3 provides the IC device according to example 2, where the thin-film device is a thin-film resistor.
Example 4 provides the IC device according to example 2, where the thin-film device is a thin-film capacitor.
Example 5 provides the IC device according to example 2, where the thin-film device is a thin-film inductor.
Example 6 provides the IC device according to any one of the preceding examples, further including a bonding interface between the frontend layer and the support structure.
Example 7 provides the IC device according to example 6, where the bonding interface includes an oxide.
Example 8 provides the IC device according to example 7, where the oxide includes one or more portions in contact with one or more portions of the support structure, and one or more portions in contact with one or more portions of the frontend layer.
Example 9 provides the IC device according to any one of the preceding examples, where the non-semiconductor material of the support structure includes glass.
Example 10 provides the IC device according to any one of the preceding examples, where the non-semiconductor material of the support structure includes mica.
Example 11 provides the IC device according to any one of the preceding examples, where the memory array includes a first nanoribbon of a first semiconductor material; a second nanoribbon of a second semiconductor material; a first source or drain (S/D) region and a second S/D region in each of the first nanoribbon and the second nanoribbon; a first gate stack at least partially surrounding a portion of the first nanoribbon between the first S/D region and the second S/D region in the first nanoribbon; a second gate stack, not electrically coupled to the first gate stack, at least partially surrounding a portion of the second nanoribbon between the first S/D region and the second S/D region in the second nanoribbon; and a bitline coupled to the first S/D region of the first nanoribbon and the first S/D region of the second nanoribbon.
Example 12 provides the IC device according to example 11, where at least a portion of the first nanoribbon is between the support structure and at least a portion of the second nanoribbon.
Example 13 provides the IC device according to example 12, where the memory array further includes a first gate contact electrically coupled to the first gate stack and a second gate contact electrically coupled to the second gate stack, and where the first gate contact is over a first region of the support structure and the second gate contact is over a second region of the support structure, the second region being different and non-overlapping with the first region.
Example 14 provides the IC device according to any one of examples 11-13, further including a first storage node coupled to the second S/D region of the first nanoribbon, and a second storage node coupled to the second S/D region of the second nanoribbon, where at least one of the first storage node and the second storage node includes a capacitor.
Example 15 provides the IC device according to any one of examples 11-14, where the first gate stack includes a gate electrode material and a ferroelectric material, and the ferroelectric material is between the gate electrode material and the first semiconductor material. In other embodiments, the second gate stack may be similar to the first gate stack and also include a ferroelectric material, which may be either the same or different material composition than the ferroelectric material of the first gate stack.
Example 16 provides the IC device according to any one of the preceding examples, where the TFTs are access transistors of the memory cells of the backend layer.
Example 17 provides the IC device according to any one of the preceding examples, where the support structure is replaced with a support structure of a material having a dielectric constant lower than 10, which may, but does not have to be, glass. For example, the material of the support structure may be mica.
Example 18 provides an IC package that includes an IC device according to any one of the preceding examples; and a further IC component, coupled to the IC device. For example, the IC device may include a frontend layer including a plurality of transistors that includes one or more of fin-based transistors, nanoribbon transistors, and nanowire transistors; a backend layer including a plurality of TFTs coupled to one or more of the plurality of transistors; and a support structure bonded to the front end layer, where the frontend layer is between the support structure and the backend layer, and where the support structure includes a non-semiconductor material having a dielectric constant that is smaller than a dielectric constant of silicon.
Example 19 provides the IC package according to example 18, where the further IC component includes one of a package substrate, an interposer, or a further IC die.
Example 20 provides the IC package according to examples 18 or 20, where the IC device includes, or is a part of, at least one of a memory device, a computing device, a wearable device, a handheld electronic device, and a wireless communications device.
Example 21 provides an electronic device that includes a carrier substrate; and one or more of the IC device according to any one of the preceding examples and the IC package according to any one of the preceding examples, coupled to the carrier substrate.
Example 22 provides the electronic device according to example 21, where the carrier substrate is a motherboard.
Example 23 provides the electronic device according to example 21, where the carrier substrate is a PCB.
Example 24 provides the electronic device according to any one of examples 21-23, where the electronic device is a wearable electronic device (e.g., a smart watch) or handheld electronic device (e.g., a mobile phone).
Example 25 provides the electronic device according to any one of examples 21-24, where the electronic device further includes one or more communication chips and an antenna.
Example 26 provides the electronic device according to any one of examples 21-25, where the electronic device is an RF transceiver.
Example 27 provides the electronic device according to any one of examples 21-25, where the electronic device is one of a switch, a power amplifier, a low-noise amplifier, a filter, a filter bank, a duplexer, an upconverter, or a downconverter of an RF communications device, e.g., of an RF transceiver.
Example 28 provides the electronic device according to any one of examples 21-25, where the electronic device is a computing device.
Example 29 provides the electronic device according to any one of examples 21-28, where the electronic device is included in a base station of a wireless communication system.
Example 30 provides the electronic device according to any one of examples 21-28, where the electronic device is included in a user equipment device (i.e., a mobile device) of a wireless communication system.
Example 31 provides a method of fabricating an IC device. The method includes providing a frontend layer over a semiconductor support structure, the frontend layer including a plurality of frontend devices; providing a backend layer over the frontend layer, the backend layer including a memory array with memory cells including TFTs, one or more of the memory cells coupled to one or more of the plurality of frontend devices; performing a back-side reveal by removing at least a portion of the semiconductor support structure to expose the frontend layer; and bonding a support structure of a non-semiconductor material having a dielectric constant that is smaller than a dielectric constant of silicon (e.g., a glass wafer) to the exposed frontend layer.
Example 32 provides the method according to example 31, where bonding the support structure of the non-semiconductor material to the exposed frontend layer includes providing one or more bonding materials on at least one of the exposed frontend layer and a face of the support structure of the non-semiconductor material to be bonded to the exposed frontend layer, and attaching the exposed frontend layer to the face of the support structure of the non-semiconductor material to be bonded to the exposed frontend layer.
Example 33 provides the method according to example 32, where the one or more bonding materials include an oxide.
Example 34 provides the method according to any one of examples 31-33, where removing the at least portions of the semiconductor support structure includes polishing or grinding away the semiconductor support structure until the frontend layer is exposed.
Example 35 provides the method according to any one of examples 31-34, where the non-semiconductor support structure includes glass.
Example 36 provides the method according to any one of examples 31-35, where the non-semiconductor support structure includes mica.
Example 37 provides the method according to any one of examples 31-36, further including processes for forming the IC device according to any one of the preceding examples (e.g., for forming the IC device according to any one of examples 1-17).
The above description of illustrated implementations of the disclosure, including what is described in the Abstract, is not intended to be exhaustive or to limit the disclosure to the precise forms disclosed. While specific implementations of, and examples for, the disclosure are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the disclosure, as those skilled in the relevant art will recognize. These modifications may be made to the disclosure in light of the above detailed description.
