Patent Application
20240250032
Semiconductor devices are used in a variety of electronic applications, such as, for example, personal computers, cell phones, digital cameras, and other electronic equipment. Semiconductor devices are typically fabricated by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers of material over a semiconductor substrate, and patterning the various material layers using lithography to form circuit components and elements thereon.
The semiconductor industry continues to improve the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continual reductions in minimum feature size, which allow more components to be integrated into a given area. However, as the minimum features sizes are reduced, additional problems arise that should be addressed.
Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures.
The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
According to various embodiment, nanostructure-FETs are formed with vertical nanostructures. The nanostructure-FETs include gate structures wrapped around the sidewalls of the vertical nanostructures. Contacts are formed to the gate structures such that the contacts are disposed between and shared by the gate structures of adjacent nanostructure-FETs. Multiple gate structures may thus be coupled together with a same gate contact instead of with higher-level interconnects. The density of the resulting integrated circuits may thus be improved.
The nanostructure-FETs each include a semiconductor nanostructure 66 (e.g., nanosheet, nanobar, or the like), with the semiconductor nanostructures 66 being semiconductor features that act as channel regions for the nanostructure-FETs. The semiconductor nanostructures 66 are vertical nanostructures that extend in a direction perpendicular to a major surface of a substrate (not separately illustrated). A gate structure 100 is wrapped around each of the sidewalls of a semiconductor nanostructure 66. The gate structures 100 each include a gate dielectric and a gate electrode (subsequently described). Source/drain regions 84 (including upper source/drain regions 84U and lower source/drain regions 84L) are disposed above and below the semiconductor nanostructures 66, respectively. Source/drain region(s) 84 may refer to a source or a drain, individually or collectively dependent upon the context. Each nanostructure-FET includes a semiconductor nanostructure 66, an upper source/drain region 84U, and a lower source/drain region 84L, with the semiconductor nanostructure 66 being disposed between the upper source/drain region 84U and the lower source/drain region 84L. Lightly doped source/drain (LDD) regions (subsequently described) may be formed between the source/drain regions 84 and the semiconductor nanostructures 66. Contacts (subsequently described) to the source/drain regions 84 and the gate structures 100 will be formed. The source/drain regions 84 and/or the gate structures 100 may be shared between various semiconductor nanostructures 66. For example, adjacent source/drain regions 84 and/or adjacent gate structures 100 may be electrically connected, such as through coupling multiple source/drain regions 84 with a same contact or coupling multiple gate structures 100 with a same contact.
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The substrate 50 has an n-type region 50N and a p-type region 50P. The n-type region 50N can be for forming n-type devices, such as NMOS transistors, e.g., n-type nanostructure-FETs, and the p-type region 50P can be for forming p-type devices, such as PMOS transistors, e.g., p-type nanostructure-FETs. The n-type region 50N may (or may not) be physically separated (not separately illustrated) from the p-type region 50P, and any number of device features (e.g., other active devices, doped regions, isolation structures, etc.) may be disposed between the n-type region 50N and the p-type region 50P. Although one n-type region 50N and one p-type region 50P are illustrated, any number of n-type regions 50N and p-type regions 50P may be provided.
A multi-layer stack 52 is formed over the substrate 50. The multi-layer stack 52 includes dummy layers 54 (including a lower dummy layer 54L and an upper dummy layer 54U) and a semiconductor layer 56. The semiconductor layer 56 is between the lower dummy layer 54L and the upper dummy layer 54U. The dummy layers 54 are formed of a first semiconductor material, and the semiconductor layer 56 is formed of a second semiconductor material. The semiconductor materials may each be selected from the candidate semiconductor materials of the substrate 50. Each of the layers of the multi-layer stack 52 may be grown by a process such as vapor phase epitaxy (VPE) or molecular beam epitaxy (MBE), deposited by a process such as chemical vapor deposition (CVD) or atomic layer deposition (ALD), or the like.
As subsequently described in greater detail, the dummy layers 54 will be removed and the semiconductor layer 56 will be patterned to form channel regions for the nanostructure-FETs. The dummy layers 54 will be removed in subsequent processing to expose the top surfaces and the bottom surfaces of the semiconductor layer 56. The first semiconductor material of the dummy layers 54 is a material that has a high etching selectivity to the semiconductor material of the semiconductor layer 56, such as silicon-germanium (e.g., SixGe1-x, where x can be in the range of 0 to 1). The second semiconductor material of the semiconductor layer 56 is a material suitable for both n-type and p-type devices, such as silicon.
A mask 58 is formed on the multi-layer stack 52. The mask 58 will be used as an etching mask during an etching processes for patterning trenches in the multi-layer stack 52 and the substrate 50. The mask 58 may include a hardmask. In some embodiments, the mask 58 is formed of a photoresist, such as a single layer photoresist, a bi-layer photoresist, a tri-layer photoresist, or the like. For example, the mask 58 may be a tri-layer photoresist including a bottom layer (e.g., a bottom anti-reflective coating (BARC) layer), a middle layer (e.g., a hardmask), and a top layer (e.g., a photoresist). The photoresist may be formed by spin coating, a deposition process such as CVD, combinations thereof, or the like, and can be patterned using any acceptable photolithography techniques to have a desired pattern of the trenches.
In some embodiments, the mask 58 is formed using one or more photolithography processes, including double-patterning or multi-patterning processes. Generally, double-patterning or multi-patterning processes combine photolithography and self-aligned processes, allowing patterns to be created that have, for example, pitches smaller than what is otherwise obtainable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers may then be used as the mask 58.
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Subsequently, fins 62 are formed in the substrate 50 and nanostructures 64, 66 (including lower dummy nanostructures 64L, upper dummy nanostructures 64U, and semiconductor nanostructures 66) are formed in the multi-layer stack 52. In some embodiments, the nanostructures 64, 66 and the fins 62 may be formed in the multi-layer stack 52 and the substrate 50, respectively, by etching trenches 68 in the multi-layer stack 52 and the substrate 50 using the combination of the first spacers 60 and the mask 58 as an etching mask. The etching may be any acceptable etch process, such as a reactive ion etch (RIE), neutral beam etch (NBE), the like, or a combination thereof. The etching may be anisotropic. Forming the nanostructures 64, 66 by etching the multi-layer stack 52 may define the lower dummy nanostructures 64L from the lower dummy layer 54L, the upper dummy nanostructures 64U from the upper dummy layer 54U, and the semiconductor nanostructures 66 from the semiconductor layer 56. Each semiconductor nanostructure 66 is between a lower dummy nanostructure 64L and an upper dummy nanostructure 64U. As subsequently described in greater detail, the upper dummy nanostructures 64U will be replaced with upper source/drain regions, and the lower dummy nanostructures 64L will be replaced with lower source/drain regions. The lower dummy nanostructures 64L and the upper dummy nanostructures 64U may further be collectively referred to as the dummy nanostructures 64.
In some embodiments, the nanostructures 64, 66 are vertical nanostructures such as nanobars, although other vertical channel structure shapes and configurations are possible, such as nanowires, multiple nanowires, multiple nanobars, or the like. A nanobar has a longitudinal axis and a latitudinal axis, which are perpendicular to each other. The longitudinal axis and the latitudinal axis of the nanostructures 64, 66 are perpendicular to a major surface of the substrate 50.
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As an example to form the gate spacers 72, the trenches 68 can be laterally expanded. Specifically, portions of the sidewalls of the dummy nanostructures 64 exposed by the trenches 68 may be recessed to form sidewall recesses. Although sidewalls of the dummy nanostructures 64 are illustrated as being concave, the sidewalls may be straight or convex. The sidewalls may be recessed by any acceptable etch process, such as one that is selective to the dummy nanostructures 64 (e.g., selectively etches the material of the dummy nanostructures 64 at a faster rate than the material of the semiconductor nanostructures 66). The etching may be isotropic. For example, when the dummy nanostructures 64 are formed of silicon-germanium and the semiconductor nanostructures 66 are formed of silicon, the etch process may be a wet etch using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), or the like. In another embodiment, the etch process may be a dry etch using a fluorine-based gas such as hydrogen fluoride (HF) gas. In some embodiments, the same etch process may be continually performed to both form the trenches 68 and recess the sidewalls of the dummy nanostructures 64. The gate spacers 72 can then be formed by conformally forming an insulating material in the sidewall recesses and the trenches 68, and subsequently etching the insulating material. The insulating material may be silicon nitride, silicon carbonitride, silicon oxycarbide, or silicon oxycarbonitride, although any suitable material, such as low-dielectric constant (low-k) materials having a k-value less than about 3.5, may be utilized. The insulating material may be formed by a deposition process, such as ALD, CVD, or the like. The etching of the insulating material may be anisotropic. For example, the etch process may be a dry etch such as a RIE, a NBE, or the like. The insulating material, when etched, has portions left in the sidewall recesses (thus forming the gate spacers 72).
Although outer sidewalls of gate spacers 72 are illustrated as being flush with sidewalls of the semiconductor nanostructures 66, the outer sidewalls of the gate spacers 72 may extend beyond or be recessed from sidewalls of the semiconductor nanostructures 66. Thus, the gate spacers 72 may partially fill, completely fill, or overfill the sidewall recesses. Moreover, although the sidewalls of the gate spacers 72 are illustrated as being straight, the sidewalls of the gate spacers 72 may be concave or convex.
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In some embodiments, the trimming process includes performing multiple oxidation and etch cycles. For example, during each oxidation cycle, portions of the semiconductor nanostructures 66 may be oxidized, and during each etch cycle, the oxidized portions of the semiconductor nanostructures 66 are removed. The oxidation and etch cycles are repeated until a desired amount of material has been trimmed from the semiconductor nanostructures 66. For example, the oxidation and etch cycles may be cyclically repeated a predetermined quantity of times. The oxidation may be accomplished by any acceptable oxidation process, such as a native oxidation process, a thermal oxidation process, a rapid thermal oxidation (RTO) process, a chemical oxidation process, an in-situ stream generation (ISSG) process, or the like. Other oxidation processes or a combination thereof may be performed. The etching may be accomplished by any acceptable etching process, such as a wet etch, a dry etch, or combinations thereof. For example, a chemical oxide removal with any acceptable etch process using, for example, dilute hydrofluoric (dHF) acid may be used.
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The insulation material 74 may be deposited over the first spacers 60 and the mask 58 such that excess insulation material 74 covers the first spacers 60 and the mask 58. A removal process is then applied to the insulation material 74 to remove excess insulation material 74 over the first spacers 60 and the mask 58. In some embodiments, a planarization process such as a chemical mechanical polish (CMP), an etch-back process, combinations thereof, or the like may be utilized. The planarization process exposes the first spacers 60 and the mask 58 such that top surfaces of the mask 58, the first spacers 60, and the insulation material 74 are substantially coplanar (within process variations) after the planarization process is complete.
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The upper source/drain regions 84U in the n-type region 50N may be formed by masking the p-type region 50P. Then, the upper source/drain regions 84U are epitaxially grown in the upper source/drain recesses 76 in the n-type region 50N. The upper source/drain regions 84U in the n-type region 50N may include any acceptable material appropriate for n-type nanostructure-FETs. For example, if the semiconductor nanostructures 66 are formed of silicon, the upper source/drain regions 84U may include materials exerting a tensile strain on the semiconductor nanostructures 66, such as silicon, carbon-doped silicon, phosphorous-doped silicon, silicon phosphide, or the like. The upper source/drain regions 84U in the n-type region 50N may be referred to as “n-type source/drain regions.” The upper source/drain regions 84U may have surfaces raised from respective upper surfaces of the semiconductor nanostructures 66 and may have facets.
The upper source/drain regions 84U in the p-type region 50P may be formed by masking the n-type region 50N. Then, the upper source/drain regions 84U are epitaxially grown in the upper source/drain recesses 76 in the p-type region 50P. The upper source/drain regions 84U in the p-type region 50P may include any acceptable material appropriate for p-type nanostructure-FETs. For example, if the semiconductor nanostructures 66 are formed of silicon, the upper source/drain regions 84U may comprise materials exerting a compressive strain on the semiconductor nanostructures 66, such as silicon-germanium, boron-doped silicon-germanium, germanium, germanium tin, or the like. The upper source/drain regions 84U in the p-type region 50P may be referred to as “p-type source/drain regions.” The upper source/drain regions 84U may also have surfaces raised from respective surfaces of the semiconductor nanostructures 66 and may have facets.
The upper source/drain regions 84U may be implanted with appropriate type (e.g., n-type or p-type) dopants to form source/drain regions, followed by an anneal. The n-type dopants may be phosphorus, arsenic, antimony, or the like. The p-type dopants may be boron, boron fluoride, indium, or the like. The source/drain regions may have a dopant concentration of between 1019 atoms/cm3 and 1021 atoms/cm3. In some embodiments, the upper source/drain regions 84U may be in situ doped during growth.
The upper source/drain regions 84U may comprise one or more semiconductor material layers. For example, the upper source/drain regions 84U may comprise a liner layer, a main layer, and a finishing layer (or more generally, a first semiconductor material layer, a second semiconductor material layer, and a third semiconductor material layer). Any number of semiconductor material layers may be used for the upper source/drain regions 84U. Each of the liner layer, the main layer, and the finishing layer may be formed of different semiconductor materials and may be doped to different dopant concentrations. In some embodiments, the liner layer may have a dopant concentration less than the main layer and greater than the finishing layer. In embodiments in which the upper source/drain regions 84U include three semiconductor material layers, the liner layers may be grown in the upper source/drain recesses 76, the main layers may be grown on the liner layers, and the finishing layers may be grown on the main layers.
Optionally, upper LDD regions 82U are formed in the upper source/drain recesses 76. The upper LDD regions 82U are formed on the semiconductor nanostructures 66 and the upper source/drain regions 84U are formed on the upper LDD regions 82U, such that the upper LDD regions 82U are between the upper source/drain regions 84U and the semiconductor nanostructures 66. The upper LDD regions 82U may be epitaxially grown in a similar manner to the upper source/drain regions 84U, e.g., using appropriate masking steps to form the upper LDD regions 82U in the p-type region 50P of acceptable material appropriate for p-type nanostructure-FETs (previously described) and to form the upper LDD regions 82U in the n-type region 50N of acceptable material appropriate for n-type nanostructure-FETs (previously described). The upper LDD regions 82U may be implanted with appropriate type (e.g., n-type or p-type) dopants to form LDD regions, followed by an anneal. The n-type and/or p-type dopants for LDD regions may be any of the previously described dopants. The LDD regions may have a dopant concentration in a range from 1015 atoms/cm3 to 1019 atoms/cm3. In some embodiments, the upper LDD regions 82U may be in situ doped during growth.
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As an example to form the source/drain masks 86, one or more dielectric material(s) may be conformally deposited in the upper source/drain recesses 76. The dielectric material(s) may also be deposited on the top surfaces of the insulation material 74 and the first spacers 60. Acceptable dielectric materials may include silicon nitride, silicon carbonitride, silicon oxynitride, silicon oxycarbonitride, or the like, which may be formed by a conformal deposition process such as chemical vapor deposition (CVD), atomic layer deposition (ALD), or the like. Other dielectric materials formed by any acceptable process may be used. A removal process is performed to remove the excess portions of the dielectric material(s), which excess portions are over the top surfaces of the insulation material 74 and the first spacers 60. In some embodiments, a planarization process such as a chemical mechanical polish (CMP), an etch-back process, combinations thereof, or the like is utilized. The dielectric material(s), after the removal process, have portions left in the upper source/drain recesses 76 (thus forming the source/drain masks 86). After the planarization process, the top surfaces of the source/drain masks 86, the insulation material 74, and the first spacers 60 are substantially coplanar (within process variations).
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A gate electrode layer 96 is formed on the gate dielectric layer 94. The gate electrode layer 96 may include one or more metal-containing material(s) such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, combinations thereof, multi-layers thereof, or the like. The formation methods of the gate electrode layer 96 may include physical vapor deposition (PVD), CVD, ALD, and the like. Although a single-layered gate electrode layer 96 is illustrated, the gate electrode layer 96 may include multiple layers, such as any number of work function tuning layers, any number of glue layers, and a fill layer.
The formation of the gate dielectric layers 94 in the n-type region 50N and the p-type region 50P may occur simultaneously such that the gate dielectric layers 94 in each region are formed from the same materials, and the formation of the gate electrode layers 96 may occur simultaneously such that the gate electrode layers 96 in each region are formed from the same materials. In some embodiments, the gate dielectric layers 94 in each region may be formed by distinct processes, such that the gate dielectric layers 94 may be different materials and/or have a different number of layers, and/or the gate electrode layers 96 in each region may be formed by distinct processes, such that the gate electrode layers 96 may be different materials and/or have a different number of layers. Various masking steps may be used to mask and expose appropriate regions when using distinct processes.
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In some embodiments, a contact etch stop layer (CESL) 112 is formed between the first ILD 114 and the gate dielectric layer 94 and the gate electrodes 104. The CESL 112 may be formed of a dielectric material having a high etching selectivity to the dielectric material of the first ILD 114, such as, silicon nitride, silicon oxide, silicon oxynitride, or the like, which may be formed by any suitable deposition process, such as CVD, ALD, or the like.
As subsequently described in greater detail, gate contacts will be formed through the first ILD 114 and the CESL 112, to the gate electrodes 104. The gate contacts are formed between adjacent gate electrodes 104 and adjacent semiconductor nanostructures 66, such that the gate contacts extend along the outer sidewalls of the gate electrodes 104. Multiple gate electrodes 104 may thus be coupled by a same gate contact, which may be advantageous when fabricating some types of circuits, such as
CMOS inverters. In some embodiments, a gate contact is disposed between (and coupled to) a gate electrode 104 in the p-type region 50P and a gate electrode 104 in the n-type region 50N. Optionally, gate contact masks are formed over the gate contacts.
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As an example to form the gate contacts 118, a liner (not separately illustrated), such as a diffusion barrier layer, an adhesion layer, or the like, and a conductive material may be formed in the contact openings 116. The liner may include titanium, titanium nitride, tantalum, tantalum nitride, or the like. The conductive material may be copper, a copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, or the like. A planarization process, such as a CMP, may be performed to remove excess material from the top surfaces of the first ILD 114. The remaining liner and conductive material form the gate contacts 118 in the contact openings 116. After the planarization process, top surfaces of the gate contacts 118 and the first ILD 114 are substantially coplanar (within process variations).
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Timed etching processes may be used to stop the etching of the gate contacts 118 after the gate contacts 118 have been recessed a desired distance. The top surfaces of the gate contacts 118 are disposed above the top surfaces of the gate electrodes 104 after the gate contacts 118 are recessed. In this embodiment, the gate dielectric layer 94 is not recessed, and as a result, the contact openings 116 expose the outer sidewalls of the gate dielectric layer 94 after the gate contacts 118 are recessed. In another embodiment (subsequently described for
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As an example to form the gate contact masks 120, one or more dielectric material(s) may be conformally deposited in the contact openings 116. The dielectric material(s) may also be deposited on the top surfaces of the first ILD 114. Acceptable dielectric materials may include silicon nitride, silicon carbonitride, silicon oxynitride, silicon oxycarbonitride, or the like, which may be formed by a conformal deposition process such as chemical vapor deposition (CVD), atomic layer deposition (ALD), or the like. Other dielectric materials formed by any acceptable process may be used. A removal process is performed to remove the excess portions of the dielectric material(s), which excess portions are over the top surfaces of the first ILD 114. In some embodiments, a planarization process such as a chemical mechanical polish (CMP), an etch-back process, combinations thereof, or the like is utilized. The dielectric material(s), after the removal process, have portions left in the contact openings 116 (thus forming the gate contact masks 120).
Additionally, a removal process is performed to form gate dielectrics 102 and to level the top surfaces of the gate contact masks 120 with the top surfaces of the first ILD 114, the gate dielectrics 102, the source/drain masks 86, and the first spacers 60. In some embodiments, a planarization process such as a chemical mechanical polish (CMP), an etch-back process, combinations thereof, or the like may be utilized. After the planarization process, the top surfaces of the gate contact masks 120, the first ILD 114, the gate dielectrics 102, the source/drain masks 86, and the first spacers 60 are substantially coplanar (within process variations). Accordingly, the top surfaces of the source/drain masks 86 (if present) are exposed through the first ILD 114. In some embodiments, the same removal process is used to form gate dielectrics 102 and to form the gate contact masks 120.
The gate contacts 118 are adjacent the resulting gate structures (including the gate dielectrics 102 and the gate electrodes 104). The gate electrodes 104 are disposed between the gate dielectrics 102 and portions of the gate contacts 118. Additionally, the gate dielectrics 102 are disposed between portions of the gate contacts 118 and the first spacers 60 and the gate spacers 72. As a result of forming the gate electrodes 104 with the previously-described etch-back process, the outer sidewalls of the gate electrodes 104 are aligned with the outer sidewalls of the gate dielectrics 102. The gate contacts 118 extend along and physically contact the outer sidewalls of the gate electrodes 104 and the outer sidewalls of the gate dielectrics 102. The gate contacts 118 also extend along the outer sidewalls of the gate spacers 72 and the outer sidewalls of the first spacers 60.
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Optionally, metal-semiconductor alloy regions 124 are formed on the upper source/drain regions 84U. The metal-semiconductor alloy regions 124 can be silicide regions formed of a metal silicide (e.g., titanium silicide, cobalt silicide, nickel silicide, etc.), germanide regions formed of a metal germanide (e.g. titanium germanide, cobalt germanide, nickel germanide, etc.), silicon-germanide regions formed of both a metal silicide and a metal germanide, or the like. The metal-semiconductor alloy regions 124 may be formed before the conductive pads 126, by depositing a metal in the upper source/drain recesses 76 and then performing a thermal annealing process. The metal can be any metal capable of reacting with the semiconductor materials (e.g., silicon, carbon-doped silicon, silicon-germanium, germanium, etc.) of the upper source/drain regions 84U to form a low-resistance metal-semiconductor alloy, such as nickel, cobalt, titanium, tantalum, platinum, tungsten, other noble metals, other refractory metals, rare earth metals, or their alloys. The metal may be formed by a deposition process such as ALD, CVD, PVD, or the like. After the thermal annealing process, a cleaning process, such as a wet clean, may be performed to remove any residual metal from the upper source/drain recesses 76, such as from surfaces of the metal-semiconductor alloy regions 124. The conductive pads 126 may be formed on the metal-semiconductor alloy regions 124.
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In some embodiments, an etch stop layer (ESL) 132 is formed between the second ILD 134 and the conductive pads 126, the gate contact masks 120, the first ILD 114, the gate dielectrics 102, and the first spacers 60. The ESL 132 may be formed of a dielectric material having a high etching selectivity to the dielectric material of the second ILD 134, such as silicon nitride, silicon oxide, silicon oxynitride, or the like, which may be formed by any suitable deposition process, such as CVD, ALD, or the like. In this embodiment, the ESL 132 contacts the top surfaces of the gate dielectrics 102.
Source/drain contacts 136 are formed through the second ILD 134 and the ESL 132, to the conductive pads 126. The source/drain contacts 136 may be physically and electrically coupled to the conductive pads 126. As an example to form the source/drain contacts 136, openings for the source/drain contacts 136 are formed through the second ILD 134 and the ESL 132. The openings may be formed using any acceptable photolithography and etching techniques. A liner (not separately illustrated), such as a diffusion barrier layer, an adhesion layer, or the like, and a conductive material are formed in the openings. The liner may include titanium, titanium nitride, tantalum, tantalum nitride, or the like. The conductive material may be copper, a copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, or the like. A planarization process, such as a CMP, may be performed to remove excess material from the top surface of the second ILD 134. The remaining liner and conductive material form the source/drain contacts 136 in the openings.
Optionally, contact spacers 138 may be formed between the source/drain contacts 136 and the second ILD 134. The contact spacers 138 extend around the source/drain contacts 136 in a top-down view (not separately illustrated) and may be circular in the top-down view. The contact spacers 138 may be formed by conformally forming one or more dielectric material(s) in the openings for the source/drain contacts 136 and subsequently etching the dielectric material(s). Acceptable dielectric materials may include silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonitride, or the like, which may be formed by a deposition process such as chemical vapor deposition (CVD), atomic layer deposition (ALD), or the like. Other insulation materials formed by any acceptable process may be used. Any acceptable etch process, such as a dry etch, a wet etch, the like, or a combination thereof, may be performed to pattern the dielectric material(s). The etching may be anisotropic. The dielectric material(s), when etched, have portions left on the sidewalls of the second ILD 134 (thus forming the contact spacers 138).
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In some embodiments, the third ILD 144 is formed of a dielectric material such as PSG, BSG, BPSG, USG, or the like, which may be formed by any suitable deposition process, such as CVD, PECVD, or the like.
In some embodiments, an ESL 142 is formed between the third ILD 144 and the contact spacers 138 (if present), the source/drain contacts 136, and the second ILD 134. The ESL 142 may be formed of a dielectric material having a high etching selectivity to the dielectric material of the third ILD 144, such as silicon nitride, silicon oxide, silicon oxynitride, or the like, which may be formed by any suitable deposition process, such as CVD, ALD, or the like.
Gate vias 146 and upper source/drain vias 148 are formed, respectively, to the gate contacts 118 and the source/drain contacts 136. The gate vias 146 may be physically and electrically coupled to the gate contacts 118. The upper source/drain vias 148 may be physically and electrically coupled to the source/drain contacts 136.
As an example to form the gate vias 146 and the upper source/drain vias 148, openings for the upper source/drain vias 148 are formed through the third ILD 144 and the ESL 142, and openings for the gate vias 146 are formed through the third ILD 144, the ESL 142, the second ILD 134, the ESL 132, and the gate contact masks 120. The openings may be formed using any acceptable photolithography and etching techniques. A liner (not separately illustrated), such as a diffusion barrier layer, an adhesion layer, or the like, and a conductive material are formed in the openings. The liner may include titanium, titanium nitride, tantalum, tantalum nitride, or the like. The conductive material may be cobalt, tungsten, copper, a copper alloy, silver, gold, aluminum, nickel, or the like. A planarization process, such as a CMP, may be performed to remove excess material from the top surface of the third ILD 144. The remaining liner and conductive material form the gate vias 146 and the upper source/drain vias 148 in the openings. The gate vias 146 and the upper source/drain vias 148 may be formed in distinct processes, or may be formed in the same process. Although shown as being formed in the same cross-section, it should be appreciated that each of the gate vias 146 and the upper source/drain vias 148 may be formed in different cross-sections, which may avoid shorting of the contacts.
As subsequently described in greater detail, a first interconnect structure (e.g., a front-side interconnect structure) will be formed over the substrate 50. Some or all of the substrate 50 will then be removed and replaced with a second interconnect structure (e.g., a back-side interconnect structure). Thus, a device layer 140 of active devices is formed between a front-side interconnect structure and a back-side interconnect structure. The front-side and back-side interconnect structures each include conductive features that are connected to the devices of the device layer 140. The conductive features (e.g., interconnects) of the front-side interconnect structure will be connected to front-sides of the upper source/drain regions 84U and the gate electrodes 104 to form functional circuits, such as logic circuits, memory circuits, image sensor circuits, or the like. The lower dummy nanostructures 64L will be replaced with lower source/drain regions, and the conductive features (e.g., power rails) of the back-side interconnect structure will be connected to back-sides of the lower source/drain regions to provide a reference voltage, supply voltage, or the like to the functional circuits.
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The dielectric layers 152 may be formed of a dielectric material. Acceptable dielectric materials include silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), or the like, which may be formed by CVD, ALD, or the like. The dielectric layers 152 may be formed of a low-k dielectric material having a k-value lower than about 3.0. The dielectric layers 152 may be formed of an extra-low-k (ELK) dielectric material having a k-value of less than about 2.5.
The conductive features 154 may include conductive lines and vias. The conductive vias may extend through respective ones of the dielectric layers 152 to provide vertical connections between layers of conductive lines. The conductive features 154 may be formed by a damascene process, such as a single damascene process, a dual damascene process, or the like. In a damascene process, a dielectric layer 152 is patterned utilizing photolithography and etching techniques to form trenches and via openings corresponding to the desired pattern of the conductive features 154. The trenches and via openings may then be filled with a conductive material. Suitable conductive materials include copper, aluminum, tungsten, cobalt, gold, combinations thereof, or the like, which may be formed by electroplating or the like.
The front-side interconnect structure 150 includes any desired number of layers of the conductive features 154. The conductive features 154 are connected to features of the underlying devices (e.g., the upper source/drain regions 84U and the gate electrodes 104) through the gate contacts 118, the source/drain contacts 136, the gate vias 146, and the upper source/drain vias 148 to form functional circuits. Thus, the conductive features 154 interconnect the devices of the device layer 140.
After the front-side interconnect structure 150 is formed, a support substrate (not separately illustrated) may be bonded to a top surface of the front-side interconnect structure 150. The support substrate may be a glass support substrate, a ceramic support substrate, a semiconductor substrate (e.g., a silicon substrate), a wafer (e.g., a silicon wafer), or the like, bonded to the front-side interconnect structure 150 by dielectric-to-dielectric bonds or the like. The support substrate may provide structural support during subsequent processing steps and in the completed device. After the support substrate is bonded to the front-side interconnect structure 150, the intermediate structure is flipped so that the back-side of the device layer 140 may be processed. The back-side of the device layer 140 refers to the side opposite to the front-side of the device layer 140 on which the front-side interconnect structure 150 is formed.
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In some embodiments, the source/drain regions 84 (including the lower source/drain regions 84L and the upper source/drain regions 84U) exert stress in the respective channel regions of the semiconductor nanostructures 66, thereby improving performance. The source/drain regions 84 are formed such that each gate electrode 104 is disposed between respective neighboring pairs of the source/drain regions 84.
Optionally, lower LDD regions 82L are formed in the lower source/drain recesses 162. The lower LDD regions 82L are formed on the semiconductor nanostructures 66 and the lower source/drain regions 84L are formed on the lower LDD regions 82L, such that the lower LDD regions 82L are between the lower source/drain regions 84L and the semiconductor nanostructures 66. The lower LDD regions 82L may be epitaxially grown in a similar manner to the upper source/drain regions 84U, e.g., using appropriate masking steps to form the lower LDD regions 82L in the p-type region 50P of acceptable material appropriate for p-type nanostructure-FETs (previously described) to form the lower LDD regions 82L in the n-type region 50N of acceptable material appropriate for n-type nanostructure-FETs (previously described). The lower LDD regions 82L may be implanted with appropriate type (e.g., n-type or p-type) dopants to form LDD regions, followed by an anneal. The n-type and/or p-type dopants for LDD regions may be any of the previously described dopants. The LDD regions may have a dopant concentration in a range from 1015 atoms/cm3 to 1019 atoms/cm3. In some embodiments, the lower LDD regions 82L may be in situ doped during growth.
In this embodiment, the surfaces of the upper LDD regions 82U and the lower LDD regions 82L are aligned with or recessed below the respective surfaces of the gate spacers 72. In another embodiment (subsequently described for
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In some embodiments, an ESL 172 is formed between the fourth ILD 174 and the conductive pads 166 and the isolation regions 90. The ESL 172 may be formed of a dielectric material having a high etching selectivity to the dielectric material of the fourth ILD 174, such as silicon nitride, silicon oxide, silicon oxynitride, or the like, which may be formed by any suitable deposition process, such as CVD, ALD, or the like.
Lower source/drain vias 178 are formed through the fourth ILD 174 and the ESL 172, to the conductive pads 166. The lower source/drain vias 178 may be physically and electrically coupled to the conductive pads 166. As an example to form the lower source/drain vias 178, openings for the lower source/drain vias 178 are formed through the fourth ILD 174 and the ESL 172. The openings may be formed using any acceptable photolithography and etching techniques. A liner (not separately illustrated), such as a diffusion barrier layer, an adhesion layer, or the like, and a conductive material are formed in the openings. The liner may include titanium, titanium nitride, tantalum, tantalum nitride, or the like. The conductive material may be cobalt, tungsten, copper, a copper alloy, silver, gold, aluminum, nickel, or the like. A planarization process, such as a CMP, may be performed to remove excess material from the bottom surface of the fourth ILD 174. The remaining liner and conductive material form the lower source/drain vias 178 in the openings.
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The dielectric layers 182 may be formed of a dielectric material. Acceptable dielectric materials include silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), or the like, which may be formed by CVD, ALD, or the like. The dielectric layers 182 may be formed of a low-k dielectric material having a k-value lower than about 3.0. The dielectric layers 182 may be formed of an extra-low-k (ELK) dielectric material having a k-value of less than about 2.5.
The conductive features 184 may include conductive lines and vias. The conductive vias may extend through respective ones of the dielectric layers 182 to provide vertical connections between layers of conductive lines. The conductive features 184 may be formed by a damascene process, such as a single damascene process, a dual damascene process, or the like. In a damascene process, a dielectric layer 182 is patterned utilizing photolithography and etching techniques to form trenches and via openings corresponding to the desired pattern of the conductive features 184. The trenches and via openings may then be filled with a conductive material. Suitable conductive materials include copper, aluminum, tungsten, cobalt, gold, combinations thereof, or the like, which may be formed by electroplating or the like.
The back-side interconnect structure 180 includes any desired number of layers of the conductive features 184. The conductive features 184 form a power distribution network for the devices of the device layer 140. Some or all of the conductive features 184 are power rails 184P, which are conductive lines that electrically connect the lower source/drain regions 84L to a reference voltage, supply voltage, or the like, through the lower source/drain vias 178. By placing the power rails 184P at a back-side of the device layer 140 rather than at a front-side of the device layer 140, advantages may be achieved. For example, a gate density of the devices of the device layer 140 may be increased. Further, the back-side of the device layer 140 may accommodate wider power rails, reducing resistance and increasing efficiency of power delivery to the devices of the device layer 140. For example, a width of the conductive features 184 may be at least twice a width of a first level conductive line (e.g., conductive line 154L) of the front-side interconnect structure 150.
The semiconductor nanostructures 66 are vertical nanostructures, such that the gate electrodes 104 wrap around the semiconductor nanostructures 66 in a plane P that is perpendicular to a direction extending between the back-side interconnect structure 180 and the front-side interconnect structure 150. The plane P was parallel to the major surface of the substrate 50 (see
Embodiments may achieve advantages. Forming the gate electrodes 104 so that the outer sidewalls of the gate electrodes 104 are aligned with the outer sidewalls of the gate dielectrics 102 allows a gate contact 118 to be formed between and coupled to multiple gate electrodes 104. Multiple gate electrodes 104 may thus be coupled by a same gate contact 118, which may be advantageous when fabricating some types of circuits, such as CMOS inverters. For example, the gate electrode 104 of a pull-up transistor may be coupled to the gate electrode 104 of a pull-down transistor without utilizing higher-level interconnects of the front-side interconnect structure 150 or the back-side interconnect structure 180. The density of the resulting integrated circuits may thus be improved.
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In an embodiment, a device includes: a lower source/drain region; an upper source/drain region; a nanostructure between the upper source/drain region and the lower source/drain region; a gate structure extending into a sidewall of the nanostructure, the gate structure including a gate dielectric and a gate electrode, an outer sidewall of the gate electrode being aligned with an outer sidewall of the gate dielectric; and a gate contact adjacent the gate structure, the gate contact extending along the outer sidewall of the gate electrode and the outer sidewall of the gate dielectric. In some embodiments, the device further includes: a gate spacer between the gate structure and the upper source/drain region, the gate dielectric extending along an outer sidewall of the gate spacer. In some embodiments, the device further includes: an inter-layer dielectric around the upper source/drain region and the nanostructure, the gate contact extending through the inter-layer dielectric. In some embodiments, the device further includes: a conductive pad on the upper source/drain region; and a contact mask on the gate contact, a top surface of the contact mask being coplanar with a top surface of the conductive pad. In some embodiments of the device, the top surface of the contact mask is coplanar with a top surface of the gate dielectric. In some embodiments of the device, the top surface of the contact mask is disposed above a top surface of the gate dielectric. In some embodiments, the device further includes: an inter-layer dielectric on the conductive pad and the contact mask; a source/drain contact extending through the inter-layer dielectric to the conductive pad; and a via extending through the inter-layer dielectric and the contact mask to the gate contact.
In an embodiment, a device includes: a front-side interconnect structure; a back-side interconnect structure; and a device layer between the back-side interconnect structure and the front-side interconnect structure, the device layer including: a pull-up transistor including a first nanostructure and a first gate electrode, the first gate electrode extending into a first sidewall of the first nanostructure in a first direction, the first direction perpendicular to a second direction extending between the back-side interconnect structure and the front-side interconnect structure; a pull-down transistor including a second nanostructure and a second gate electrode, the second gate electrode extending into a second sidewall of the second nanostructure in the first direction; and a gate contact between the pull-up transistor and the pull-down transistor in a plane that is parallel to the first direction, the gate contact physically contacting the first gate electrode and the second gate electrode. In some embodiments of the device: the pull-up transistor further includes a first lower source/drain region and a first upper source/drain region, the first nanostructure disposed between the first lower source/drain region and the first upper source/drain region; and the pull-down transistor further includes a second lower source/drain region and a second upper source/drain region, the second nanostructure disposed between the second lower source/drain region and the second upper source/drain region. In some embodiments of the device, the back-side interconnect structure includes: a supply power rail connected to the first lower source/drain region; and a reference power rail connected to the second lower source/drain region. In some embodiments of the device, the front-side interconnect structure includes: an input interconnect connected to the gate contact; and an output interconnect connected to the first upper source/drain region and the second upper source/drain region. In some embodiments of the device, the first gate electrode is wrapped around the first nanostructure in the plane that is parallel to the first direction, and the second gate electrode is wrapped around the second nanostructure in the plane that is parallel to the first direction. In some embodiments of the device, the first nanostructure and the second nanostructure are each nanobars.
In an embodiment, a method includes: forming a nanostructure between a first gate spacer and a second gate spacer; forming a sidewall recess by recessing a sidewall of the nanostructure from a sidewall of the first gate spacer and from a sidewall of the second gate spacer; forming a gate structure in the sidewall recess and on the sidewall of the nanostructure; and depositing an inter-layer dielectric around the gate structure; and forming a gate contact through the inter-layer dielectric to contact a sidewall of the gate structure. In some embodiments, the method further includes: patterning a contact opening in the inter-layer dielectric, the contact opening exposing the sidewall of the gate structure, the gate contact being formed in the contact opening. In some embodiments, the method further includes: recessing a top surface of the gate contact from a top surface of the inter-layer dielectric; and forming a contact mask on the top surface of the gate contact, a top surface of the contact mask being coplanar with the top surface of the inter-layer dielectric. In some embodiments, the method further includes: forming an upper source/drain region above the nanostructure; and forming a lower source/drain region below the nanostructure. In some embodiments of the method, forming the gate structure includes: depositing a gate dielectric layer in the sidewall recess; depositing a gate electrode layer on the gate dielectric layer and in the sidewall recess; and removing a portion of the gate electrode layer outside of the sidewall recess with an etch-back process. In some embodiments of the method, the etch-back process selectively etches a material of the gate electrode layer at a faster rate than a material of the gate dielectric layer. In some embodiments of the method, the etch-back process includes a dry etch performing using chlorine as an etchant.
The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.
This application claims the benefit of U.S. Provisional Application No. 63/481,006, filed on Jan. 23, 2023, which application is hereby incorporated herein by reference.
| Number | Date | Country | |
|---|---|---|---|
| 63481006 | Jan 2023 | US |
