Patent Application
20240055416
The present application claims the benefit of priority to Chinese Patent Application No. CN 202210955805.6, entitled “WAFER-LEVEL PACKAGING STRUCTURE AND METHOD FOR PREPARING SAME”, filed with CNIPA on Aug. 10, 2022, the disclosure of which is incorporated herein by reference in its entirety for all purposes.
The present disclosure generally relates to the field of semiconductor packaging technology, and in particular, relates to a wafer-level packaging structure and a method for preparing the same.
As electronic products such as computers, tablets, mobile phones, car controls, household appliance controls, and Internet of things (IoT) objects have become smaller, faster, more energy-efficient and higher-performing, there is an increasing demand for the miniaturization and integration of chips on these objects. Packaging more functional modules onto a single die has become an important trend in semiconductor packaging.
To achieve product integration, active devices like switches, low noise amplifiers, power amplifiers, basebands, and application processors are integrated onto a single die. Additionally, more wafer-level packaging requires the introduction of RF Integrated Passive Devices (IPDs) like filters to reduce the size of RF modules.
Most related technologies use planar IPDs. Since these IPDs are formed on a 2D plane parallel to the silicon substrate, they can't meet the integration requirements of RF packaging structures or packaging performance, especially at high frequencies.
In related technology, independent IPDs can also be fixed to the substrate using flip-chip bonding or wire bonding. Using these methods to introduce IPDs requires additional packaging space and may cause deterioration of IPD performance due to the introduction of solder balls or wire bonding.
Therefore, integrating 3D IPDs into wafer-level packaging structures is a challenge that needs to be addressed by technical professionals in this field.
The present disclosure provides a wafer-level packaging structure, including a molding layer, and a 3D IPD structure fabricated in the molding layer, wherein the molding layer includes a first surface and a second surface opposite to the first surface.
The present disclosure further provides a method for preparing a wafer-level packaging structure, including: preparing a molding layer; and forming a 3D IPD structure inside the molding layer.
The wafer-level packaging structure of the present disclosure can integrate various electronic chips and components such as millimeter wave antenna/capacitor/inductor/electric crystal/GPU/PMU/DDR/flash memory/filter, etc., with higher flexibility and wider compatibility, thus reducing package size and package cost.
The embodiments of the present disclosure will be described below. Those skilled can easily understand disclosure advantages and effects of the present disclosure according to contents disclosed by the specification. The present disclosure can also be implemented or applied through other different exemplary embodiments. Various modifications or changes can also be made to all details in the specification based on different points of view and applications without departing from the spirit of the present disclosure.
Refer to
The present disclosure provides a wafer-level packaging structure, as shown in
As an example, a material of the molding layer 1 includes one or more of epoxy-based resin, liquid thermosetting epoxy resin, and plastic molding compound, and techniques of forming the molding layer 1 include one of compression molding, transfer molding, liquid seal potting molding, vacuum lamination, and spin coating. A thickness of the molding layer 1 ranges from 10 um to 200 um, for example, it can be 30 um, 50 um, 80 um, 100 um, 150 um, 180 um, etc.
As an example, the 3D IPD structure includes one or more of a 3D inductive IPD structure 21, a 3D capacitive IPD structure 22, and a 3D resistive IPD structure.
In one example, as shown in
As an example, a material of the first metal solder pads 211 includes, but is not limited to, copper. Techniques of forming the first metal solder pads 211 include one of physical vapor deposition, chemical vapor deposition, sputtering, electroplating, and chemical plating. As an example, the first metal solder pads 211 are arranged parallel to each other.
As an example, the metal pillar 212 includes one of a copper pillar and a titanium pillar, and the method for forming the metal pillar 212 includes one of physical vapor deposition (PVD), chemical vapor deposition (CVD), sputtering, electroplating, and chemical plating.
As an example, a material of the second metal solder pads 213 includes, but is not limited to, copper. Techniques of forming the second metal solder pads 213 include one of physical vapor deposition, chemical vapor deposition, sputtering, electroplating, and chemical plating. As an example, the second metal solder pads 213 are arranged parallel to each other.
As an example, as shown in
Although only a 3D inductive IPD structure 21 and a 3D capacitive IPD structure 22 are described, in other embodiments there may be other 3D IPD structures in the packaging structure.
As an example, as shown in
The first wiring metal layer 32 and the second wiring metal layer 42 are not shown in
As an example, materials of the first dielectric layer 31 and the second dielectric layer 41 include at least one of epoxy resin, silicone, polyimide, polybenzoxazoles, benzocyclobutene, silicon oxide, phosphor silica glass, fluorine containing glass, and other suitable materials.
As an example, materials of the first wiring metal layer 32 and the second wiring metal layer 42 include at least one of copper, aluminum, and titanium. Techniques of forming the first wiring metal layer 32 and the second wiring metal layer 42 include one of physical vapor deposition, chemical vapor deposition, sputtering, electroplating, and chemical plating, The first wiring metal layer 32 and the second wiring metal layer 42 are single-layer or multiple-layer structures.
The wafer-level packaging structure may also include other structural layers to form different types of wafer-level packaging structures.
As an example, as shown in
As another example, as shown in
Material of the solder balls 7, 8 include, but are not limited to, copper or nickel. The first wiring metal layer 32 may have solder balls 7, 8 directly formed on its surface, or may have metal pillars (not shown) formed thereon first and then have solder balls 7, 8 formed on the metal pillars.
It should be noted that the wafer-level packaging structure of the present disclosure can serve as an RF ASIC wafer-level packaging structure or a fan-out wafer-level packaging structure, and it can also serve as any other packaging structure that requires the integration of a 3D IPD structure.
The present disclosure also provides a method for preparing a wafer-level packaging structure, using which the above-mentioned wafer-level packaging structure can be obtained. The method includes: first preparing a molding layer 1; and forming a 3D IPD structure 2 in the molding layer.
As an example, the 3D IPD structure includes one or more of a 3D inductive IPD structure 21, a 3D capacitive IPD structure 22, and a 3D resistive IPD structure. Depending on the specific packaging type, the 3D IPD structure 2 can also be other suitable passive devices.
As an example, the 3D IPD structure 2 is a 3D inductive IPD structure 21, and forming the 3D inductive IPD structure 21 in the molding layer 1 may include the steps described below.
First, providing a substrate 10 having a release layer 11 as shown in
As an example, the substrate 10 includes one of a glass substrate, a metal substrate, a semiconductor substrate, a polymer substrate, and a ceramic substrate. In one example, the substrate 10 is a semiconductor substrate, such as a silicon wafer. The shape of the substrate 10 may be round, square or any other desired shapes. In one example, the substrate 10 is used to prevent structural layers above it from cracking, warping, breaking, etc. during subsequent manufacturing processes.
The release layer 11 is used to subsequently separate the substrate 10 from the molding layer 1 and the first metal solder pads 211. The release layer 11 includes one of a tape layer and a polymer layer, which is applied to the substrate 10 by spin coating and then cured by laser curing, ultra-violet (UV) curing, or thermal curing.
As an example, a material of the first metal solder pads 211 includes, but is not limited to, copper. Techniques of forming the first metal solder pads 211 include one of physical vapor deposition, chemical vapor deposition, sputtering, electroplating, and chemical plating. As an example, the first metal solder pads 211 are arranged parallel to each other.
Then, as shown in
As an example, the metal pillar 212 includes one of a copper pillar and a titanium pillar, and the method for forming the metal pillar 212 includes one of the processes such as physical vapor deposition (PVD), chemical vapor deposition (CVD), sputtering, electroplating, and chemical plating.
Next, a molding layer 1 covering the metal pillars 212 and the first metal solder pads 211 is formed over the release layer 11, as shown in
As an example, a material of the molding layer 1 includes one or more of epoxy-based resin, liquid thermosetting epoxy resin, and plastic molding compound, and techniques of forming the molding layer 1 include one of compression molding, transfer molding, liquid seal potting molding, vacuum lamination, and spin coating. The molding layer 1 as shown in
Next, second metal solder pads 213 are formed over the molding layer 1 as shown in
As an example, a material of the second metal solder pads 213 includes, but is not limited to, copper. Techniques of forming the second metal solder pads 213 include one of physical vapor deposition, chemical vapor deposition, sputtering, electroplating, and chemical plating. As an example, the second metal solder pads 213 are arranged parallel to each other.
Finally, as shown in
Refer to
As another example, the 3D IPD structure 2 is a 3D capacitive IPD structure 22, and forming the 3D capacitive IPD structure 22 in the molding layer 1 may include the steps described below.
First, providing a substrate having a release layer, forming a molding layer on a surface of the release layer.
Next, etching the molding layer to form at least one pair of parallel openings exposing the release layer;
Then, filling the openings with metal materials to form at least one pair of metal layers 221 parallel to each other, wherein the at least one pair of metal layers 221 are spaced apart and parallel to each other, wherein said pair of metal layers 221 are perpendicular to one of the first and second surfaces of the molding layer;
Finally, removing the release layer to remove the substrate, thereby forming the 3D capacitive IPD structure 22, as shown in
Although only one method for prepare a 3D inductive IPD structure 21 or a 3D capacitive IPD structure 22 is described, in other examples there may be other methods for preparing corresponding 3D IPD structures.
As an example, as shown in
The first wiring metal layer 32 and the second wiring metal layer 42 are not shown in
As an example, materials of the first dielectric layer 31 and the second dielectric layer 41 include at least one of epoxy resin, silicone, polyimide, polybenzoxazoles, benzocyclobutene, silicon oxide, phosphor silica glass, fluorine containing glass, and other suitable materials.
As an example, materials of the first wiring metal layer 32 and the second wiring metal layer 42 include at least one of copper, aluminum, and titanium. Techniques of forming the first wiring metal layer 32 and the second wiring metal layer 42 include one of physical vapor deposition, chemical vapor deposition, sputtering, electroplating, and chemical plating. The first wiring metal layer 32 and the second wiring metal layer 42 are single-layer or multiple-layer structures.
Subsequently, the method may include other steps to form different types of wafer-level packaging structures.
As an example, where an RF ASIC wafer-level packaging structure needs to be formed, in a way as shown in
First, soldering an RF ASIC chip 9 to the second rewiring layer 4, with the RF ASIC chip 9 connected to the second wiring metal layer (not illustrated).
Then, forming solder balls 8 on a surface of the first rewiring layer 3, with the solder balls 8 connected to the first wiring metal layer (not shown), thereby forming the RF ASIC wafer-level packaging structure shown in
As another example, where a fan-out wafer-level packaging structure needs to be formed, as shown in
First, forming metal connection pillars 5 in the molding layer 1, with the metal connection pillars 5 connected to the first wiring metal layer 32 and the second wiring metal layer 42. It is to be noted that the preparation of the metal connection pillars 5 can be carried out simultaneously with the preparation of the 3D IPD structure 2, i.e., while preparing the 3D IPD structure 2 in the molding layer 1, the method includes etching the molding layer 1 and depositing metal material to form the metal connection pillars 5.
Then, soldering chips 6 to the second rewiring layer 42, with the chips 6 connected to the second wiring metal layer 42. Cu—Cu bonding may be used to solder the chips 6.
Finally, forming solder balls 7 on a surface of the first rewiring layer 3 away from the molding layer 1, with the solder balls connected to 7 the first wiring metal layer 32, thereby forming a fan-out wafer-level packaging structure as shown in
Material of the solder balls 7, 8 include, but are not limited to, copper or nickel. The first wiring metal layer 32 may have solder balls 7, 8 directly formed on its surface, or may have metal pillars (not shown) formed thereon first and then have solder balls 7, 8 formed on the metal pillars.
It should be noted that the methods of the present disclosure can be used to prepare not only the RF ASIC wafer-level packaging structure and fan-out wafer-level packaging structure as described above, but can be also used to prepare any other devices that require the integration of a 3D IPD structure 2.
The method for preparing the wafer-level packaging structure of the present disclosure enables the preparation of higher performance system-based packaging structures by preparing integrated 3D IPD structures in the molding layer. In addition, the wafer-level packaging structures of the present disclosure can integrate various electronic chips and components such as millimeter wave antenna/capacitor/inductor/electric crystal/GPU/PMU/DDR/flash memory/filter, etc., with higher flexibility and wider compatibility, thus reducing package size and package cost.
Therefore, the present disclosure effectively overcomes various shortcomings in the existing technology and has high industrial utilization value.
The above-mentioned embodiments are just used for exemplarily describing the principle and effects of the present disclosure instead of limiting the present disclosure. Those skilled in the art can make modifications or changes to the above-mentioned embodiments without going against the spirit and the range of the present disclosure. Therefore, all equivalent modifications or changes made by those who have common knowledge in the art without departing from the spirit and technical concept disclosed by the present disclosure shall be still covered by the claims of the present disclosure.
| Number | Date | Country | Kind |
|---|---|---|---|
| 202210955805.6 | Aug 2022 | CN | national |
