Patent Application
20250212324
The present invention relates to wiring boards.
Conventionally, for example, a packaging technique using through-silicon vias (TSVs) has been known as a packaging technique for large-scale integrated circuits (LSIs). Silicon substrates provided with TSVs, i.e., silicon interposers, are wiring boards connecting components having different inter-terminal distances, such as integrated circuit (IC) chips and printed circuit boards with different wiring design rules.
In silicon interposers, the silicon, which is a semiconductor, needs to be electrically insulated from the through-electrodes. Specifically, an insulation treatment is required to be performed on the silicon substrate after the through-holes are formed. Silicon substrates are expensive. Therefore, silicon interposers raise an issue of increase in production costs. In view of this, attention has been focused on glass interposers, which are obtained by forming through-glass vias (TGVs) or the like in an inexpensive, large-area glass substrate and dividing the substrate into individual pieces.
In the TGV technique, it is necessary to form through-holes in glass substrates. Various methods can be used for forming through-holes in glass substrates.
For example, as described in PTL 1, there is known a technique for forming through-holes in glass substrates by applying a laser beam using a pulsed YAG laser.
PTL 2 describes a method of forming fine holes in a photosensitive glass substrate. In this method, first, a photosensitive glass substrate is irradiated with ultraviolet light through a photomask to form latent images on the photosensitive glass substrate. The photosensitive glass substrate is then heat-treated to cause crystallization in the portions where the latent images are formed. Next, at the center of each portion where a latent image is formed, a hole smaller than the latent image is formed by laser irradiation. After that, the crystallized portions are selectively etched using hydrofluoric acid. In this way, holes larger than the holes formed by laser irradiation are produced.
PTL 3 describes a method of drilling holes in a glass plate using a pair of core drills coaxially arranged and facing each other with the glass plate sandwiched therebetween.
PTL 4 describes a method of simultaneously forming through-holes in a glass substrate and thinning the glass substrate by etching. In this method, the glass substrate is irradiated with a laser beam first to produce modified portions. Next, one surface of the glass substrate is etched using hydrofluoric acid to thin the glass substrate, while forming through-holes by removing the modified portions.
Glass interposers can also be provided with inductors or capacitors PTL 5 describes a glass core wiring board integrated with an LC filter which is a combination an inductor and a capacitor. In this wiring board, the capacitor has a structure called MIM (Metal/Insulator/Metal) in which a metal layer, a dielectric layer, and a metal layer are laminated in the thickness direction of the glass core substrate. In this wiring board, the inductor has a structure in which the helical axis is parallel to the major surface of the glass core substrate and helically extends passing through two rows of through-holes provided in the glass core substrate.
[Citation List] [Patent Literature] PTL 1: JP2000-61667A; PTL 2: JP2001-105398A; PTL3: JP54-126215A; PTL 4: WO2019/235617; PTL 5: JP2021-166257A.
The present invention aims to provide a technique with which disconnection is less likely to occur between a wiring layer provided on a glass substrate and TGVs provided in the glass substrate.
According to an aspect of the present invention, there is provided a wiring board including a glass substrate having a first surface and a second surface, which is to a rear of the first surface, and provided with one or more first through-holes each extending from the first surface to the second surface; a first conductor layer including a first copper layer facing the first surface, and a hydrofluoric acid resistant metal layer interposed between the first copper layer and the glass substrate and covering openings of the one or more first through-holes on the first surface side, the first conductor layer having recesses in a surface thereof at positions of the one or more first through-holes on the glass substrate side, each of the recesses having an opening whose contour is wider than and surrounding the opening of a corresponding one of the one or more first through-holes on the first surface side; and a second conductor layer including an adhesion layer covering the side walls of the one or more first through-holes, inner surfaces of the recesses, and regions of the second surface surrounding openings of the one or more first through-holes on the second surface side, a seed layer provided on the adhesion layer, and a second copper layer provided on the seed layer, wherein a sum T1+T2 of a thickness T1 of the adhesion layer and a thickness T2 of the seed layer is greater than or equal to a thickness T3 of the hydrofluoric acid resistant metal layer.
According to another aspect of the present invention, there is provided the wiring board according to the above aspect, wherein the hydrofluoric acid resistant metal layer is provided with one or more second through-holes at positions of the one or more first through-holes, and the one or more second through-holes form the recesses in the surface of the first conductor layer on the glass substrate side.
According to still another aspect of the present invention, there is provided the wiring board according to any of the above aspects, wherein the thickness T1 is greater than or equal to the thickness T3.
According to still another aspect of the present invention, there is provided the wiring board according to any of the above aspects, wherein the thickness T2 is greater than or equal to a sum T1+T3 of the thickness T1 and the thickness T3.
According to still another aspect of the present invention, there is provided the wiring board according to any of the above aspects, wherein the thickness T2 is 0.5 μm or less.
According to still another aspect of the present invention, there is provided the wiring board according to any of the above aspects, wherein the thickness T1 is in a range of 10 nm to 0.5 μm, the thickness T2 is in a range of 100 nm to 0.5 μm, and the thickness T3 is in a range of 10 nm to 0.5 μm.
According to still another aspect of the present invention, there is provided the wiring board according to any of the above aspects, further including a dielectric layer provided on the first conductor layer, and an upper electrode provided on the dielectric layer, wherein a portion of the first conductor layer facing the upper electrode serves as a lower electrode, and the upper electrode, the dielectric layer, and the lower electrode constitute a capacitor.
According to still another aspect of the present invention, there is provided the wiring board according to the above aspect, wherein the lower electrode covers at least one opening of the one or more first through-holes on the first surface side.
According to still another aspect of the present invention, there is provided the wiring board according to any of the above aspects, wherein the one or more first through-holes are a plurality of first through-holes, and part of the first conductor layer and part of the second conductor layer constitute a solenoid coil.
According to still another aspect of the present invention, there is provided the wiring board according to any of the above aspects, wherein the wiring board further includes a dielectric layer provided on the first conductor layer, and an upper electrode provided on the dielectric layer, a portion of the first conductor layer facing the upper electrode serves as a lower electrode, and the upper electrode, the dielectric layer, and the lower electrode constitute a capacitor; the one or more first through-holes are a plurality of first through-holes, and part of the first conductor layer and part of the second conductor layer constitute a solenoid coil; and the capacitor and the solenoid coil constitute an LC filter.
It should be noted that LC filters are also referred to as LC frequency filters. LC filters have a structure in which an inductor (L) and a capacitor (C) are combined with each other. LC filters utilize the resonance phenomenon to pass electrical signals of specific frequencies through circuits and block signals of other frequencies, and have functions as band-pass filters, low-pass filters, high-pass filters, or diplexers.
According to still another aspect of the present invention, there is provided the wiring board according to any of the above aspects, wherein the hydrofluoric acid resistant metal layer is made of a material selected from the group consisting of chromium, nickel, and nickel-chromium alloys.
According to still another aspect of the present invention, there is provided the wiring board according to any of the above aspects, wherein the adhesion layer is made of one or more materials selected from the group consisting of titanium, chromium, and nickel, or made of an oxide thereof, and the seed layer is made of copper.
According to still another aspect of the present invention, there is provided the wiring board according to any of the above aspects, wherein the wiring board serves as an interposer.
According to still another aspect of the present invention, there is provided a packaged device including the wiring board according to any of the above aspects, and functional devices mounted on the wiring board.
The term functional devices refers to devices which are activated with a supply of electrical power and/or electrical signals, devices which output electrical power and/or electrical signals due to external stimulation, or devices which are activated with a supply of electrical power and/or electrical signals and which output electrical power and/or electrical signals due to external stimulation. Functional devices may be, for example, in the forms of chips, such as semiconductor chips or chips in which circuits or elements are formed on a substrate, such as a glass substrate, made of a material other than semiconductor materials. Functional devices can include, for example, one or more from among LSIs, memories, imaging devices, light-emitting devices, and (Micro Electro Mechanical Systems) MEMSs. The MEMSs may be, for example, one or more from among pressure sensors, acceleration sensors, gyro sensors, tilt sensors, microphones, and acoustic sensors. According to an example, functional devices may be semiconductor chips including LSIs.
According to still another aspect of the present invention, there is provided a method of producing a wiring board, including preparing a glass substrate having a first surface and a second surface which is to a rear of the first surface; irradiating the glass substrate with a laser beam to form one or more modified portions in the glass substrate; forming a first conductor layer on the first surface, the first conductor layer including a first copper layer facing the first surface, and a hydrofluoric acid resistant metal layer interposed between the first copper layer and the glass substrate to cover the one or more modified portions; etching the second surface using an etching solution containing hydrogen fluoride to form recesses in the second surface and form one or more first through-holes at positions of the one or more modified portions; subjecting portions of the hydrofluoric acid resistant metal layer exposed in the one or more first through-holes to wet etching to form recesses in a surface of the first conductor layer on the glass substrate side; forming an adhesion layer covering side walls of the one or more first through-holes, inner surfaces of the recesses, and the second surface; forming a seed layer on the adhesion layer; and forming a second copper layer on the seed layer, wherein the adhesion layer, the seed layer, and the hydrofluoric acid resistant metal layer are formed so that a sum T1+T2 of a thickness T1 of the adhesion layer and a thickness T2 of the seed layer is greater than or equal to a thickness T3 of the hydrofluoric acid resistant metal layer.
According to still another aspect of the present invention, there is provided the method of producing a wiring board according to the above aspect, further including allowing a first support to support the glass substrate so that the second surface faces the first support, prior to irradiating the glass substrate with the laser beam; and removing the first support from the glass substrate after forming the first conductor layer but before forming the one or more first through-holes.
According to still another aspect of the present invention, there is provided the method of producing a wiring board according to any of the above aspects, wherein the wet etching for the hydrofluoric acid resistant metal layer is performed so that one or more second through-holes are formed in the hydrofluoric acid resistant metal layer.
According to still another aspect of the present invention, there is provided the method of producing a wiring board according to any of the above aspects, further including allowing a second support to support a composite including the glass substrate and the first conductor layer so that the first conductor layer faces the second support, after forming the first conductor layer but before forming the one or more first through-holes.
According to the present invention, there is provided a technique with which disconnection is less likely to occur between a wiring layer provided on a glass substrate and TGVs provided in the glass substrate.
Referring to the drawings, some embodiments of the present invention will be described. The embodiments described below are more specific implementations of any of the aspects set forth above. The matters described below can be incorporated into the aspects set forth above, either alone or in combination.
The embodiments described below are merely examples of the configurations for specifically implementing the technical ideas of the present invention, and the technical ideas of the present invention should not be construed as being limited to the materials, shapes, structures, and the like of the components described below. Various modifications can be made to the technical ideas of the present invention within the technical scope defined by the claims.
It should be noted that components having equivalent or similar functions are designated with like reference signs in the drawings referenced below to omit repeated explanations. The drawings are only schematic, and the relationship between the dimensions in one direction and the dimensions in another direction, the relationship between the dimensions of one member and the dimensions of other members, and the like, may differ from the actual relationships.
A wiring board 1 shown in
The wiring board 1 includes a glass substrate 10, a first conductor layer 20, a dielectric layer 31, an upper electrode 32, an interlayer insulating film 40, a conductor layer 50, an insulating layer 60, a second conductor layer 70, an interlayer insulating film 80, a conductor layer 90, and an insulating layer 100.
The glass substrate 10 has a first surface S1 and a second surface S2 which is the rear of the first surface S1. The first and second surfaces S1 and S2 are parallel to each other.
The glass substrate 10 is provided with one or more first through-holes (a plurality of first through-holes in this example) extending from the first surface S1 to the second surface S2. Each of the first through-holes tapers from the second surface S2 toward the first surface S1.
The first conductor layer 20 comprises conductor patterns provided on the first surface S1. The conductor patterns each include a land, a wiring portion, and a lower electrode of a capacitor 30 described later. The first conductor layer 20 serves as a first wiring layer.
The first conductor layer 20 has a multilayer structure. Specifically, the first conductor layer 20 includes a first copper layer 24 facing the first surface S1, and a hydrofluoric acid resistant metal layer 21 interposed between the first copper layer 24 and the glass substrate 10. As shown in
The first conductor layer 20 covers the openings of the first through-holes on the first surface S1 side. The surface of the first conductor layer 20 on the glass substrate 10 side has recesses at positions of the first through-holes. In this example, the hydrofluoric acid resistant metal layer 21 is provided with second through-holes at positions of the first through-holes. The second through-holes form the recesses mentioned above in the surface of the first conductor layer 20 on the glass substrate 10 side.
The contour of the opening of each of the recesses provided in the surface of the first conductor layer 20 (hereinafter may also be referred to as first opening) is wider than and surrounds the opening of the corresponding one of the first through-holes on the first surface S1 side (hereinafter may also be referred to as second opening). That is, the contour of the orthogonal projection of each first opening onto a plane perpendicular to the thickness direction of the wiring board 1 is wider than and surrounds the orthogonal projection of the corresponding second opening onto this plane. The distance from the contour of the orthogonal projection of the first opening onto the plane to the orthogonal projection of the corresponding second opening onto the plane, i.e., the width of an undercut produced by side etching described later, is in the range of 1 μm to 10 μm according to an example, and in the range of 0.1 μm to 5 μm according to another example.
The hydrofluoric acid resistant metal layer 21 is made of a metal material having superior resistance to etching using hydrofluoric acid, compared to the glass substrate 10. For example, the hydrofluoric acid resistant metal layer 21 may be made of a material selected from the group consisting of chromium, nickel, and nickel-chromium alloys. The hydrofluoric acid resistant metal layer 21 has a thickness T3 which is preferred to be in the range of 10 nm to 500 nm, and is more preferred to be in the range of 0.02 μm to 0.08 μm.
The adhesion layer 22 and the seed layer 23 are laminated in this order on the hydrofluoric acid resistant metal layer 21. The adhesion layer 22 and the seed layer 23 can be made of the materials exemplified respectively for an adhesion layer 72 and a seed layer 73 described later. The adhesion layer 72 and the seed layer 73 are provided when the first copper layer 24 is formed by electrolytic plating. The adhesion layer 72 may be omitted. Furthermore, when the first copper layer 24 is formed using other methods such as electroless plating or sputtering, both the adhesion layer 22 and the seed layer 23 may be omitted.
The dielectric layer 31 and the upper electrode 32 are laminated in this order on part of the first conductor layer 20. The portion of the first conductor layer 20 facing the upper electrode 32 serves as a lower electrode. The upper electrode 32, the dielectric layer 31, and the lower electrode form a capacitor 30, specifically a MIM capacitor.
In the example shown in
Although the capacitor 30 is disposed so as to face the first surface S1 in this example, the capacitor may be disposed on the second surface S2 side. Alternatively, while the capacitor 30 is disposed so as to face the first surface S1, another capacitor may further be disposed on the second surface S2 side. The capacitor 30 may be omitted.
The interlayer insulating film 40 covers the first surface S1 and has embedded therein the first conductor layer 20, the dielectric layer 31, and the upper electrode 32. The interlayer insulating film 40 has through-holes at positions of the lands included in the first conductor layer 20 and at the position of the upper electrode 32. According to an example, the interlayer insulating film 40 comprises an insulating resin layer.
The conductor layer 50 comprises conductor patterns provided on the interlayer insulating film 40. The conductor patterns each include a pad provided on the major surface of the interlayer insulating film 40, and a via covering the side walls of the corresponding through-hole provided in the interlayer insulating film 40. The pad serves as an external connection terminal. Each via connects the corresponding land included in the first conductor layer 20 or the upper electrode 32 to the corresponding pad.
The conductor layer 50 includes a seed layer 53 and a copper layer 54. The seed layer 53 and the copper layer 54 are laminated in this order on the interlayer insulating film 40. The conductor layer 50 can further include an adhesion layer between the interlayer insulating film 40 and the seed layer 53. The adhesion layer included in the conductor layer 50 and the seed layer 53 can be made of the materials exemplified respectively for the adhesion layer 72 and the seed layer 73 described later. The seed layer 53 may be omitted.
The insulating layer 60 at least partially covers the interlayer insulating film 40 and has embedded therein the conductor layer 50. The insulating layer 60 is provided with through-holes at positions of the pads included in the conductor layer 50. For example, the insulating layer 60 may be made of a solder resist.
The second conductor layer 70 comprises conductor patterns each including a portion covering the second surface S2 of the glass substrate 10, a portion covering the side walls of the first through-hole provided in the glass substrate 10, and a portion covering the inner surface of the recess provided in the first conductor layer 20. The conductor patterns each include a land, a wiring portion, and a via. The portions of the second conductor layer 70 covering the second surface S2 are portions of a second wiring layer respectively including lands and wiring portions. The vias each include a portion of the second conductor layer 70 covering the side walls of the corresponding one of the first through-holes provided in the glass substrate 10, and a portion thereof covering the inner surface of the corresponding one of the recesses provided in the first conductor layer 20.
The second conductor layer 70 has a multilayer structure. Specifically, as shown in
The adhesion layer 72 covers the side walls of the first through-holes provided in the glass substrate 10, the inner surfaces of the recesses provided in the first conductor layer 20, and the regions of the second surface S2 surrounding the openings of the first through-holes on the second surface S2 side. The adhesion layer 72 is conformal to these surfaces.
The adhesion layer 72 enhances adhesion of the seed layer 73 to the glass substrate 10. The adhesion layer 72 is preferred to be made of one or more materials selected from the group consisting of titanium, chromium, and nickel, or oxides thereof, and are more preferred to be made of titanium or a titanium oxide. The adhesion layer 72 has a thickness T1 which is preferred to be in the range of 10 nm to 0.5 μm, and is more preferred to be in the range of 20 nm to 0.08 μm. The thickness T1 of the adhesion layer 72 is a thickness of the adhesion layer 72 at a portion on the second surface S2.
In order to increase a sum T1+T2 of the thickness T1 of the adhesion layer 72 and a thickness T2 of the seed layer 73, it is advantageous to increase the thickness T1. However, if the thickness T1 is too large, the connection resistance between the first and second conductor layers 20 and 70 increases.
The seed layer 73 is provided on the adhesion layer 72. The seed layer 73 is conformal to the adhesion layer 72. The seed layer 73 functions as a power supply layer for electrolytic plating. For example, the seed layer 73 may be made of copper. The thickness T2 of the seed layer 73 is preferred to be in the range of 100 nm to 0.5 μm, and is more preferred to be in the range of 200 nm to 0.4 μm. The thickness T2 of the seed layer 73 is a thickness of the seed layer 73 at a portion on the second surface S2.
Considering the function as a power supply layer, the seed layer 73 is preferred to be thick. However, if the thickness T2 is increased, in the case of forming the second conductor layer 70 using a semi-additive method, the surface regions of the second copper layer 74 may be removed during removal of the unnecessary portions of the seed layer 73, etc., which are formed as continuous films, by full-surface etching. Therefore, if the thickness T2 is increased, the shape accuracy or dimensional accuracy of the wiring included in the second conductor layer 70 may be reduced.
The second copper layer 74 is provided on the seed layer 73. The second copper layer 74 is conformal to the seed layer 73. For example, the second copper layer 74 may have a thickness in the range of 2 μm to 10 μm.
The sum T1+T2 of the thickness T1 of the adhesion layer 72 and the thickness T2 of the seed layer 73 is equal to or greater than the thickness T3 of the hydrofluoric acid resistant metal layer 21. That is, the thicknesses T1 to T3 satisfy the relationship shown in the following Inequality (1).
T3≤T1+T2 (1)
The sum T1+T2 is preferred to be greater than the thickness T3, more preferred to be twice or more the thickness T3, and even more preferred to be six times or more the thickness T3. The thicknesses T2 and T3 may satisfy the relationship shown in the following Inequality (2).
T3≤T1 (2)
As described later, if the thicknesses T1 to T3 satisfy the above relationship, the seed layer 73 is less likely to produce a discontinuity due to an undercut between the bottom surface of each recess provided in the first conductor layer 20 and the side walls of the corresponding first through-hole. Therefore, in the electrolytic plating for forming the second copper layer 74, the deposition of copper in the recesses provided in the first conductor layer 20 is less likely to be insufficient.
The sum T1+T2 is preferred to be 20 times or less than the thickness T3, and more preferred to be 8 times or less than the thickness T3. In the case of forming the second conductor layer 70 using a semi-additive method, the unnecessary portions of the adhesion layer 72, the seed layer 73, etc., which are formed as continuous films, are removed by full-surface etching. If the sum T1+T2 is increased, the time required for removing these unnecessary portions will become longer.
The thickness T2 is preferred to be greater than or equal to a sum T1+T3 of the thicknesses T1 and T3. That is, the thicknesses T1 to T3 are preferred to satisfy the relationship shown in the following Inequality (3).
T1+T3≤T2 (3)
If the thicknesses T1 to T3 satisfy the above relationship, the seed layer 73 is thicker than the hydrofluoric acid resistant metal layer 21 and the adhesion layer 72. If such a configuration is adopted, the seed layer 73 can exhibit particularly excellent performance as a power supply layer during electrolytic plating for forming the second copper layer 74.
The interlayer insulating film 80 covers the second surface S2 and has embedded therein the second conductor layer 70. The interlayer insulating film 80 has through-holes at positions of the lands included in the second conductor layer 70. According to an example, the interlayer insulating film 80 comprises an insulating resin layer.
The conductor layer 90 comprises conductor patterns provided on the interlayer insulating film 80. The conductor patterns each include a pad provided on the major surface of the interlayer insulating film 80, and a via covering the side walls of the corresponding through-hole provided in the interlayer insulating film 80. The pad serves as an external connection terminal. Each via connects the corresponding land included in the second conductor layer 70 to the corresponding one of the pads.
The conductor layer 90 includes a seed layer 93 and a copper layer 94. The seed layer 93 and the copper layer 94 are laminated in this order on the interlayer insulating film 80. The conductor layer 90 can further include an adhesion layer between the interlayer insulating film 80 and the seed layer 93. The adhesion layer included in the conductor layer 90 and the seed layer 93 can be made of the materials exemplified respectively for the adhesion layer 72 and the seed layer 73. The seed layer 93 may be omitted.
The insulating layer 100 at least partially covers the interlayer insulating film 80 and has embedded therein the conductor layer 90. The insulating layer 100 is provided with through-holes at positions of the pads included in the conductor layer 90. For example, the insulating layer 100 may be made of a solder resist.
For example, the wiring board 1 can be produced using the following method.
In this method, first, a glass substrate 10 having a first surface S1 and a second surface S2 which is the rear of the first surface S1 is prepared. For example, contaminants are removed from the surface of a non-alkali glass plate having a thickness of 500 μm by ultrasonic cleaning or the like to obtain a glass substrate 10. The glass substrate 10 at this stage is thicker than the glass substrate 10 included in the wiring board 1. The glass substrate 10 at this stage is a large-sized glass substrate having a larger dimension in the direction perpendicular to the thickness direction, compared to the glass substrate 10 included in a packaged device described later.
Next, the glass substrate 10 is irradiated with a laser beam from the first surface S1 to the second surface S2 to form one or more modified portions 11 in the glass substrate 10 as shown in
The laser beam used in this example has a wavelength of 535 nm or less. The wavelength of the laser beam is preferred to be 355 nm or more and 535 nm or less. If the wavelength of the laser beam is less than 355 nm, sufficient laser output is less likely to be attained, and therefore it may be difficult to attain laser modification in a stable manner. However, if the wavelength of the laser beam is greater than 535 nm, the irradiation spots may become larger, and it may be difficult to form laser modification in smaller areas. Furthermore, due to the influence of heat, microcracks may occur, and the glass substrate 10 may become fragile.
In the case of using a pulsed laser, the laser pulse width is preferred to be in the range of picoseconds to femtoseconds. If the laser pulse width is longer than nanoseconds, it may become difficult to control the amount of energy per pulse, microcracks may occur, and the glass substrate 10 may become fragile.
The energy value of the laser pulses is preferred to be selected according to the type of laser modification to be caused, and is preferred to be in the range of 5 μJ or more and 150 μJ or less. By increasing the laser pulse energy, the length of the modified portions 11 can be increased in proportion to the increase in the laser pulse energy.
Next, a first conductor layer 20 including a first copper layer 24 facing the first surface S1, and a hydrofluoric acid resistant metal layer 21 interposed between the first copper layer 24 and the glass substrate 10 is formed on the first surface S1 to cover the modified portions 11.
For example, as shown in
Next, a mask pattern formed of an insulator is formed on the seed layer 23 so as to have openings at positions corresponding to parts of the first copper layer 24. For example, the mask pattern may be formed by providing a photoresist layer on the seed layer 23 and performing pattern exposure and development of the photoresist layer. According to an example, RD1225 that is a dry photoresist manufactured by Showa Denko Materials Co., Ltd. is laminated on the seed layer 23 and the dry photoresist is pattern-exposed and developed sequentially to obtain a mask pattern made of a resin.
Subsequently, electrolytic copper plating is performed using the seed layer 23 as a power supply layer. Thus, copper is deposited on the seed layer 23 at positions of the openings of the mask pattern to obtain a first copper layer 24 shown in
After that, the mask pattern is removed. For example, the dry film resist may be dissolved and peeled off. Next, the entire surface of the composite including the first copper layer 24 and the glass substrate 10 is etched on the first copper layer 24 side until the exposed portions of the seed layer 23 are removed. If an adhesion layer 22 is provided between the seed layer 23 and the hydrofluoric acid resistant metal layer 21, the entire surface of the composite on the first copper layer 24 side is further etched until the portions of the adhesion layer 22 that have been exposed by removing the exposed portions of the seed layer 23 are also removed.
In this way, the first conductor layer 20 shown in
Next, a dielectric layer 31 and an upper electrode 32 are formed in this order on the lower electrode included in the first conductor layer 20 to obtain a capacitor 30 shown in
Next, an insulating resin layer is provided to the surface of the composite including the capacitor 30 and the glass substrate 10 on the capacitor 30 side. According to an example, ABF-GXT31 (thickness: 32.5 μm) that is an insulating resin film manufactured by Ajinomoto Fine-Techno Co., Inc. is laminated on the surface mentioned above and pre-cured. Next, blind vias are formed in the insulating resin layer by laser processing. After that, residues produced due to the laser processing are removed by performing desmearing. In this way, the interlayer insulating film 40 shown in
Next, a seed layer 53 is formed by sputtering or electroless plating. In this example, the seed layer 53 is formed to cover the upper surface of the interlayer insulating film 40, the side walls of the through-holes provided to the film, and portions of the first conductor layer 20 and the upper electrode 32 exposed at positions of the through-holes.
Next, a mask pattern formed of an insulator is formed on the seed layer 53 so as to have openings at positions corresponding to parts of the copper layer 54. For example, the mask pattern may be formed by providing a photoresist layer on the seed layer 53 and performing pattern exposure and development of the photoresist layer. According to an example, RD1225 that is a dry film resist manufactured by Showa Denko Materials Co., Ltd. is laminated on the seed layer 53 and the dry film resist is pattern-exposed and developed sequentially to obtain a mask pattern made of a resin.
Subsequently, electrolytic plating is performed using the seed layer 53 as a power supply layer. Thus, copper is deposited on the seed layer 53 at positions of the openings of the mask pattern to obtain a copper layer 54 shown in
After that, the mask pattern is removed. For example, the dry film resist may be dissolved and peeled off. Next, the entire surface of the composite including the copper layer 54 and the glass substrate 10 is etched on the copper layer 54 side until the exposed portions of the seed layer 53 are removed. In this way, a conductor layer 50 is obtained.
Next, an insulating layer 60 shown in
Next, as shown in
For example, REVALPHA (trademark) manufactured by Nitto Denko Corporation may be used as the adhesive 142. For example, a thin glass carrier may be used as the second support 141. The second support 141 does not have to be made of glass but may be made of a metal or resin.
The second support 141 is preferred to have a thickness in the range of 0.7 mm or more and 10 mm or less from the perspective of transferability of the glass substrate 10 after being thinned. The thickness of the second support 141 may be appropriately determined according to the thickness of the glass substrate 10.
Next, the second surface S2 of the composite supported by the second support 141 is etched with an etching solution containing hydrogen fluoride to form recesses in the second surface S2 and form first through-holes 12 at positions of the modified portions 11, as shown in
In the etching, the hydrofluoric acid resistant metal layer 21 functions as an etching stopper film. In
The amount of etching of the glass substrate 10 may be appropriately determined according to the thickness of the wiring board 1. For example, if the thickness of the glass substrate 10 before etching is 400 μm, the amount of etching is preferred to be in the range of 100 μm or more and 350 μm or less. The thickness of the glass substrate 10 after thinning is preferred to be in the range of 50 μm or more and 300 μm or less.
For example, the etching solution containing hydrogen fluoride may be an aqueous solution of hydrogen fluoride. The etching solution can further contain one or more inorganic acids selected from the group consisting of nitric acid, hydrochloric acid, and sulfuric acid.
For example, the hydrogen fluoride concentration of the etching solution may be in the range of 1.0 mass % or more and 6.0 mass % or less, or is more preferred to be in the range of 2.0 mass % or more and 5.0 mass % or less. For example, the inorganic acid concentration is preferred to be in the range of 1.0 mass % or more and 20.0 mass % or less, or is more preferred to be in the range of 3.0 mass % or more and 16.0 mass % or less. It is desirable to perform etching at an etching rate of 1.0 μm/min or less using an etching solution in which the concentrations of the components are set within the above ranges. During the etching, it is desirable that the etching solution has a temperature in the range of 10° C. or more and 40° C. or less.
Next, portions of the hydrofluoric acid resistant metal layer 21 exposed in the individual first through-holes 12 are subjected to wet etching to form recesses, as shown in
Any etching solution may be used for this wet etching as long as the exposed portions of the hydrofluoric acid resistant metal layer 21 can be removed. As the etching solution, a chromium etching solution is favorably used.
According to an example, an alkaline chromium etching solution manufactured by Nihon Kagaku Sangyo Co., Ltd. containing potassium ferricyanide and potassium hydroxide is used as the above etching solution. Using this etching solution, wet etching is performed at a temperature of 40° C. for 1.5 minutes. According to such wet etching, only the exposed portions of the hydrofluoric acid resistant metal layer 21 can be removed without damaging other members, e.g., the glass substrate 10, first copper layer 24, and interlayer insulating film 40, than the hydrofluoric acid resistant metal layer 21.
As described above, the first through-holes 12 each have a frustoconical shape with a radius (or cross section) on the second surface S2 side larger than a radius (or cross section) on the first surface S1 side. Such a shape promotes circulation of the etching solution between the inside and outside of the first through-holes 12, enabling efficient etching.
Prior to the wet etching, for example, it is preferred to perform plasma treatment using CF4 gas, oxygen gas, argon gas, or hydrogen gas, or perform ultrasonic cleaning to improve wettability of the hydrofluoric acid resistant metal layer 21 to the etching solution at the exposed portions. It is more preferred to perform both the plasma treatment and ultrasonic cleaning. In this case, the effect of improving wettability is further enhanced.
After that, the adhesion layer 72 shown in
Next, a seed layer 73 shown in
The adhesion layer 73 and the seed layer 72 are formed such that the thickness T1 of the adhesion layer 72, the thickness T2 of the seed layer 73, and the thickness T3 of the hydrofluoric acid resistant metal layer satisfy the relationships described above.
Next, as shown in
For example, first, a mask pattern formed of an insulator is formed on the seed layer 73 so as to have openings at positions corresponding to parts of the second copper layer 74. For example, the mask pattern may be formed by providing a photoresist layer on the seed layer 73 and performing pattern exposure and development of the photoresist layer. According to an example, RD1225 that is a dry photoresist manufactured by Showa Denko Materials Co., Ltd. is laminated on the seed layer 73 and the dry photoresist is pattern-exposed and developed sequentially to obtain a mask pattern made of a resin.
Subsequently, electrolytic copper plating is performed using the seed layer 73 as a power supply layer. Thus, copper is deposited on the seed layer 73 at positions of the openings of the mask pattern to obtain the second copper layer 74 shown in
After that, the mask pattern is removed. For example, the dry film resist may be dissolved and peeled off. Next, the entire surface of the composite including the second copper layer 74 and the glass substrate 10 is etched on the second copper layer 74 side until the exposed portions of the seed layer 73 are removed. Subsequently, the entire surface of the composite on the second copper layer 74 side is further etched until the portions of the adhesion layer 72 that have been exposed by removing the exposed portions of the seed layer 73 are removed.
In this way, the second conductor layer 70 shown in
Next, the surface of the composite including the second conductor layer 70 and the glass substrate 10 on the second conductor layer 70 side is subjected to a treatment as in the fifth process to provide the interlayer insulating film 80, the conductor layer 90, and the insulating layer 100 shown in
After that, the second support 141 and the adhesive 142 are removed from the composite including the glass substrate 10, the first conductor layer 20, the second conductor layer 70, etc. In this way, the wiring board 1 shown in
The wiring board 1 described above can be used for producing packaged devices.
The wiring board 1 is obtained by dividing the wiring board described referring to
The bonding conductors 4 and 5 are solder balls in this example. The bonding conductors 4 are provided on the respective pads included in the conductor layer 50. The bonding conductors 4 bond the functional device 2 to the wiring board 1. The bonding conductors 5 are provided on the respective pads included in the conductor layer 90. The bonding conductors 5 can bond the packaged device to another wiring board, e.g., mother board.
As described above, the functional device 2 is a device activated with a supply of electrical power and/or electrical signals, a device outputting electrical power and/or electrical signals due to external stimulation, or a device activated with a supply of electrical power and/or electrical signals and outputting electrical power and/or electrical signals due to external stimulation. The functional device 2 may be, for example, in the form of a chip, such as a semiconductor chip or a chip in which circuits or elements are formed on a substrate, such as a glass substrate, made of a material other than semiconductor materials. For example, the functional device 2 can include one or more from among LSIs, memories, imaging elements, light-emitting elements, and MEMSs. The MEMSs may be, for example, one or more from among pressure sensors, acceleration sensors, gyro sensors, tilt sensors, microphones, and acoustic sensors. According to an example, functional devices may be semiconductor chips including LSIs.
The functional device 2 is mounted on the wiring board 1. In this example, the functional device 2 is mounted on the wiring board 1 using flip chip bonding. The functional device 2 may be mounted on the wiring board 1 using other surface mounting techniques. The packaged device may include two or more functional devices 2.
The chip component 3 is a passive component on which chip resistors, chip capacitors, chip inductors, etc. can be surface-mounted. The chip component 3 is mounted on the wiring board 1. In this example, the chip component 3 is mounted on the wiring board 1 using die bonding and wire bonding. The chip component 3 may be mounted on the wiring board 1 using other surface mounting techniques. The packaged device may include two or more chip components 3. The chip component 3 may be omitted. In this example, the chip component 3 is a chip inductor and constitutes an LC filter together with the capacitor 30.
For example, the technique described above provides the following effects.
According to the production method described above, the glass substrate 10 is less likely to suffer damage, and can achieve good handleability. This will be described below.
Forming through-holes in glass substrates may deteriorate the physical strength of the glass substrates. Also, glass substrates with a small thickness, e.g., glass substrates with a thickness of 300 μm or less, easily undergo cracking during transfer for forming conductors such as circuits, and thus are difficult to handle.
In the method described above, the glass substrate 10 is relatively thick during formation of the first conductor layer 20 and the like on the first surface S1 and thus is less likely to be broken. In addition, the composite including the glass substrate 10 and the first conductor 20 has high strength even after the thinning of the glass substrate 10 and formation of the first through-holes 12. Therefore, the glass substrate 10 is less likely to be damaged in the processes that follow. Furthermore, the second support 141 contributes to further reduce breakage of the glass substrate 10. Also, since the strength of the composite is enhanced by forming the second conductor layer 70, etc. before removal of the second support 141, the glass substrate 10 is less likely to be damaged even after removal of the second support 141 from the composite. Thus, according to the production method described above, the glass substrate 10 is less likely to be damaged and can be easily handled.
According to the production method described above, high productivity can be achieved as described below.
In the TSV technique, methods such as the Bosch process, in which dry etching is used, have been established as methods of forming through-holes in silicon substrates. However, forming through-holes in a glass substrate by dry etching takes a long time and may not be practical.
In the production method described above, wet etching which is used for thinning the glass substrate 10 is also used for forming the first through-holes 12. The first through-holes 12 are formed at positions of the modified portions 11 produced by laser irradiation. The modified portions 11 of the glass substrate 10 have a higher etching rate compared to other portions. Accordingly, according to the production method described above, high productivity can be achieved.
The wiring board 1 obtained through the method described above has good electrical characteristics at connecting portions between the wiring layer provided on the glass substrate 10 and the TGVs provided in the glass substrate.
The method described referring to
In the eighth process, following the seventh process of the method described above, portions of the hydrofluoric acid resistant metal layer 21 exposed at positions of the first through-holes 12 are removed by wet etching. Wet etching, which is isotropic etching, can also remove portions of the hydrofluoric acid resistant metal layer 21 directly below the etching residues 10ER by side etching. Therefore, this etching can also remove the etching residues 10ER. In general, materials used for the hydrofluoric acid resistant metal layer 21 have electrical resistance greater than that of copper, etc. Therefore, removing portions of the hydrofluoric acid resistant metal layer 21 exposed at positions of the first through-holes 12 can reduce connection resistance between the first and second conductor layers 20 and 70.
In the method described above, portions of the hydrofluoric acid resistant metal layer 21 exposed at positions of the first through-holes 12 are removed by wet etching which is isotropic etching. Therefore, as shown in
Accordingly, the wiring board 1 obtained through the method described above has good electrical characteristics at connecting portions between the wiring layer provided on the glass substrate 10 and the TGVs provided in the glass substrate.
The wiring board 1 obtained through the method described above has high connection reliability between the wiring layer provided on the glass substrate 10 and the TGVs provided in the glass substrate.
The etching residues 10ER shown
In the wiring board 1, stress is concentrated at the connecting portions between the first and second conductor layers 20 and 70. Therefore, connection reliability is greatly affected by disconnection occurring at these connecting portions.
In the wiring board 1, the hydrofluoric acid resistant metal layer 21 includes undercuts and the second conductor layer 70 at least has partially embedded therein the undercuts. If stresses are applied to portions of the composite layer composed of the seed layer 73 and the second copper layer 74 located in the first through-holes 12 in the direction of separating these portions from the first conductor layer 20, the portions of the second conductor layer 70 having embedded therein the undercuts can make it difficult for the portions located in the first through-holes 12 to move.
Accordingly, the wiring board 1 obtained through the method described above has high connection reliability between the wiring layer provided on the glass substrate 10 and the TGVs provided in the glass substrate.
Furthermore, according to the method described above, disconnection can be made less likely to occur between the wiring layer provided on the glass substrate 10 and the TGVs provided in the glass substrate, and therefore a high yield can be achieved. This will be described below.
As described above, as shown in
If the seed layer 73 has such discontinuities, power cannot be supplied to the portions of the seed layer 73 surrounded by the annular discontinuities during the electrolytic copper plating performed in the tenth process. As a result of this, voids can be produced in the portions between the second copper layer 74 and portions of the seed layer 73 surrounded by the annular discontinuities, at positions of the recesses formed in the first conductor layer 20. That is, disconnection may occur between the wiring layer provided on the glass substrate 10 and the TGVs provided in the glass substrate.
In the method described referring to
In this method, the thickness T1 is preferred to be made greater than or equal to the thickness T3. If the adhesion layer 72 is formed to satisfy this relationship, the occurrence of the discontinuities in the seed layer 73 can be more reliably prevented.
In this method, the thickness T2 is preferred to be made greater than or equal to the sum T1+T3 of the thicknesses T1 and T3. If power supply to the portions of the seed layer 73 at positions in the first through-holes 12 is insufficient when performing electrolytic plating for forming the second copper layer 74, deposition of copper in the first through-holes 12 may become insufficient, due to which, there is a risk of causing disconnection between the wiring layer provided on the glass substrate 10 and the TGVs provided in the glass substrate. If the adhesion layer 72 and seed layer 73 are formed to satisfy the above relationship, disconnection due to insufficient power supply can be made less likely to occur.
Various modifications can be made to the wiring board 1 and the packaged device described above.
In the wiring board 1 described above, the through-holes 12 provided in the glass substrate 10 are tapered from the second surface S2 toward the first surface S1. That is, the first through-holes 12 are forward tapered. As shown in
In this example, the forward tapered portion extends from the second surface S2 toward the first surface S1 while being reduced in diameter from the second surface S2 toward the first surface S1. Also, the reverse tapered portion extends from the first surface S1 toward the second surface S2 while being increased in diameter from the first surface S1 toward the second surface S2.
In the structure shown in
In each of the structures shown in
The packaged device described above includes an inductor as the chip component 3. As described above, an LC filter can be constituted by combining an inductor with a capacitor 30.
The inductor may be incorporated in the wiring board 1. If the inductor is incorporated in the wiring board 1, the wiring length can be reduced, for example, leading to improvement in electrical characteristics and transmission characteristics, or size reduction or height reduction of the packaged device.
For example, the inductor incorporated in the wiring board 1 may be a helical coil. The wiring board 1 may include a portion of the first conductor layer 20 as a helical coil or may include a portion of the second conductor layer 70 as a helical coil. Alternatively, the wiring board 1 may include a portion of the first conductor layer 20 as a helical coil and may include a portion of the second conductor layer 70 as another helical coil.
The wiring board 1 may incorporate a solenoid coil described below as the inductor.
The solenoid coil 110 is constituted of part of the first conductor layer 20 and part of the second conductor layer 70. Specifically, the solenoid coil 110 includes first conductor paths 20A, second conductor paths 70A, and third conductor paths 70B.
The first conductor paths 20A are parts of the first conductor layer 20. The first conductor paths 20A each have a shape extending in a first direction parallel to the first surface S1, and are arranged at a regular pitch in a second direction parallel to the first surface S1 and intersecting the first direction. Each of the first conductor paths 20A includes a first end and a second end. The first through-holes 12 are provided in the glass substrate 10 at positions of the first ends and the second ends.
The second conductor paths 70A are parts of the second conductor layer 70 in portions located on the second surface S2. The second conductor paths 70A each have a shape parallel to the second surface S2 and extending in a third direction intersecting the first and second directions and are arranged at a regular pitch in the second direction. Each second conductor path 70A has a third end facing the first end of a first conductor path 20A, and a fourth end facing the second end of the first conductor path 20A adjacent to the previous first conductor path 20A.
The third conductor paths 70B are parts of the second conductor layer 70 in portions located in the first through-holes 12. The third conductor paths 70B connect the third and fourth ends of second conductor paths 70A to the first end of a first conductor path 20A and the second end of the first conductor path 20A adjacent to the previous first conductor path 20A.
The solenoid coil 110 has a structure in which a plurality of segments are connected in series, each segment including a first conductor path 20A, a third conductor path 70B, a second conductor path 70A, and a third conductor path 70B in this order. The helical axis of the solenoid coil 110 is parallel to the second direction. The solenoid coil 110 constitutes an LC filter in combination with the capacitor 30.
As described above, in the structure described referring to
In contrast, in the solenoid coil 110 described above, the connecting portions between the first conductor paths 20A and the third conductor paths 70B each have the structure described referring to
The solenoid coil 110 is constituted of part of the first conductor layer 20 and part of the second conductor layer 70. A solenoid coil having a similar structure can be constituted of part of the first conductor layer 20 and part of the conductor layer 50, and also can be constituted of part of the second conductor layer 70 and part of the conductor layer 90.
In the method described referring to
In the structure shown in
In contrast, in the structure shown in
In the structure shown in
In the vias, the copper layer may adopt either of the conformal form and the filled form. If the filled form is adopted, electrical characteristics or transmission characteristics can be improved at connecting portions between the wiring layer provided on the glass substrate 10 and the TGVs provided in the glass substrate, compared to the case of adopting the conformal form.
In the structure shown in
If the etching residues 10ER described referring to
If the portions of the hydrofluoric acid resistant metal layer 21 corresponding to the respective first through-holes 12 are not completely removed, portions of the hydrofluoric acid resistant metal layer 21 remaining at the respective first through-holes 12 may deteriorate the electrical characteristics or transmission characteristics mentioned above. From the perspective of electrical characteristics or transmission characteristics, the average depth D is preferred to be 70% or more of the thickness T3.
If etching is ended before producing through-holes in the hydrofluoric acid resistant metal layer 21, time required for the etching can be shortened. Considering this effect, the average depth D is preferred to be 90% or less of the depth T3.
Still other modifications can be made to the wiring board 1 and the packaged device described above.
For example, the wiring board 1 shown in
Similarly, the wiring board 1 shown in
A second embodiment of the present invention is similar to the first embodiment except that the wiring board is produced through the following method.
As described below, the production method according to the second embodiment is similar to the production method described referring to
In this method, first, a glass substrate 10 having a first surface S1 and a second surface S2 which is the rear of the first surface S1 is prepared. The glass substrate 10 is preferred to have a smaller thickness than that of the substrate used in the first process. For example, contaminants are removed from the surface of a non-alkali glass plate having a thickness of 130 μm by ultrasonic cleaning or the like to obtain a glass substrate 10. The glass substrate 10 at this stage is a large-sized glass substrate having a larger dimension in the direction perpendicular to the thickness direction, compared to the glass substrate 10 included in a packaged device.
Next, as shown in
Next, the glass substrate 10 is irradiated with a laser beam from the first surface S1 to the second surface S2 to form one or more modified portions 11 in the glass substrate 10 as shown in
Next, third to sixth processes are sequentially performed for the glass substrate 10 supported by the first support 151. Thus, the structure shown in
After that, the first support 151 and the adhesive 152 are removed from the composite including the glass substrate 10, the first conductor layer 20, the second support 141, etc.
Furthermore, seventh to twelfth processes are sequentially performed for the composite including the glass substrate 10, the first conductor layer 20, etc. Thus, the wiring board 1 shown in
The second embodiment has effects similar to those of the first embodiment.
In the second embodiment, the modified portions 11 are formed so as to extend from the first surface S1 and reach the second surface S2. Therefore, the modified portions 11 are not varied in length in the glass substrate 10. In this way, according to the second embodiment, variation in diameter of the first through-holes 12 can be easily reduced compared to the first embodiment and higher processing accuracy can be achieved.
For example, modifications similar to those described in the first embodiment can be made to the above production method, the wiring board obtained from the production method, and the packaged device including the wiring board.
A third embodiment of the present invention is similar to the first embodiment except that the wiring board is produced through the following method.
As described below, the production method according to the third embodiment is similar to the production method described referring to
First, the first process is performed, followed by the third process without performing the second process. In the third process, first, the structure shown in
Next, the glass substrate 10 is irradiated with a laser beam from the second surface S2 to the first surface S1 to form one or more modified portions 11 in the glass substrate 10 as shown in
Furthermore, seventh to twelfth processes are sequentially performed for the composite including the glass substrate 10, the first conductor layer 20, etc. Thus, the wiring board 1 shown in
The third embodiment has effects similar to those of the first embodiment.
For example, modifications similar to those described in the first embodiment can be made to the above production method, the wiring board obtained from the production method, and the packaged device including the wiring board.
A fourth embodiment of the present invention is similar to the first embodiment except that the wiring board is produced through the following method.
As described below, the production method according to the fourth embodiment is similar to the production method described referring to
First, the thirteenth process is performed instead of the first process, followed by the third process without performing the second process. In the third process, first, the structure shown in
Next, the glass substrate 10 is irradiated with a laser beam from the second surface S2 to the first surface S1 to form one or more modified portions 11 in the glass substrate 10 as shown in
Next, by performing the fifteenth process, the first support 151 and the adhesive 152 are removed from the composite including the glass substrate 10, the first conductor layer 20, the second support 141, etc. After that, the seventh to twelfth processes are sequentially performed for the composite including the glass substrate 10, the first conductor layer 20, etc. Thus, the wiring board 1 shown in
The fourth embodiment has effects similar to those of the first and second embodiments.
For example, modifications similar to those described in the first embodiment can be made to the above production method, the wiring board obtained from the production method, and the packaged device including the wiring board.
Hereinafter, tests performed in connection with the present invention will be described.
For each of the structures of
In Table 1, etching ratio represents ratio of the average depth D to the thickness T3. That is, the structure where the etching ratio is 100% is the structure shown in
As shown in Table 1, regardless of the length of the through-electrodes, resistance reduction effect increased with the increase of the etching ratio. Also, the shorter the length of the through-electrodes, the higher the resistance reduction effect accompanying the increase in etching ratio.
For the wiring boards each having a structure similar to the wiring board 1 shown in
In Table 2, Q-value increase ratio represents increase ratio of Q-value to Q-value in the case of the etching ratio being 0%. Also, S21-value reduction ratio represents reduction ratio of S21 value to S21 value in the case of the etching ratio being 0%.
As shown in Table 2, the more the etching ratio was increased, the more the Q-values of the capacitor 30 and the solenoid coil 110 increased, and thus the effect of increasing the Q-values accompanying the increase in etching ratio was higher as the etching ratio was increased. Also, the S21-values of the LC filters decreased as the etching ratio was increased, and thus the effect of improving filter characteristics accompanying the increase in etching ratio was higher as the etching ratio was increased.
50 wiring boards 1 described referring to
50 wiring boards similar to the above were prepared except that each of them adopted the structure shown in
50 wiring boards similar to the above were prepared except that each of them adopted the structure shown in
Consequently, it was revealed that the wiring boards adopting the structure shown in
50 wiring boards 1 described referring to
50 wiring boards 1 were prepared as in Example 1 except that the thickness T3 was changed to 100 nm. For each of these wiring boards 1 also, electrical continuity between the wiring layer provided on the glass substrate 10 and the through-electrodes was determined in a manner similar to Example 1.
50 wiring boards 1 were prepared as in Example 1 except that the thickness T2 was changed to 100 nm and the thickness T3 was changed to 50 nm. For each of these wiring boards 1 also, electrical continuity between the wiring layer provided on the glass substrate 10 and the through-electrodes was determined in a manner similar to Example 1.
50 wiring boards 1 were prepared as in Example 1 except that the thickness T2 was changed to 100 nm and the thickness T3 was changed to 100 nm. For each of these wiring boards 1 also, electrical continuity between the wiring layer provided on the glass substrate 10 and the through-electrodes was determined in a manner similar to Example 1.
50 wiring boards were prepared as in Example 1 except that the thickness T2 was changed to 100 nm and the thickness T3 was changed to 200 nm. For each of these wiring boards also, electrical continuity between the wiring layer provided on the glass substrate 10 and the through-electrodes was determined in a manner similar to Example 1.
Table 3 below shows the results.
In Table 3, Y represents that the relationships shown in the inequalities are satisfied, and N represents that the relationships shown in the inequalities are not satisfied. Pass rate represents a rate of the number of wiring boards caused no conduction failures, relative to the total number (50) of the wiring boards.
As shown in Table 3, much higher pass rate could be achieved in the case of the sum T1+T2 of the thicknesses T1 and T2 being greater than or equal to the thickness T3, than in the case of the sum T1+T2 being smaller than the thickness T3. In addition, a pass rate of 100% could be achieved in the case of the thickness T2 being greater than the sum T1+T3 of the thicknesses T1 and T3.
[Reference Signs List] 1 . . . Wiring board; 2 . . . Functional device; 3 . . . Chip component; 4 . . . Bonding conductor; 5 . . . Bonding conductor; 10 . . . Glass substrate; 10ER . . . Etching residues; 11 . . . Modified portion; 12 . . . First through-hole; 20 . . . First conductor layer; 20A . . . First conductor path; 21 . . . Hydrofluoric acid resistant metal layer; 22 . . . Adhesion layer; 23 . . . . Seed layer; 24 . . . First copper layer; 30 . . . Capacitor; 31 . . . Dielectric layer; 32 . . . Upper electrode; 40 . . . Interlayer insulating film; 50 . . . Conductor layer; 53 . . . Seed layer; 54 . . . Copper layer; 60 . . . . Insulating layer; 70 . . . Second conductor layer; 70A . . . Second conductor path; 70B . . . Third conductor path; 72 . . . Adhesion layer; 73 . . . Seed layer; 74 . . . Second copper layer; 80 . . . Interlayer insulating film; 90 . . . Conductor layer; 93 . . . Seed layer; 94 . . . Copper layer; 100 . . . Insulating layer; 110 . . . Solenoid coil; 141 . . . Second support; 142 . . . Adhesive; 151 . . . First support; 152 . . . . Adhesive; S1 . . . First surface; S2 . . . Second surface; UC . . . Undercut.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2022-151675 | Sep 2022 | JP | national |
This application is a continuation application filed under 35 U.S.C. § 111 (a) claiming the benefit under 35 U.S.C. §§ 120 and 365 (c) of International Patent Application No. PCT/JP2023/029603, filed on Aug. 16, 2023, which is based upon and claims the benefit to Japanese Patent Application No. 2022-151675, filed on Sep. 22, 2022; the disclosures of all which are incorporated herein by reference in their entirety.
| Number | Date | Country | |
|---|---|---|---|
| Parent | PCT/JP2023/029603 | Aug 2023 | WO |
| Child | 19079947 | US |
