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Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
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PHYSICS
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Computing
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ELECTRICAL DIGITAL DATA PROCESSING
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Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
Sub Industries
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Providing a specific technical effect
G06F2212/1004
Compatibility
G06F2212/1008
Correctness of operation
G06F2212/1012
Design facilitation
G06F2212/1016
Performance improvement
G06F2212/1021
Hit rate improvement
G06F2212/1024
Latency reduction
G06F2212/1028
Power efficiency
G06F2212/1032
Reliability improvement, data loss prevention, degraded operation etc
G06F2212/1036
Life time enhancement
G06F2212/1041
Resource optimization
G06F2212/1044
Space efficiency improvement
G06F2212/1048
Scalability
G06F2212/1052
Security improvement
G06F2212/1056
Simplification
G06F2212/15
Use in a specific computing environment
G06F2212/151
Emulated environment
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Virtualized environment
G06F2212/154
Networked environment
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General purpose computing application
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Portable computer
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Server or database system
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Mainframe system
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Embedded application
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Portable consumer electronics
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Non-portable consumer electronics
G06F2212/1721
Home entertainment system
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Vehicle or other transportation
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Telecommunications system
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Industrial control system
G06F2212/177
Smart card
G06F2212/178
Electronic token or RFID
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Employing a main memory using a specific memory technology
G06F2212/202
Non-volatile memory
G06F2212/2022
Flash memory
G06F2212/2024
Rewritable memory not requiring erasing
G06F2212/2028
Battery-backed RAM
G06F2212/205
Hybrid memory
G06F2212/206
Memory mapped I/O
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Employing a record carrier using a specific recording technology
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Optical disk storage
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with a removable carrier
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Tape storage
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Solid state disk
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using write-once memory
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being detachable, e.g.. USB memory
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Hybrid disk
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Employing cache memory using specific memory technology
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Static RAM
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Non-volatile memory
G06F2212/2228
Battery-backed RAM
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Disk storage
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Hybrid cache memory
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Using a specific main memory architecture
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Local memory within processor subsystem
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being configurable for different purposes
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Centralized memory
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comprising a plurality of modules
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Distributed memory
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Non-uniform memory access [NUMA] architecture
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Using a specific storage system architecture
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Storage comprising a plurality of storage devices
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configured as RAID
G06F2212/263
Network storage
G06F2212/264
Remote server
G06F2212/27
Using a specific cache architecture
G06F2212/271
Non-uniform cache access [NUCA] architecture
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Cache only memory architecture [COMA]
G06F2212/28
Using a specific disk cache architecture
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Single cache
G06F2212/282
Partitioned cache
G06F2212/283
Plural cache memories
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being distributed
G06F2212/285
Redundant cache memory
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Mirrored cache memory
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Providing cache or TLB in specific location of a processing system
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In special purpose processing node
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In image processor or graphics adapter
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In peripheral interface
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In peripheral device
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In main memory subsystem
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being part of a memory device
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being part of a memory device
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In system interconnect
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Providing disk cache in a specific location of a storage system
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In host system
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In storage controller
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In storage device
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In storage network
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Specific encoding of data in memory or cache
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Compressed data
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Encrypted data
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Error protection encoding
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Caching of specific data in cache memory
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Stack data
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Instruction code
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Microcode or microprogram
G06F2212/454
Vector or matrix data
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Image or video data
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Caching storage objects of specific type in disk cache
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Sector or disk block
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Track or segment
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File
G06F2212/464
Multimedia object
G06F2212/465
Structured object
G06F2212/466
Metadata, control data
G06F2212/468
The specific object being partially cached
G06F2212/50
Control mechanisms for virtual memory, cache or TLB
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using adaptive policy
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using speculative control
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Details of cache memory
G06F2212/601
Reconfiguration of cache memory
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of operating mode
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Details relating to cache prefetching
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Using a prefetch buffer or dedicated prefetch cache
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History based prefetching
G06F2212/6026
Prefetching based on access pattern detection
G06F2212/6028
Prefetching based on hints or prefetch instructions
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of operating mode
G06F2212/6032
Way prediction in set-associative cache
G06F2212/604
Details relating to cache allocation
G06F2212/6042
Allocation of cache space to multiple users or processors
G06F2212/6046
Using a specific cache allocation policy other than replacement policy
G06F2212/608
Details relating to cache mapping
G06F2212/6082
Way prediction in set-associative cache
G06F2212/62
Details of cache specific to multiprocessor cache arrangements
G06F2212/621
Coherency control relating to peripheral accessing
G06F2212/622
State-only directory
G06F2212/65
Details of virtual memory and virtual address translation
G06F2212/651
Multi-level translation tables
G06F2212/652
Page size control
G06F2212/653
Page colouring
G06F2212/654
Look-ahead translation
G06F2212/655
Same page detection
G06F2212/656
Address space sharing
G06F2212/657
Virtual address space management
G06F2212/68
Details of translation look-aside buffer [TLB]
G06F2212/681
Multi-level TLB
G06F2212/682
Multiprocessor TLB consistency
G06F2212/683
Invalidation
G06F2212/684
TLB miss handling
G06F2212/69
Details of replacement control
G06F2212/70
Details relating to dynamic memory management
G06F2212/702
Conservative garbage collection
G06F2212/72
Details relating to flash memory management
G06F2212/7201
Logical to physical mapping or translation of blocks or pages
G06F2212/7202
Allocation control and policies
G06F2212/7203
Temporary buffering
G06F2212/7204
Capacity control
G06F2212/7205
Cleaning, compaction, garbage collection, erase control
G06F2212/7206
Reconfiguration of flash memory system
G06F2212/7207
management of metadata or control data
G06F2212/7208
Multiple device management
G06F2212/7209
Validity control
G06F2212/7211
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Issue date
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G06 - COMPUTING CALCULATING COUNTING