Patent Application
20230260999
The present disclosure relates generally to the field of manufacturing transistors.
In the manufacture of semiconductor devices, various fabrication processes are executed, such as film-forming depositions, etch mask creation, patterning, material etching and removal, and doping treatments. These processes may be performed to form semiconductor device components on a substrate. Some example fabrication techniques allow the manufacture of transistors on a single active device plane, while wiring or metallization is formed above the active device plane. Such devices are accordingly characterized as two-dimensional (2D) circuits, manufactured using 2D fabrication techniques. Although scaling efforts have greatly increased the number of transistors per unit area in 2D circuits, these 2D fabrication techniques are approaching physical atomic limitations with single digit nanometer semiconductor device fabrication nodes.
Three-dimensional (3D) integration, e.g., a stacking (or vertical arrangement) of multiple semiconductor devices (e.g., transistor structures), aims to overcome scaling limitations experienced in planar devices by increasing transistor density in volume rather than area.
One aspect of the present disclosure may be directed to a semiconductor device. The semiconductor device includes a transistor structure that may include a structure having a seed layer; a first source/drain extension in contact with the structure; a second source/drain extension in contact with the structure; a two-dimensional (2D) material around at least one of the seed layer, the first source/drain extension, or the second source/drain extension; a first source/drain structure in electrical contact with the 2D material through the first source/drain extension; a second source/drain structure in electrical contact with the 2D material through the second source/drain extension; and a gate structure around at least the 2D material.
The semiconductor device may include a second transistor structure disposed above the transistor structure and comprising: a second structure having a second seed layer; a third source/drain extension in contact with the second structure; a fourth source/drain extension in contact with the second structure; a second 2D material around at least one of the second seed layer, the third source/drain extension, or the fourth source/drain extension; a third source/drain structure in electrical contact with the second 2D material through the third source/drain extension; a fourth source/drain structure in electrical contact with the second 2D material through the fourth source/drain extension; and a second gate structure around at least the second 2D material, wherein the transistor has a first conductive type and the second transistor has a second conductive type, the first conductive type being opposite to the first conductive type.
The first 2D material and the second 2D material each include at least one of: WS2, WSe2, WTe2, MoS2, MoSe2, MoTe2, HfS2, ZrS2, TiS2, GaSe, InSe, or phosphorene.
The first source/drain extension and the second source/drain extension may each include a doped metal material or a doped semiconductor material, and wherein the gate structure is around respective portions of the first source/drain extension and second source/drain extension. The seed layer may be around a semiconductor core. The semiconductor core may include one of: amorphous silicon, crystalline silicon, amorphous germanium, or crystalline germanium.
The first source/drain extension may include a first silicide metal between the first source/drain structure and a first end of the 2D material; and the second source/drain extension may include a second silicide metal between the second source/drain structure and a second end of the 2D material. The structure may comprise a dielectric material.
Another aspect of the present disclosure may be directed to a method for fabricating semiconductor devices. The method may include forming a structure vertically interposed by a first sacrificial dielectric and a second sacrificial dielectric, wherein the structure comprises a dielectric or a semiconductor; forming a source extension and a drain extension in contact with a first end and a second end of the structure, respectively; forming a source structure and a drain structure in electrical contact with the source extension and drain extension, respectively; exposing at least one of the structure, the source extension, or the drain extension at least by removing the first sacrificial dielectric and second sacrificial dielectric; and selectively growing a two-dimensional (2D) material around the structure.
The structure may include amorphous silicon, crystalline silicon, amorphous germanium, or crystalline germanium. Accordingly, the method may further include replacing end portions of the structure with a first silicide metal and a second silicide metal to form the source extension and drain extension, respectively, wherein the first silicide metal is interposed between the source structure and the first end of the structure, and the second silicide metal is interposed between the drain structure and the second end of the structure; and transforming a surface of the structure into a dielectric layer to selectively grow the 2D material on the dielectric layer. The 2D material may electrically coupled to the source structure and the drain structure through the first silicide metal and second silicide metal, respectively.
The structure may comprise a dielectric material. Accordingly, the method may further include replacing end portions of the structure with the source extension and the drain extension, respectively. The source extension may be interposed between the source structure and the first end of the structure, and the drain extension may be interposed between the drain structure and the second end of the structure. Each of the source extension and drain extension may include at least one of a semiconductor material or a metal material.
Yet another aspect of the present disclosure may be directed to a semiconductor device. The semiconductor device may include a first transistor structure and a second transistor structure. The first transistor structure may include a first two-dimensional (2D) material around a first structure having a first seed layer; a first source/drain extension in electrical contact with the first 2D material; a first source/drain structure electrically coupled to the first 2D material through the first source/drain extension; a second source/drain extension in electrical contact with the first 2D material; a second source/drain structure electrically coupled to the first 2D material through the second source/drain extension; and a first gate structure around at least the first 2D material. The semiconductor device includes a second transistor. The second transistor structure may include a second 2D material around a second structure having a second seed layer; a third source/drain extension in electrical contact with the second 2D material; a third source/drain structure electrically coupled to the second 2D material through the third source/drain extension; a fourth source/drain extension in electrical contact with the second 2D material; a fourth source/drain structure electrically coupled to the second 2D material through the fourth source/drain extension; and a second gate structure around at least the second 2D material. The second transistor structure may be disposed above the first transistor structure and isolated by a dielectric. The first transistor structure may have a first conductive type and the second transistor structure may have a second conductive type, the first conductive type being opposite to the first conductive type
These and other aspects and implementations are discussed in detail below. The foregoing information and the following detailed description include illustrative examples of various aspects and implementations, and provide an overview or framework for understanding the nature and character of the claimed aspects and implementations. The drawings provide illustration and a further understanding of the various aspects and implementations, and are incorporated in and constitute a part of this specification. Aspects can be combined and it will be readily appreciated that features described in the context of one aspect can be combined with other aspects. Aspects can be implemented in any convenient form. As used in the specification and in the claims, the singular form of ‘a’, ‘an’, and ‘the’ include plural referents unless the context clearly dictates otherwise.
Non-limiting embodiments of the present disclosure are described by way of example with reference to the accompanying figures, which are schematic and are not intended to be drawn to scale. Unless indicated as representing the background art, the figures represent aspects of the disclosure. For purposes of simplicity, not every component may be labeled in every drawing. In the drawings:
Reference will now be made to the illustrative embodiments depicted in the drawings, and specific language will be used here to describe the same. It will nevertheless be understood that no limitation of the scope of the claims or this disclosure is thereby intended. Alterations and further modifications of the inventive features illustrated herein, and additional applications of the principles of the subject matter illustrated herein, which would occur to one skilled in the relevant art and having possession of this disclosure, are to be considered within the scope of the subject matter disclosed herein. Other embodiments may be used and/or other changes may be made without departing from the spirit or scope of the present disclosure. The illustrative embodiments described in the detailed description are not meant to be limiting of the subject matter presented.
Disclosed herein are embodiments related to one or more transistor structures formed based on a template structure. In some embodiments, the template structure may be formed of a seed layer that can facilitate the growth of a two-dimensional (2D) material. In some embodiments, the template structure may be formed of a semiconductor core, with its outer surface covered by a seed layer that can also facilitate the growth of a two-dimensional (2D) material. Based on such a template structure, advantageously, the transistor structures, as disclosed herein, may be formed as gate-all-around (GAA) transistor structures with 2D materials. In one aspect, any number of template structures can be easily stacked to form a single transistor structure having improved characteristics in an area efficient manner. In one aspect, any number of transistor structures can be stacked (e.g., vertical direction) to improve area efficiency. In one aspect, 2D materials allow significant boost in performance relative to Si, such that transistor structures disclosed herein may have improved performances or characteristics (e.g., improved transconductance (gm), improved gain bandwidth (Ft), improved saturation current (Idsat), etc.).
Reference will now be made to the figures, which for the convenience of visualizing the 3D fabrication techniques described herein, illustrate a substrate undergoing a process flow in both top and cross-sectional views. Unless expressly indicated otherwise, each Figure represents one (or a set) of fabrication steps in a process flow for manufacturing the devices described herein. In the top and cross-sectional views of the Figures, connections between conductive layers or materials may be shown. However, it should be understood that these connections between various layers and masks are merely illustrative, and are intended to show a capability for providing such connections and should not be considered limiting to the scope of the claims.
Likewise, although the Figures and aspects of the disclosure may show or describe devices herein as having a particular shape, it should be understood that such shapes are merely illustrative and should not be considered limiting to the scope of the techniques described herein. For example, although certain figures show various layers defining transistor structures or other electric structures in a circular configuration, other shapes are also contemplated, and indeed the techniques described herein may be implemented in any shape or geometry.
In various embodiments, operations of the method 100 may be associated with cross-sectional views of an example semiconductor device 200 at various fabrication stages as shown in
In brief overview, the method 100 starts with operation 102 of forming a stack of a number of sacrificial materials and a number of semiconductor materials. The method 100 proceeds to operation 104 of patterning the stack. The method 100 proceeds to operation 106 of depositing a dielectric isolation. The method 100 proceeds to operation 108 of defining source/drain regions in the dielectric isolation. The method 100 proceeds to operation 110 of recessing each of the sacrificial materials. The method 100 proceeds to operation 112 of forming silicide metals. The method 100 proceeds to operation 114 of filling up the recesses. The method 100 proceeds to operation 116 of forming source/drain structures. The method 100 proceeds to operation 118 of exposing sidewalls of each of the semiconductor materials. The method 100 proceeds to operation 120 of removing the sacrificial materials. The method 100 proceeds to operation 122 of forming a dielectric layer around each of the semiconductor materials. The method 100 proceeds to operation 124 of forming a two-dimensional (2D) material, a high-k dielectric, and a gate metal around each of the semiconductor materials. The method 100 proceeds to operation 126 of depositing again the dielectric isolation.
Corresponding to operation 102 of
As shown in
In various embodiments, the sacrificial material 204 (e.g., including a dielectric material) can have an etching selectively with respect to one or more other materials formed next to itself, allowing the sacrificial material to be selectively removed while keeping the adjacent materials substantially intact (which will be discussed in further detail below). The semiconductor material 206 may be selected from the group consisting of: amorphous silicon, crystalline silicon, poly silicon, amorphous germanium, crystalline germanium, poly germanium, and combinations thereof. In this way, surfaces (e.g., top and bottom surfaces, and sidewalls) of the semiconductor material 206, upon at least removing the sacrificial material 204, can be exposed, allowing those surface to be transformed into a material or a seed layer the facilitates growth of a 2D material. The 2D material can function as a channel of the semiconductor device 200 or a portion of the channel. Accordingly, such a semiconductor material 206 can sometimes be referred to as a semiconductor bridge, semiconductor core, semiconductor sheet, or otherwise template structure for growing a 2D material channel, in accordance with various embodiments.
Corresponding to operation 104 of
Corresponding to operation 106 of
Corresponding to operation 108 of
Corresponding to operation 110 of
Corresponding to operation 112 of
Corresponding to operation 114 of
Corresponding to operation 116 of
Corresponding to operation 118 of
Corresponding to operation 120 of
Corresponding to operation 122 of
Corresponding to operation 124 of
The 2D material 230 can include, but are not limited to, graphene, transition metal dichalcogenides (TMDs), WS2, WSe2, WTe2, MoS2, MoSe2, MoTe2, HfS2, ZrS2, TiS2, GaSe, InSe, phosphorene, among others. The 2D material 230, as described herein, may be deposited by an atomic layer deposition (ALD) process and may be 5-15 angstroms thick, the thinness lending to their name-2D material. Other deposition techniques may also be used, including but not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), and plasma-enhanced deposition techniques. The 2D material 230 may be annealed during or after the device formation process to recrystallize or grow the crystals and thereby improve electrical characteristics.
The high-k dielectric 232 can be any type of material that has a relatively large dielectric constant. As one example, a silicon oxide based gate dielectric such as silicon dioxide (SiO2) may be selectively formed on a gate layer of silicon. Additionally or alternatively, other gate dielectric materials may be utilized such as silicon oxynitride (SiOxNy), silicon nitride (Si3N4), alumina (Al2O3), lanthanum oxide (La2O3), zirconium oxide (ZrO2), hafnium oxide (HfO2), hafnium zirconium oxide (HfZrO), tantalum oxide (Ta2O5), hafnium silicon oxide (HfSiO4), zirconium silicon oxide (ZrSiO4), titanium oxide (TiO2), strontium titanium oxide (SrTiO3), hafnium silicon oxynitride (HfSiOxNy), zirconium silicon oxynitride (ZrSiOxNy), hafnium oxynitride (HfOxNy), zirconium oxynitride (ZrOxNy), other suitable materials and combinations thereof. The formation methods of high-k dielectric 232 may include molecular beam deposition (MBD), atomic layer deposition (ALD), PECVD, and the like.
The gate metal 234 may include a p-type work function layer, an n-type work function layer, multi-layers thereof, or combinations thereof, in some embodiments. Accordingly, the gate metal is sometimes referred to as a work function layer or work function metal. Example p-type work function metals that may be included in the gate structures for p-type devices include TiN, TaN, Ru, Mo, Al, WN, ZrSi2, MoSi2, TaSi2, NiSi2, WN, other suitable p-type work function materials, or combinations thereof. Example n-type work function metals that may be included in the gate structures for n-type devices include Ti, Ag, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, other suitable n-type work function materials, or combinations thereof. The work function layer(s) may be deposited by CVD, physical vapor deposition (PVD), ALD, and/or other suitable process.
In various embodiments, the high-k dielectric 232 and gate metal 234 can be collectively referred to as a gate structure. Upon forming such a gate structure, a GAA transistor can be formed. In the present example, the semiconductor device 200, configured as a GAA transistor, includes two semiconductor materials 206 wrapped by the 2D materials 230, respectively. These two 2D materials can collectively function as a channel of the GAA transistor. Further, each of the 2D materials is (e.g., electrically) in contact with the source/drain structures 222 through a respective pair of the silicide metals 218. In some embodiments, the silicide metals 218 may sometimes be referred to as extensions of the source/drain structures 222, e.g., source/drain extensions. Still further, the gate structure, formed of the high-k dielectric 232 and gate metal 234, wraps around each of the 2D materials.
In the illustrative embodiment of
In various embodiments, some of the operations described above with respect to the method 100 (e.g., operations 102 to 116) may be reused in the method 300, and thus, the following discussions will be focused on the different operations. Such (different) operations of the method 300 may be associated with cross-sectional views of an example semiconductor device 400 at various fabrication stages as shown in
In brief overview, the method 300 starts with operation 302 of forming a stack of a number of sacrificial materials and a number of semiconductor materials. The method 300 proceeds to operation 304 of patterning the stack. The method 300 proceeds to operation 306 of depositing a first dielectric isolation. The method 300 proceeds to operation 308 of defining source/drain regions in the first dielectric isolation. The method 300 proceeds to operation 310 of recessing each of the sacrificial materials. The method 300 proceeds to operation 312 of forming silicide metals. The method 300 proceeds to operation 314 of filling up the recesses. The method 300 proceeds to operation 316 of forming source/drain structures. The method 300 proceeds to operation 318 of forming first source/drain structures. The method 300 proceeds to operation 320 of forming second source/drain structures. The method 300 proceeds to operation 322 of exposing sidewalls of each of the semiconductor materials. The method 300 proceeds to operation 324 of removing the sacrificial materials. The method 300 proceeds to operation 326 of forming a dielectric layer around each of the semiconductor materials. The method 300 proceeds to operation 328 of forming a first two-dimensional (2D) material, a first high-k dielectric, and a first gate metal around each of the semiconductor materials. The method 300 proceeds to operation 330 of depositing a second dielectric isolation. The method 300 proceeds to operation 332 of removing a portion of the second dielectric isolation. The method 300 proceeds to operation 334 of removing respective portions of the first gate metal, the high-k dielectric, and the first 2D material. The method 300 proceeds to operation 336 of forming a second 2D material, a second high-k dielectric, and a second gate metal around one or more of the semiconductor materials. The method 300 proceeds to operation 338 of depositing again the first dielectric isolation.
As mentioned above, the operations 302 to 316 are substantially similar to the operations 102 to 116 of the method 100 in
Corresponding to operation 318 of
Corresponding to operation 320 of
In various embodiments, in addition to being electrically isolated from each other by the dielectric material 220, the metal material of the second source/drain structure 406 may be different from the metal material of the first source/drain structure 402. For example, the first semiconductor material 206A may be used to form a first GAA with a first conductive type (e.g., p-type), and the second semiconductor material 206B may be used to form a second GAA with a second, different conductive type (e.g., n-type). As such, the first source/drain structure 402 may include a metal material suitable for a p-type transistor, and the second source/drain structure 406 may include a metal material suitable for an n-type transistor.
Corresponding to operation 322 of
Corresponding to operation 324 of
Corresponding to operation 326 of
Corresponding to operation 328 of
The first 2D material 412 can include, but are not limited to, graphene, transition metal dichalcogenides (TMDs), WS2, WSe2, WTe2, MoS2, MoSe2, MoTe2, HfS2, ZrS2, TiS2, GaSe, InSe, phosphorene, among others. In various embodiments, the first 2D material 412 may be selected from the group above as a suitable channel material for a p-type transistor. The first 2D material 412, as described herein, may be deposited by an atomic layer deposition (ALD) process and may be 5-15 angstroms thick, the thinness lending to their name-2D material. Other deposition techniques may also be used, including but not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), and plasma-enhanced deposition techniques. The first 2D material 412 may be annealed during or after the device formation process to recrystallize or grow the crystals and thereby improve electrical characteristics.
The first high-k dielectric 414 can be any type of material that has a relatively large dielectric constant. As one example, a silicon oxide based gate dielectric such as silicon dioxide (SiO2) may be selectively formed on a gate layer of silicon. Additionally or alternatively, other gate dielectric materials may be utilized such as silicon oxynitride (SiOxNy), silicon nitride (Si3N4), alumina (Al2O3), lanthanum oxide (La2O3), zirconium oxide (ZrO2), hafnium oxide (HfO2), hafnium zirconium oxide (HfZrO), tantalum oxide (Ta2O5), hafnium silicon oxide (HfSiO4), zirconium silicon oxide (ZrSiO4), titanium oxide (TiO2), strontium titanium oxide (SrTiO3), hafnium silicon oxynitride (HfSiOxNy), zirconium silicon oxynitride (ZrSiOxNy), hafnium oxynitride (HfOxNy), zirconium oxynitride (ZrOxNy), other suitable materials and combinations thereof. The formation methods of first high-k dielectric 412 may include molecular beam deposition (MBD), atomic layer deposition (ALD), PECVD, and the like.
The first gate metal 416 may include a p-type work function layer, or multi-layers thereof, in some embodiments. Accordingly, the gate metal is sometimes referred to as a work function layer or work function metal. Example p-type work function metals that may be included in the gate structures for p-type devices include TiN, TaN, Ru, Mo, Al, WN, ZrSi2, MoSi2, TaSi2, NiSi2, WN, other suitable p-type work function materials, or combinations thereof. The work function layer(s) may be deposited by CVD, physical vapor deposition (PVD), ALD, and/or other suitable process.
In various embodiments, the first high-k dielectric 414 and first gate metal 416 can be collectively referred to as a first gate structure. Upon forming such a gate structure, a first GAA transistor can be formed. In the present example, the semiconductor device 400, configured as two GAA transistors stacked on top of one another, includes two semiconductor materials 206A-B wrapped by the first 2D materials 412, respectively. As will be discussed below, the first 2D material 412 around the second semiconductor material 206B will be removed, together with the corresponding first high-k dielectric and first gate metal. The (remaining) first 2D material 412 wrapping around the first semiconductor material 206A can function as a channel of one of the two GAA transistors. Further, the (remaining) first 2D material 412 is (e.g., electrically) in contact with the source/drain structures 402 through a respective pair of the first silicide metals 218A. Still further, the first gate structure, formed of the remaining first high-k dielectric 414 and remaining first gate metal 416, wraps around the remaining first 2D material 412.
In the illustrative embodiment of
Corresponding to operation 332 of
Corresponding to operation 334 of
Corresponding to operation 336 of
The second 2D material 420 can include, but are not limited to, graphene, transition metal dichalcogenides (TMDs), WS2, WSe2, WTe2, MoS2, MoSe2, MoTe2, HfS2, ZrS2, TiS2, GaSe, InSe, phosphorene, among others. In various embodiments, the second 2D material 420 may be selected from the group above as a suitable channel material for an n-type transistor. The second 2D material 420, as described herein, may be deposited by an atomic layer deposition (ALD) process and may be 5-15 angstroms thick, the thinness lending to their name-2D material. Other deposition techniques may also be used, including but not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), and plasma-enhanced deposition techniques. The second 2D material 420 may be annealed during or after the device formation process to recrystallize or grow the crystals and thereby improve electrical characteristics.
The second high-k dielectric 422, which can be the same as the first high-k dielectric 414, can be any type of material that has a relatively large dielectric constant. As one example, a silicon oxide based gate dielectric such as silicon dioxide (SiO2) may be selectively formed on a gate layer of silicon. Additionally or alternatively, other gate dielectric materials may be utilized such as silicon oxynitride (SiOxNy), silicon nitride (Si3N4), alumina (Al2O3), lanthanum oxide (La2O3), zirconium oxide (ZrO2), hafnium oxide (HfO2), hafnium zirconium oxide (HfZrO), tantalum oxide (Ta2O5), hafnium silicon oxide (HfSiO4), zirconium silicon oxide (ZrSiO4), titanium oxide (TiO2), strontium titanium oxide (SrTiO3), hafnium silicon oxynitride (HfSiOxNy), zirconium silicon oxynitride (ZrSiOxNy), hafnium oxynitride (HfOxNy), zirconium oxynitride (ZrOxNy), other suitable materials and combinations thereof. The formation methods of second high-k dielectric 422 may include molecular beam deposition (MBD), atomic layer deposition (ALD), PECVD, and the like.
The second gate metal 424 may include an n-type work function layer, or multi-layers thereof, in some embodiments. Accordingly, the gate metal is sometimes referred to as a work function layer or work function metal. Example n-type work function metals that may be included in the gate structures for n-type devices include Ti, Ag, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, other suitable n-type work function materials, or combinations thereof. The work function layer(s) may be deposited by CVD, physical vapor deposition (PVD), ALD, and/or other suitable process.
In various embodiments, the second high-k dielectric 422 and second gate metal 424 can be collectively referred to as a second gate structure. Upon forming such a gate structure, a second GAA transistor can be formed. In the present example, the second 2D material 420 wrapping around the second semiconductor material 206B can function as a channel of the other of the two GAA transistors. Further, the second 2D material 420 is (e.g., electrically) in contact with the source/drain structures 406 through a respective pair of the second silicide metals 218B. Still further, the second gate structure, formed of the second high-k dielectric 422 and second gate metal 424, wraps around the second 2D material 420.
In the illustrative embodiment of
In various embodiments, operations of the method 500 may be associated with cross-sectional views of an example semiconductor device 600 at various fabrication stages as shown in
In brief overview, the method 500 starts with operation 502 of forming a stack including a first seed layer interposed by first sacrificial materials, a second seed layer interposed by second sacrificial materials, and a first dielectric isolation. The method 500 proceeds to operation 504 of patterning the stack. The method 500 proceeds to operation 506 of depositing a second dielectric isolation. The method 500 proceeds to operation 508 of defining source/drain regions in the second dielectric isolation. The method 500 proceeds to operation 510 of recessing the first sacrificial materials. The method 500 proceeds to operation 512 of filling up the recesses with the first dielectric isolation. The method 500 proceeds to operation 514 of recessing the first seed layer. The method 500 proceeds to operation 516 of forming first source/drain structures. The method 500 proceeds to operation 518 of depositing a third dielectric isolation. The method 500 proceeds to operation 520 of forming second source/drain structures. The method 500 proceeds to operation 522 of exposing a perimeter of the first seed layer. The method 500 proceeds to operation 524 of forming a first two-dimensional (2D) material, a first high-k dielectric, and a first gate metal around the first seed layer. The method 500 proceeds to operation 526 of exposing a perimeter of the second seed layer. The method 500 proceeds to operation 528 of forming a second 2D material, a second high-k dielectric, and a second gate metal around the second seed layer.
Corresponding to operation 502 of
As shown in
In various embodiments, each of the first and second sacrificial materials, 604 and 610, (e.g., including a dielectric material) can have an etching selectively with respect to one or more other materials formed next to itself, allowing the sacrificial material to be selectively removed while keeping the adjacent materials substantially intact (which will be discussed in further detail below). In various embodiments, surfaces (e.g., top and bottom surfaces, and sidewalls) of each of the first and second seed layers, 606 and 612, upon at least removing the corresponding interposing sacrificial materials, can be exposed, allowing those surface to facilitate growth of a 2D material. The 2D material can function as the channel of a corresponding GAA transistor. Example materials of the seed layers, 606 and 612, include, but are not limited to, dielectric materials (e.g., SiO2). Accordingly, such a seed layer can sometimes be referred to as a bridge or otherwise template structure for growing a 2D material channel, in accordance with various embodiments.
In various embodiments, compositions and/or materials of the first seed layer 606 may be configured to facilitate the growth of a first 2D material suitable for an n-type transistor, and compositions and/or materials of the second seed layer 612 may be configured to facilitate the growth of a second 2D material suitable for a p-type transistor.
Corresponding to operation 504 of
Corresponding to operation 506 of
Corresponding to operation 508 of
Corresponding to operation 510 of
Corresponding to operation 512 of
Corresponding to operation 514 of
Corresponding to operation 516 of
Corresponding to operation 518 of
Corresponding to operation 520 of
The recesses can be formed at least by etching the second sacrificial materials 610 through the source/drain regions 622. The etching may be isotropic, anisotropic, or combinations thereof. Specifically, the etching may include applying etchants on exposed sidewalls of the second sacrificial materials 610 and the second seed layer 612, while the etchants may induce a limited etching amount on the second seed layer. As such, the second sacrificial materials 610 may each be inwardly indented on each end with a certain distance. Such a distance can be controlled according to a time duration of the etching process, for example. Next, the recesses may be filled up by performing at least some of the following processes: (1) depositing the first dielectric isolation 608 and filling the recesses through the source/drain regions 622; and (2) removing (e.g., etching) excessive first dielectric isolation 608 using the cap layer 605 as a mask. As such, the newly deposited first dielectric isolation 608 can be self-aligned with the recesses.
Corresponding to operation 522 of
A pair of recesses (not shown) are formed on ends of the second seed layer 612. The recesses can be formed at least by etching the second seed layer 612 through the source/drain regions 622. The etching may be isotropic, anisotropic, or combinations thereof. Specifically, the etching may include applying etchants on exposed sidewalls of the second sacrificial materials 610 and the second seed layers 612, while the etchants may induce a limited etching amount on the second sacrificial materials 610. As such, the second seed layer 612 may be inwardly indented on each end with a certain distance. Such a distance can be controlled according to a time duration of the etching process, for example. Next, the source/drain regions 622 may be filled up with a metal material (e.g., tungsten, titanium, nickel, cobalt, or combinations thereof). Specifically, in addition to filling up the source/drain regions 622 (
Corresponding to operation 524 of
To expose the perimeter of the first seed layer 606, sidewalls of the first seed layer 606 (facing toward and away from the plane) are first exposed by performing at least some of the following processes: (1) forming a (e.g., photoresist) mask 638 having at least an opening; and (2) etching the workpiece (including the first and second sacrificial materials, 604 and 610, and the first and second seed layers, 606 and 612) using the mask 638. Specifically, the opening of the mask 638 is configured to open up at least the sidewalls of the first seed layer 606 that face toward and away from the plane.
Next, the top and bottom surfaces of the first seed layer 606 are exposed by performing at least some of the following processes: (1) continuing using the (e.g., photoresist) mask 638; and (2) performing a selective etching on the first sacrificial materials 604. Such a selective etching may leave the cap layer 605, first seed layer 606, second seed layer 612, second sacrificial materials 610, first dielectric isolation 607, and second dielectric isolation 618 substantially intact. Consequently, a pair of cavities 640, each of which exposes a bottom surface or a top surface of the first seed layer 606, can be formed, which further opens up the full perimeter of the first seed layer 606. As shown, the cavities 640 can further expose a full perimeter of the laterally extending portion of each of the first source/drain structures 630.
Corresponding to operation 526 of
The first 2D material 642 can include, but are not limited to, graphene, transition metal dichalcogenides (TMDs), WS2, WSe2, WTe2, MoS2, MoSe2, MoTe2, HfS2, ZrS2, TiS2, GaSe, InSe, phosphorene, among others. In various embodiments, the first 2D material 642 may be selected from the group above as a suitable channel material for an n-type transistor. The first 2D material 642, as described herein, may be deposited by an atomic layer deposition (ALD) process and may be 5-15 angstroms thick, the thinness lending to their name-2D material. Other deposition techniques may also be used, including but not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), and plasma-enhanced deposition techniques. The first 2D material 642 may be annealed during or after the device formation process to recrystallize or grow the crystals and thereby improve electrical characteristics.
The first high-k dielectric 644 can be any type of material that has a relatively large dielectric constant. As one example, a silicon oxide based gate dielectric such as silicon dioxide (SiO2) may be selectively formed on a gate layer of silicon. Additionally or alternatively, other gate dielectric materials may be utilized such as silicon oxynitride (SiOxNy), silicon nitride (Si3N4), alumina (Al2O3), lanthanum oxide (La2O3), zirconium oxide (ZrO2), hafnium oxide (HfO2), hafnium zirconium oxide (HfZrO), tantalum oxide (Ta2O5), hafnium silicon oxide (HfSiO4), zirconium silicon oxide (ZrSiO4), titanium oxide (TiO2), strontium titanium oxide (SrTiO3), hafnium silicon oxynitride (HfSiOxNy), zirconium silicon oxynitride (ZrSiOxNy), hafnium oxynitride (HfOxNy), zirconium oxynitride (ZrOxNy), other suitable materials and combinations thereof. The formation methods of first high-k dielectric 644 may include molecular beam deposition (MBD), atomic layer deposition (ALD), PECVD, and the like.
The first gate metal 646 may include an n-type work function layer, or multi-layers thereof, in some embodiments. Accordingly, the gate metal is sometimes referred to as a work function layer or work function metal. Example n-type work function metals that may be included in the gate structures for n-type devices include Ti, Ag, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, other suitable n-type work function materials, or combinations thereof. The work function layer(s) may be deposited by CVD, physical vapor deposition (PVD), ALD, and/or other suitable process.
In various embodiments, the first high-k dielectric 644 and first gate metal 646 can be collectively referred to as a first gate structure. Upon forming such a gate structure, a first GAA transistor can be formed. In the present example, the semiconductor device 600, configured as two GAA transistors stacked on top of one another. The first 2D material 642 wrapping around the first seed layer 606 can function as a channel of one of the two GAA transistors. Further, the first 2D material 642 is (e.g., electrically) in contact with the first source/drain structures 630 through their laterally extending portions, respectively. Still further, the first gate structure, formed of first high-k dielectric 644 and first gate metal 646, wraps around the first 2D material 642.
Corresponding to operation 528 of
To expose the perimeter of the second seed layer 612, sidewalls of the second seed layer 612 (facing toward and away from the plane) are first exposed by performing at least some of the following processes: (1) forming a (e.g., photoresist) mask 648 having at least an opening; and (2) etching the workpiece (including the first and second sacrificial materials, 604 and 610, and the first and second seed layers, 606 and 612) using the mask 648. Specifically, the opening of the mask 648 is configured to open up at least the sidewalls of the second seed layer 612 that face toward and away from the plane.
Next, the top and bottom surfaces of the second seed layer 612 are exposed by performing at least some of the following processes: (1) continuing using the (e.g., photoresist) mask 648; and (2) performing a selective etching on the second sacrificial materials 610. Such a selective etching may leave the cap layer 605, first seed layer 606, second seed layer 612, first dielectric isolation 607, and second dielectric isolation 618 substantially intact. Consequently, a pair of cavities 650, each of which exposes a bottom surface or a top surface of the second seed layer 612, can be formed, which further opens up the full perimeter of the second seed layer 612. As shown, the cavities 650 can further expose a full perimeter of the laterally extending portion of each of the second source/drain structures 636.
Corresponding to operation 530 of
The second 2D material 652 can include, but are not limited to, graphene, transition metal dichalcogenides (TMDs), WS2, WSe2, WTe2, MoS2, MoSe2, MoTe2, HfS2, ZrS2, TiS2, GaSe, InSe, phosphorene, among others. In various embodiments, the second 2D material 652 may be selected from the group above as a suitable channel material for a p-type transistor. The second 2D material 652, as described herein, may be deposited by an atomic layer deposition (ALD) process and may be 5-15 angstroms thick, the thinness lending to their name-2D material. Other deposition techniques may also be used, including but not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), and plasma-enhanced deposition techniques. The second 2D material 652 may be annealed during or after the device formation process to recrystallize or grow the crystals and thereby improve electrical characteristics.
The second high-k dielectric 654 can be any type of material that has a relatively large dielectric constant. As one example, a silicon oxide based gate dielectric such as silicon dioxide (SiO2) may be selectively formed on a gate layer of silicon. Additionally or alternatively, other gate dielectric materials may be utilized such as silicon oxynitride (SiOxNy), silicon nitride (Si3N4), alumina (Al2O3), lanthanum oxide (La2O3), zirconium oxide (ZrO2), hafnium oxide (HfO2), hafnium zirconium oxide (HfZrO), tantalum oxide (Ta2O5), hafnium silicon oxide (HfSiO4), zirconium silicon oxide (ZrSiO4), titanium oxide (TiO2), strontium titanium oxide (SrTiO3), hafnium silicon oxynitride (HfSiOxNy), zirconium silicon oxynitride (ZrSiOxNy), hafnium oxynitride (HfOxNy), zirconium oxynitride (ZrOxNy), other suitable materials and combinations thereof. The formation methods of second high-k dielectric 654 may include molecular beam deposition (MBD), atomic layer deposition (ALD), PECVD, and the like.
The second gate metal 656 may include a p-type work function layer, or multi-layers thereof, in some embodiments. Accordingly, the gate metal is sometimes referred to as a work function layer or work function metal. Example p-type work function metals that may be included in the gate structures for p-type devices include TiN, TaN, Ru, Mo, Al, WN, ZrSi2, MoSi2, TaSi2, NiSi2, WN, other suitable p-type work function materials, or combinations thereof. The work function layer(s) may be deposited by CVD, physical vapor deposition (PVD), ALD, and/or other suitable process.
In various embodiments, the second high-k dielectric 654 and second gate metal 656 can be collectively referred to as a second gate structure. Upon forming such a gate structure, a second GAA transistor can be formed. In the present example, the semiconductor device 600, configured as two GAA transistors stacked on top of one another. The second 2D material 652 wrapping around the second seed layer 612 can function as a channel of the other of the two GAA transistors. Further, the second 2D material 652 is (e.g., electrically) in contact with the second source/drain structures 636 through their laterally extending portions, respectively. Still further, the second gate structure, formed of second high-k dielectric 654 and second gate metal 656, wraps around the second 2D material 652.
In various embodiments, some of the operations described above with respect to the method 500 (e.g., operations 502 to 508, 516-518, and 522-530) may be reused in the method 700, and thus, the following discussions will be focused on the different operations. Such (different) operations of the method 700 may be associated with cross-sectional views of an example semiconductor device 800 at various fabrication stages as shown in
In brief overview, the method 700 starts with operation 702 of forming a stack of a number of sacrificial materials and a number of semiconductor materials. The method 700 proceeds to operation 704 of patterning the stack. The method 700 proceeds to operation 706 of depositing a first dielectric isolation. The method 700 proceeds to operation 708 of defining source/drain regions in the first dielectric isolation. The method 700 proceeds to operation 710 of forming first source/drain extensions and second source/drain extensions. The method 700 proceeds to operation 712 of filling up recesses of the first sacrificial materials and recesses of the second sacrificial materials with the first dielectric isolation. The method 700 proceeds to operation 714 of forming first source/drain structures. The method 700 proceeds to operation 716 of depositing a third dielectric isolation. The method 700 proceeds to operation 718 of forming second source/drain structures. The method 700 proceeds to operation 720 of exposing a perimeter of the first seed layer. The method 700 proceeds to operation 722 of forming a first two-dimensional (2D) material, a first high-k dielectric, and a first gate metal around the first seed layer. The method 700 proceeds to operation 724 of exposing a perimeter of the second seed layer. The method 700 proceeds to operation 726 of forming a second 2D material, a second high-k dielectric, and a second gate metal around the second seed layer.
As mentioned above, the operations 702 to 708 are substantially similar to the operations 502 to 508 of the method 500 in
Next, corresponding to operation 710,
The first source/drain extensions 802 are disposed on recessed ends of the first seed layer 606, respectively, and the second source/drain extensions 804 are disposed on recessed ends of the second seed layer 612, respectively. Specifically, the first source/drain extensions 802 may each be inwardly indented toward the first seed layer 606 with respect to the first sacrificial materials 604, and the second source/drain extensions 804 may each be inwardly indented toward the second seed layer 612 with respect to the second sacrificial materials 610.
To form the first source/drain extensions 802 and second source/drain extensions 804, respective end portions of the first seed layer 606 may first be recessed by a selective etching process through the source/drain regions 622. Next, the recesses of the first seed layer 606 are filled with a highly doped metal material or semiconductor material (e.g., poly-Si). In the example where the first seed layer 606 is configured as a template to grow a 2D material for an n-type transistor, the first source/drain extensions 802 may be heavily doped in n-type. Next, respective end portions of the second seed layer 612 may be recessed by a selective etching process through the source/drain regions 622. Next, the recesses of the second seed layer 612 are filled with another highly doped metal material or semiconductor material (e.g., poly-Si). In the example where the second seed layer 612 is configured as a template to grow a 2D material for a p-type transistor, the second source/drain extensions 804 may be heavily doped in p-type.
Next, corresponding to operation 712,
Alternatively or additionally, the second source/drain extensions 804 (e.g., for the p-type transistor) may be formed prior to forming the first source/drain extensions 802 (e.g., for the n-type transistor), as shown in
Next, operations 714 to 726 of the method 700 (similar to operations 516 to 530 of the method 500 except for operation 520, respectively) are performed to continue making the semiconductor device 800, which is substantially similar to the semiconductor device 600 shown in
Having now described some illustrative implementations and implementations, it is apparent that the foregoing is illustrative and not limiting, having been presented by way of example. In particular, although many of the examples presented herein involve specific combinations of method acts or system elements, those acts and those elements may be combined in other ways to accomplish the same objectives. Acts, elements and features discussed only in connection with one implementation are not intended to be excluded from a similar role in other implementations or implementations.
The phraseology and terminology used herein is for the purpose of description and should not be regarded as limiting. The use of “including” “comprising” “having” “containing” “involving” “characterized by” “characterized in that” and variations thereof herein, is meant to encompass the items listed thereafter, equivalents thereof, and additional items, as well as alternate implementations consisting of the items listed thereafter exclusively. In one implementation, the systems and methods described herein consist of one, each combination of more than one, or all of the described elements, acts, or components.
“Substrate” or “target substrate” may include any material portion or structure of a device, particularly a semiconductor or other electronics device, and may, for example, be a base substrate structure, such as a semiconductor wafer, reticle, or a layer on or overlying a base substrate structure such as a thin film. Thus, substrate is not limited to any particular base structure, underlying layer or overlying layer, patterned or un-patterned, but rather, is contemplated to include any such layer or base structure, and any combination of layers and/or base structures. The description may reference particular types of substrates, but this is for illustrative purposes only.
Any references to implementations or elements or acts of the systems and methods herein referred to in the singular may also embrace implementations including a plurality of these elements, and any references in plural to any implementation or element or act herein may also embrace implementations including only a single element. References in the singular or plural form are not intended to limit the presently disclosed systems or methods, their components, acts, or elements to single or plural configurations. References to any act or element being based on any information, act or element may include implementations where the act or element is based at least in part on any information, act, or element.
Any implementation disclosed herein may be combined with any other implementation, and references to “an implementation,” “some implementations,” “an alternate implementation,” “various implementation,” “one implementation” or the like are not necessarily mutually exclusive and are intended to indicate that a particular feature, structure, or characteristic described in connection with the implementation may be included in at least one implementation. Such terms as used herein are not necessarily all referring to the same implementation. Any implementation may be combined with any other implementation, inclusively or exclusively, in any manner consistent with the aspects and implementations disclosed herein.
References to “or” may be construed as inclusive so that any terms described using “or” may indicate any of a single, more than one, and all of the described terms.
Where technical features in the drawings, detailed description or any claim are followed by reference signs, the reference signs have been included for the sole purpose of increasing the intelligibility of the drawings, detailed description, and claims. Accordingly, neither the reference signs nor their absence have any limiting effect on the scope of any claim elements.
The preceding description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the embodiments described herein and variations thereof. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the principles defined herein may be applied to other embodiments without departing from the spirit or scope of the subject matter disclosed herein. Thus, the present disclosure is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the following claims and the principles and novel features disclosed herein.
While various aspects and embodiments have been disclosed, other aspects and embodiments are contemplated. The various aspects and embodiments disclosed are for purposes of illustration and are not intended to be limiting, with the true scope and spirit being indicated by the following claims.
