Patent Application
20190206718
The present invention relates to semiconductor device fabrication and integrated circuits and, more specifically, to interconnect structures and methods for forming an interconnect structure.
An interconnect structure may be used to electrically connect device structures fabricated by front-end-of-line (FEOL) processing. A back-end-of-line (BEOL) portion of the interconnect structure may include metallization formed using a damascene process in which via openings and trenches etching in a dielectric layer are filled with metal to create features of a metallization level. The dielectric layer may be formed from low-k dielectric materials that provide a reduced capacitance, but such reduced-capacitance dielectric layers are also required to provide a high level of performance.
Improved interconnect structures and methods for forming an interconnect structure are needed.
In an embodiment of the invention, an interconnect structure includes a metallization level including a first metallization structure, a second metallization structure, and a first cavity with an entrance arranged between the first metallization structure and the second metallization structure. A cap layer is located over the metallization level, and is arranged relative to the first metallization structure and the second metallization structure to close the entrance to the cavity. A dielectric layer is arranged on surfaces surrounding the cavity, between the cap layer and the first metallization structure, and between the cap layer and the second metallization structure. The dielectric layer and cap layer encapsulate an air gap inside the cavity.
In an embodiment of the invention, a method includes forming a first metallization structure and a second metallization structure in an intralayer dielectric layer, and removing the intralayer dielectric layer to form a cavity with an entrance between the first metallization structure and the second metallization structure. The method further includes depositing a dielectric layer on surfaces surrounding the cavity, over the first metallization structure, and over the second metallization structure, and forming a sacrificial material inside the cavity after the dielectric layer is deposited. The method further includes depositing a cap layer on the dielectric layer over the first metallization structure, on the dielectric layer over the second metallization structure, and on the sacrificial material to close the entrance to the cavity. After the cap layer is deposited, the sacrificial material is removed from the cavity. The dielectric layer and cap layer encapsulate an air gap inside the cavity.
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate various embodiments of the invention and, together with a general description of the invention given above and the detailed description of the embodiments given below, serve to explain the embodiments of the invention.
With reference to
The openings 18 in the intralayer dielectric layer 10 may be formed by lithography and etching at selected locations distributed across the surface area of intralayer dielectric layer 10. The openings 18 may be contact openings, via openings, or trenches and, in that regard, may have an aspect ratio of height-to-width that is characteristic of a contact opening, a via opening, or a trench. In an embodiment, the openings 18 may be trenches that are formed in the intralayer dielectric layer 10.
The interior surfaces surrounding each of the openings 18 may be coated with a liner layer 20 of a given conformal thickness. The liner layer 20 may be composed of one or more conductive materials (i.e., conductors), such as titanium nitride (TiN), tantalum nitride (TaN), tantalum (Ta), titanium (Ti), tungsten (W), tungsten nitride (WN), ruthenium (Ru), rhenium (Re), a layered stack of these conductive materials (e.g., a bilayer of Ti and TiN), or a combination of these conductive materials, deposited by, for example, physical vapor deposition (PVD) or chemical vapor deposition (CVD). The metallization structures 14, 16 may be sections of a conductor layer that is deposited in the openings 18 after the liner layer 20. The conductor layer may be composed of a metal, such as copper (Cu), cobalt (Co), ruthenium (Ru), or rhenium (Re) that is deposited by electroless or electrolytic deposition. The respective materials of the liner layer 20 and the conductor layer also deposit in the field area on the top surface 11 of the intralayer dielectric layer 10, and may be removed from the field area with a chemical mechanical polishing (CMP) process.
A hardmask layer 22 is deposited and patterned to define a block mask covering an area of the intralayer dielectric layer 10 in a defined region 24 in which the metallization structures 14 will be subsequently contacted from above by vias in an overlying metallization level and air gaps are undesired. The hardmask layer 22 may be composed of a dielectric material, such as silicon nitride (Si3N4), deposited by chemical vapor deposition (CVD), and may be patterned with a lithography and etching process selective to the material of the intralayer dielectric layer 10. As used herein, the term “selective” in reference to a material removal process (e.g., etching) denotes that the material removal rate (i.e., etch rate) for the targeted material is higher than the material removal rate (i.e., etch rate) for at least another material exposed to the material removal process.
Regions 25 and 26 of the intralayer dielectric layer 10 are not masked by the hardmask layer 22, and may represent respective regions in which air gaps to be formed. In regions 24 and 25, the metallization structures 14 are separated from each other by a spacing, s1. In region 26, the metallization structure 16 is separated from the nearest metallization structure 14 by a spacing, s2, that is greater than the spacing, s1, in regions 24 and 25. In conventional air gap formation processes, the region 26 is also masked by a block mask because of the inability to form closed air gaps with pinchoff because of the wide spacing in region 26.
With reference to
In an embodiment, the unmasked material of the intralayer dielectric layer 10 in regions 25 and 26 may be damaged and removed, along with the hardmask layer 22, by an etching process, such as wet chemical etching using a solution of dilute hydrofluoric acid (dHF). For example, the unmasked material of the intralayer dielectric layer 10 may be damaged by exposure to radicals (i.e., uncharged or neutral species) generated from a gas mixture of nitrogen (N2) and hydrogen (H2) in a remote plasma.
The height of the cavities 28, 30 may extend in a vertical direction over the full height of the metallization structures 14, 16 to terminate near the respective bottom surfaces of the metallization structures 14, 16. Each of the cavities 28 extends horizontally from the liner layer 20 on one of the metallization structures 14 to the liner layer 20 on another of the metallization structures 14. The cavity 30 is partially surrounded by surfaces 29 and includes an entrance 31 that allows access to the space that is partially surrounded by the surfaces 29. The cavity 30 extends horizontally from a surface 29 of the liner layer 20 at the sidewall of one of the metallization structures 14 to a surface 29 of the liner layer 20 at the sidewall of the metallization structure 16. The volume of the cavities 28 is less than the volume of the cavity 30 and, in particular, the width at the entrance 31 to the cavity 30 is greater than the width at the respective entrances to the cavities 28.
With reference to
The cavity 30 does not support pinch off because of its relatively large dimensions (e.g., width) at its entrance 31 in comparison with the entrances to the cavities 28. Instead, the dielectric layer 32 deposits on the surfaces 29 of the cavity 30 and partially surrounds the cavity 30 such that the volume of the cavity 30 is reduced. The dielectric layer 32 narrows the dimensions of the cavity 30, particularly the width of the cavity 30 at its entrance 31, such that the cavity 30 is only partially surrounded by the dielectric layer 32.
With reference to
With reference to
In an embodiment, the cap layer 38 may be composed of a dielectric material, such as silicon nitride (Si3N4), containing a concentration of a porogen that is activated by curing to form pores in a solid matrix. The pores may be connected to provide pathways for gaseous diffusion through the solid matrix, such as the products of the curing process. The porogen is a sacrificial organic-based material in the form of particles that are distributed in the matrix of the cap layer 38 and that are used to generate or form pores when the cap layer 38 is cured. The porosity of the cap layer 38, following curing, may be adjusted by adjusting the concentration of porogen in the matrix. In an alternative embodiment, the cap layer 38 may be composed of a dielectric material, such as silicon nitride (Si3N4), with less than full density than normal density content as may occur with a hydrogen-rich deposition.
With reference to
In an embodiment in which the sacrificial layer 36 is completely removed, the air gap 40 may occupy the entire space formerly occupied by the sacrificial layer 36. The air gap 40 is arranged laterally between the metallization structure 16 and the nearest metallization structure 14 with sections of the dielectric layer 32 arranged as intervening structures. The cap layer 38 is not modified by the removal of the sacrificial layer 36. The cap layer 38 and dielectric layer 32 cooperate to completely surround the air gap 40 with the cap layer 38 extending across the entrance 31 of the cavity 30 (
The air gap 40 may be characterized by a permittivity or dielectric constant of near unity (i.e., vacuum permittivity). The air gap 40 may be filled by atmospheric air at or near atmospheric pressure, may be filled by another gas (e.g., the gas resulting from the decomposition of the energy removal film) at or near atmospheric pressure, or may contain atmospheric air or another gas at a sub-atmospheric pressure (e.g., a partial vacuum).
In an embodiment in which the cap layer 38 contains a porogen concentration when deposited, the curing of the dielectric material of the cap layer 38 to convert its porogen concentration to pores and to provide its porosity may cause the sacrificial layer 36 to decompose into its gaseous state, which may be released to the ambient environment through the pores generated in the cap layer 38 during its curing.
The BEOL processing may continue to form additional metallization levels over the cap layer 38. In an embodiment, the metallization structures 14, 16 and the air gaps 34, 40 may be arranged in the lowest or first BEOL metallization level that is stacked closest to the FEOL device structures.
The methods as described above are used in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (e.g., as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case, the chip is mounted in a single chip package (e.g., a plastic carrier, with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (e.g., a ceramic carrier that has either or both surface interconnections or buried interconnections). In any case, the chip may be integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either an intermediate product or an end product.
References herein to terms such as “vertical”, “horizontal”, “lateral”, etc. are made by way of example, and not by way of limitation, to establish a frame of reference. Terms such as “horizontal” and “lateral” refer to a direction in a plane parallel to a top surface of a semiconductor substrate, regardless of its actual three-dimensional spatial orientation. Terms such as “vertical” and “normal” refer to a direction perpendicular to the “horizontal” and “lateral” direction. Terms such as “above” and “below” indicate positioning of elements or structures relative to each other and/or to the top surface of the semiconductor substrate as opposed to relative elevation.
A feature “connected” or “coupled” to or with another element may be directly connected or coupled to the other element or, instead, one or more intervening elements may be present. A feature may be “directly connected” or “directly coupled” to another element if intervening elements are absent. A feature may be “indirectly connected” or “indirectly coupled” to another element if at least one intervening element is present.
The descriptions of the various embodiments of the present invention have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.
