The field generally relates to bonded structures, and in particular, to bonded structures with an interconnect structure.
A bonded structure can include an electronic component that is mounted to a carrier or a substrate. The bonded structure can include molding material disposed over the electronic component to provide further mechanical support and/or protection for the bonded structure. During manufacturing (and/or operation) of the bonded structure, heat may be applied to the bonded structure. The application of heat (e.g., an annealing process) may impart stresses to the electronic component. Accordingly, there remains a continuing need for improved structures and methods for manufacturing a bonded structure.
Specific implementations will now be described with reference to the following drawings, which are provided by way of example, and not limitation.
Various embodiments disclosure herein relate to bonded structures having improved reliability when heated, for example, during manufacturing and/or bonding. A bonded structure can include a interconnect structure (e.g., an RDL), a first die bonded to the interconnect structure, a second die bonded to the interconnect structure, and a low coefficient of thermal expansion (CTE) layer disposed between the first die and the second die. The bonded structure can also include a molding material that is disposed between the first die and the second die. The first die and/or the second die can be directly bonded to the interconnect structure without an intervening adhesive.
Two or more semiconductor elements (such as integrated device dies, wafers, etc.) may be stacked on or bonded to one another to form a bonded structure. Conductive contact pads of one element may be electrically connected to corresponding conductive contact pads of another element. Any suitable number of elements can be stacked in the bonded structure.
In some embodiments, the elements (e.g., the first integrated device die 12 and the interconnect structure 10) are directly bonded to one another without an adhesive. In various embodiments, a dielectric field region (e.g., a non-conductive material 32) (also referred to as a nonconductive bonding region) of a first element (e.g., a first semiconductor device die with active circuitry or the first integrated device die 12) can be directly bonded (e.g., using dielectric-to-dielectric bonding techniques) to a corresponding dielectric field region (e.g., a non-conductive material 20) of a second element (e.g., a second semiconductor device die with active circuitry or the interconnect structure 10) without an adhesive. For example, dielectric-to-dielectric bonds may be formed without an adhesive using the direct bonding techniques disclosed at least in U.S. Pat. Nos. 9,564,414; 9,391,143; and 10,434,749, the entire contents of each of which are incorporated by reference herein in their entirety and for all purposes.
In various embodiments, hybrid direct bonds can be formed without an intervening adhesive. For example, dielectric bonding surfaces can be polished to a high degree of smoothness. The bonding surfaces can be cleaned and exposed to a plasma and/or etchants to activate the surfaces. In some embodiments, the surfaces can be terminated with a species after activation or during activation (e.g., during the plasma and/or etch processes). Without being limited by theory, in some embodiments, the activation process can be performed to break chemical bonds at the bonding surface, and the termination process can provide additional chemical species at the bonding surface that improves the bonding energy during direct bonding. In some embodiments, the activation and termination are provided in the same step, e.g., a plasma or wet etchant to activate and terminate the surfaces. In other embodiments, the bonding surface can be terminated in a separate treatment to provide the additional species for direct bonding. In various embodiments, the terminating species can comprise nitrogen. Further, in some embodiments, the bonding surfaces can be exposed to fluorine. For example, there may be one or multiple fluorine peaks near layer and/or bonding interfaces. Thus, in the directly bonded structures, the bonding interface between two dielectric materials can comprise a very smooth interface with higher nitrogen content and/or fluorine peaks at the bonding interface. Additional examples of activation and/or termination treatments may be found throughout U.S. Pat. Nos. 9,564,414; 9,391,143; and 10,434,749, the entire contents of each of which are incorporated by reference herein in their entirety and for all purposes.
In various embodiments, conductive contact pads of the first element can be directly bonded to corresponding conductive contact pads of the second element. For example, a hybrid bonding technique can be used to provide conductor-to-conductor direct bonds along a bond interface that includes covalently direct bonded dielectric-to-dielectric surfaces, prepared as described above. In various embodiments, the conductor-to-conductor (e.g., contact pad to contact pad) direct bonds and the dielectric-to-dielectric hybrid bonds can be formed using the direct bonding techniques disclosed at least in U.S. Pat. Nos. 9,716,033 and 9,852,988, the entire contents of each of which are incorporated by reference herein in their entirety and for all purposes.
For example, dielectric bonding surfaces can be prepared and directly bonded to one another without an intervening adhesive as explained above. Conductive contact pads (which may be surrounded by nonconductive dielectric field regions) may also directly bond to one another without an intervening adhesive. In some embodiments, the respective contact pads can be recessed below exterior (e.g., upper) surfaces of the dielectric field or nonconductive bonding regions, for example, recessed by less than 20 nm, less than 15 nm, or less than 10 nm, for example, recessed in a range of 2 nm to 20 nm, or in a range of 4 nm to 10 nm. The nonconductive bonding regions can be directly bonded to one another without an adhesive at room temperature in some embodiments and, subsequently, the bonded structure can be annealed. Upon annealing, the contact pads can expand and contact one another to form a metal-to-metal direct bond. Beneficially, the use of Direct Bond Interconnect, or DBI®, techniques can enable high density of pads connected across the direct bond interface (e.g., small or fine pitches for regular arrays). In some embodiments, the pitch of the bonding pads may be less 40 microns or less than 10 microns or even less than 2 microns. For some applications the ratio of the pitch of the bonding pads to one of the dimensions of the bonding pad is less than 5, or less than 3 and sometimes desirably less than 2. In various embodiments, the contact pads can comprise copper, although other metals may be suitable.
Thus, in direct bonding processes, a first element can be directly bonded to a second element without an intervening adhesive. In some arrangements, the first element can comprise a singulated element, such as a singulated integrated device die. In other arrangements, the first element can comprise a carrier or substrate (e.g., a wafer) that includes a plurality (e.g., tens, hundreds, or more) of device regions that, when singulated, form a plurality of integrated device dies. Similarly, the second element can comprise a singulated element, such as a singulated integrated device die. In other arrangements, the second element can comprise a carrier or substrate (e.g., a wafer).
As explained herein, the first and second elements can be directly bonded to one another without an adhesive, which is different from a deposition process. The first and second elements can accordingly comprise non-deposited elements. Further, directly bonded structures, unlike deposited layers, can include a defect region along the bond interface in which nanovoids are present. The nanovoids may be formed due to activation of the bonding surfaces (e.g., exposure to a plasma). As explained above, the bond interface can include concentration of materials from the activation and/or last chemical treatment processes. For example, in embodiments that utilize a nitrogen plasma for activation, a nitrogen peak can be formed at the bond interface. In embodiments that utilize an oxygen plasma for activation, an oxygen peak can be formed at the bond interface. In some embodiments, the bond interface can comprise silicon oxynitride, silicon oxycarbonitride, or silicon carbonitride. The bonding layers can also comprise polished surfaces that are planarized to a high degree of smoothness.
In various embodiments, the metal-to-metal bonds between the contact pads can be joined such that copper grains grow into each other across the bond interface. In some embodiments, the copper can have grains oriented along the 111 crystal plane for improved copper diffusion across the bond interface. The bond interface can extend substantially entirely to at least a portion of the bonded contact pads, such that there is substantially no gap between the nonconductive bonding regions at or near the bonded contact pads. In some embodiments, a barrier layer may be provided under the contact pads (e.g., which may include copper). In other embodiments, however, there may be no barrier layer under the contact pads, for example, as described in US 2019/0096741, which is incorporated by reference herein in its entirety and for all purposes.
In some embodiments, the carrier 11 can remain with the interconnect structure until after the application of the molding material 16. However, in some other processes, the carrier 11 can be removed from the interconnect structure 10 at any suitable time, for example, before application of the molding material 16, or before application of the dielectric layer 18. For example, the carrier can be removed from the interconnect structure after the step shown in
In some embodiments, the interconnect structure 10 can comprise a redistribution layer (RDL). In some embodiments, the interconnect structure 10 can serve as an alignment layer by locking and aligning the relative lateral positions of the dies 12, 14 relative to one another. The interconnect structure 10 can comprise a non-conductive material 20, a plurality of conductive lines 22 formed in the non-conductive material 20, a plurality of conductive vias 23 formed in the non-conductive material 20. In some embodiments, a conductive via 23 can extend through a thickness of the non-conductive material 20. The non-conductive material 20 can comprise any suitable material. For example, the non-conductive material 20 can comprise a dielectric material, such as an oxide material (e.g., silicon oxide), a nitride material (e.g., silicon nitride), or amorphous silicon. In some embodiments, the interconnect structure 10 can have an upper contact surface 10a that comprises a plurality of conductive pads (e.g., a first conductive pad 24a and a second conductive pad 24b), and a non-conductive region 26 at least between the first conductive pad 24a and the second conductive pad 24b.
The first integrated device die 12 and/or the second integrated device die 14 can comprise any suitable type of device die. For example, the first integrated device die 12 and/or the second integrated device die 14 can comprise an electronic component such as a processor die, a memory die, a microelectromechanical systems (MEMS) die, an optical device, or any other suitable type of device die. In some embodiments, the first integrated device die 12 and/or the second integrated device die 14 can comprise a stack of a plurality of dies. In other embodiments, the electronic component can comprise a passive device such as a capacitor, inductor, or other surface-mounted device. Circuitry (such as active components like transistors) can be patterned at or near active surface(s) of the first integrated device die 12 and/or the second integrated device die 14 in various embodiments. The active surfaces may be on a side of the first integrated device die 12 and/or the second integrated device die 14 which is opposite respective backsides of the dies first integrated device die 12 and/or the second integrated device die 14. The backsides may or may not include any active circuitry or passive devices. The first integrated device die 12 and the second integrated device die 14 may be the same type of integrated device die or a different type of device die.
The first die 12 can comprise a bonding surface 12a and an upper surface 12b opposite the bonding surface 12a. The bonding surface 12a can have a conductive bond pad 30, and a non-conductive material 32 proximate to the conductive bond pad 30. In some embodiments, the conductive bond pad 30 can be bonded to the first conductive pad 24a, and the non-conductive material 32 can be bonded to a portion of the non-conductive region 26. In some embodiments, the conductive bond pad 30 can be directly bonded to the first conductive pad 24a without an intervening adhesive, and the non-conductive material 32 can be directly bonded to the portion of the non-conductive region 26 without an intervening adhesive. The non-conductive materials 32, 36 and conductive bond pads 30, 24 can be directly bonded without an adhesive as described below.
The second die 14 can comprise a bonding surface 14a and a back surface 14b opposite the bonding surface 14a. The bonding surface 14a can have a conductive bond pad 34, and a non-conductive material 36 proximate to the conductive bond pad 34. In some embodiments, the conductive bond pad 34 can be bonded to the second conductive pad 24b, and the non-conductive material 36 can be bonded to a portion of the non-conductive region 26. In some embodiments, the conductive bond pad 34 can be directly bonded to the second conductive pad 24b without an intervening adhesive, and the non-conductive material 36 can be directly bonded to the portion of the non-conductive region 26 without an intervening adhesive.
In some embodiments, the first integrated device die 12 and/or the second integrated device die 14 can be bonded to the interconnect structure 10 such that, the active surface(s) of the first integrated device die 12 and/or the second integrated device die 14 face the interconnect structure 10. In some embodiments, the first integrated device die 12 and/or the second integrated device die 14 can be bonded to the interconnect structure 10 such that, the active surface(s) of the first integrated device die 12 and/or the second integrated device die 14 face away the interconnect structure 10. In some embodiments, the active surface of one of the first integrated device die 12 and the second integrated device die 14 faces the interconnect structure 10 and the active surface of the other one of the first integrated device die 12 and the second integrated device die 14 faces away the interconnect structure 10. In the illustrated embodiment, the dielectric layer 18 and the non-conductive material 32 can be flush with the upper surface of the interconnect structure 10. The non-conductive material 32 can accordingly extend along side surfaces of the bulk portion of the dies 12, 14 and along side surfaces of the non-conductive material 32.
The molding material 16 can comprise a polymer, epoxy, resin, or the like material. In some embodiments, the molding material 16 provide mechanical support for the first integrated device die 12 and/or the second integrated device die 14. In some embodiments, the molding material 16 can at least partially fill a gap 40 between the first integrated device die 12 and the second integrated device die 14. The CTE of the molding material 16 may be relatively high such that the molding material 16 may expand when heated, which can induce stresses in the dies 12, 14 and/or the interconnect structure 10.
The low CTE layer 18 can comprise any suitable material. In some embodiments, the low CTE layer 18 can have a CTE that is equal to or lower than that of the non-conductive material 20 of the interconnect structure 10, the non-conductive material 32 of the first die 12, or the non-conductive material 36 of the second die 14. In some embodiments, the low CTE layer 18 can have a CTE that is lower than that of the molding material 16. In some embodiments, the low CTE layer 18 can comprise a dielectric layer. For example, the low CTE layer 18 can comprise a silicon oxide layer. The use of a low CTE layer 18 can reduce the overall thermal mismatch between the molding material 16 and the other components of the structure. The layer 18 can comprise a material that is different from or the same as non-conductive material 32. The layer 18 can be a different material from the molding material 16. The low CTE layer 18 can beneficially reduce and/or remove stresses at the first die 12, the interconnect structure 10, and the molding material 16 during manufacture (or operation) relative to a similar bonded structure without a low CTE layer. In some embodiments, the low CTE layer 18 can have a thickness in a range of, for example, 1 μm to 10 μm, in a range of, for example, 1 μm to 5 μm, in a range of, for example, 3 μm to 10 μm, in a range of, for example, 5 μm to 10 μm, or in a range of, for example, 3 μm to 5 μm.
In some embodiments, the low CTE layer 18 can be disposed along at least a portion of a sidewall 12c of the first integrated device die 12. In the illustrated embodiment, the layer 18 may be disposed only along the sidewall 12c, e.g., not along the upper surface 12b of the integrated device die 12. In some embodiments, a majority of the upper surface 12b of the integrated device die 12 can be free from the low CTE layer 18. In some embodiments, the low CTE layer 18 can be disposed along at least a portion of a sidewall 14c of the second integrated device die 14. In some embodiments, the low CTE layer 18 can be applied to the upper surface 12b and the sidewall 12c of the die 12, and the low CTE layer 18 can be removed from the upper surface 12b by, for example, lapping. In the illustrated embodiment, the layer 18 may be disposed only along the sidewall 14c, e.g., not along the upper surface of the die 14. In some embodiments, the low CTE layer 18 can be disposed along at least a portion of the upper contact surface 10a of the interconnect structure 10. In some embodiments, the low CTE layer 18 can comprise a conformal layer that conform with surfaces of the first die 12, second die 14, and the interconnect structure 10. In some embodiments, the low CTE layer 18 can separate the molding material 16 from surfaces of the first die 12, second die 14, and the interconnect structure 10. In some embodiments, the low CTE layer 18 completely separates the molding material 16 from the interconnect structure 10 such that no portion of the molding material directly contacts the interconnect structure 10. In some embodiments, the low CTE layer 18 can have a CTE in a range of, for example, 3 ppm to 7 ppm, in a range of, for example, 3 ppm to 5 ppm, in a rage of, for example, 5 ppm to 7 ppm.
In some embodiments, the low CTE layer 18 can improve rigidity of the bonded structure 1. In some embodiments, the low CTE layer 18 can provide more reliability during manufacture (and/or operation) of the bonded structure 1 than a similar bonded structure without a low CTE layer. A similar bonded structure without the low CTE layer can have a high stress region at a three point corner or edge between its die, interconnect structure, and molding material. In the bonded structure 1, the low CTE layer 18 can move or shift the high stress region from the three point corner to a region near a corner between the CTE layer 18 and the interconnect structure 10 thereby reducing the stress applied to the first die 12 or the second die 14. For example, the low CTE layer 18 can reduce stress applied to the first and second dies 12, 14 during manufacturing (and/or operation) of the bonded structure.
Bonding surfaces (e.g., the upper contact surface 10a, the bonding surface 12a, and the bonding surface 14a) can be polished or planarized, activated, and terminated with a suitable species. For example, in various embodiments, one or more of the non-conductive region 26, the non-conductive material 32 at the bonding surface 12a, and the conductive bond pad 34 (e.g., non-conductive material) at the bonding surface 14a may comprise an inorganic dielectric material, for example, silicon oxide. The bonding surfaces can be polished to a root-mean-square (rms) surface roughness of less than 2 nm, e.g., less than 1 nm, less than 0.5 nm, etc. The polished bonding surfaces can be activated by for example, a process comprising atmospheric or a vacuum plasma method. In various embodiments, the bonding surfaces can be terminated with nitrogen, for example, by way of wet or dry etching (e.g., very slight etching (VSE)) using, for example, a nitrogen-containing solution or by using a plasma etch with nitrogen. In some embodiments, a portion of the non-conductive region 26 and the non-conductive material 32 at the bonding surface 12a can be brought into contact to form a direct bond at room temperature without application of external pressure and without an adhesive. In some embodiments, a non-conductive region 26 and the conductive bond pad 34 at the bonding surface 14a can be brought into contact to form a direct bond at room temperature without application of external pressure and without an adhesive.
In some embodiments, the bonded structure 1 can be heated further to improve the bond strength between the opposing bonding surfaces of the interconnect structure 10 and the first die 12 and/or the second die 14, and to form reliable electrical and mechanical contact at the interface between the interconnect structure 10 and the first die 12 or the second die 14. For example, in some embodiments, the respective contact pads 24a, 24b, and conductive bond pads 30, 34 can be flush with the surface of the respective non-conductive region 26 and non-conductive materials 32, 36, or can be recessed below the non-conductive region 26 and non-conductive materials 32, 36, for example, recessed in a range of 0 nm to 20 nm, or in a range of 4 nm to 10 nm. Portions of the non-conductive region 26 and the non-conductive materials 32, 36 can be directly bonded to one another without an adhesive at room temperature and, subsequently, the bonded structure 1 can be annealed. Upon annealing, the contact pads 24a, 24b, and conductive bond pads 30, 34 can expand and contact one another to form a metal-to-metal direct bond. The metal-to-metal direct bonds can provide an electrical and a mechanical connection between the opposing bonding surfaces of the interconnect structure 10 and the first die 12 and/or the second die 14. Additional details of the direct bonding processes used in conjunction with each of the disclosed embodiments may be found throughout U.S. Pat. Nos. 7,126,212; 8,153,505; 7,622,324; 7,602,070; 8,163,373; 8,389,378; 7,485,968; 8,735,219; 9,385,024; 9,391,143; 9,431,368; 9,953,941; 9,716,033; 9,852,988; 10,032,068; 10,204,893; 10,434,749; and 10,446,532, the contents of each of which are hereby incorporated by reference herein in their entirety and for all purposes.
The carrier 11 can be removed from the interconnect structure 10 to transfer the RDL to the electronic component (e.g., the first integrated device die 12) at any suitable time in the manufacturing process. For example, the carrier 11 can be removed from the interconnect structure 10 after the step 39a and before the step 39b, after the step 39b and before the step 39c, after the step 39c and before the step 39d, after the step 39d and before the step 39e, after the step 39e and before the step 39f, or after the step 39f.
The support structure 50 can comprise any suitable material for supporting the first integrated device die 12 and/or the second integrated device die 14, such as a silicon handle wafer or other structure. The support structure 50 can be positioned such that the first integrated device die 12 and the second integrated device die 14 are positioned between the support structure 50 and the interconnect structure 10.
In some embodiments, the support structure 50 can comprise a third integrated device die. In such embodiments, the support structure may provide an electrical connection between the first integrated device die 12 and the second integrated device die 14. Also, the third integrated device die can electrically connect to the interconnect structure 10 by way of a via (not illustrated) formed in the first integrated device die 12, the second integrated deice die 14, or the molding material 16.
The substrate 54 can comprise a conductive via 56 the extends at least partially through the substrate. In some embodiments, the via 56 can be electrically coupled with the first integrated deice die 12 and/or the second integrated device die 14 through the interconnect structure 10. The substrate 54 can comprise any suitable material. In some embodiments, the substrate 54 can comprise a semiconductor die.
In one embodiment, a bonded structure is disclosed. The bonded structure can include an interconnect structure that has conductors at least partially embedded in a non-conductive material and an upper surface. The upper surface includes a first conductive pad, a second conductive pad, and a non-conductive region. The bonded structure can also include a first integrated device die that has a first bonding surface. The first bonding surface includes a first conductive bond pad and a first non-conductive material. The first conductive bond pad is directly bonded to the first conductive pad without an intervening adhesive. The first non-conductive material can be directly bonded to a first portion of the non-conductive region. The bonded structure can further include a second integrated device die that is mounted to the interconnect structure. The second integrated device die can be spaced apart from the first integrated device die laterally along the upper surface of the interconnect structure. The second integrated device die can be electrically connected with the first integrated device die through at least the interconnect structure. The bonded structure can further include a dielectric layer that is disposed over the upper surface of the interconnect structure between the first integrated device die and the second integrated device die.
In one embodiment, the bonded structure further includes a molding material positioned over the dielectric layer between the first integrated device die and the second integrated device die.
In one embodiment, the dielectric layer has a coefficient of thermal expansion (CTE) lower than a CTE of the molding material
In one embodiment, the interconnect structure includes a transfer redistribution layer (RDL).
In one embodiment, the dielectric layer comprises a silicon oxide layer.
In one embodiment, the dielectric layer is disposed between the molding material and the first integrated device die and between the molding material and a portion of the upper surface of the interconnect structure.
In one embodiment, the dielectric layer is disposed along a sidewall of the first integrated device die, a portion of the upper surface of the interconnect structure, and a sidewall of the second integrated device die.
In one embodiment, the first bonding surface of the first integrated device die comprises an active surface of the first integrated device die.
The second integrated device die can include a back side opposite the second bonding surface. The back side of the second integrated device die comprises an active surface of the second integrated device die.
In one embodiment, the bonded structure further includes a support structure that is coupled to the first integrated device die and the second integrated device die such that the first integrated device die and the second integrated device die are positioned between the interconnect structure and the support structure.
In one embodiment, the interconnect structure includes a first conductive line connected to the first conductive pad by way of a first conductive via, and a second conductive line connected to the second conductive pad by way of a second conductive via.
In one embodiment, the second integrated device die comprises a second bonding surface. The second bonding surface can include a second conductive bond pad and a second non-conductive material. The second conductive bond pad can be bonded to the second conductive pad. The second non-conductive material can be bonded to a second portion of the non-conductive region that is different from the first portion.
In one embodiment, the second conductive bond pad is directly bonded to the second conductive pad without an intervening adhesive, and the second non-conductive material is directly bonded to a second portion of the non-conductive region different from the first portion without an intervening adhesive.
In one aspect, a bonded structure is disclosed. The bonded structure can include an interconnect structure that has conductors at least partially embedded in a non-conductive material and an upper surface. The upper surface includes a first conductive pad, a second conductive pad in electrical communication with the first conductive pad, and a non-conductive region. The bonded structure can also include a first integrated device die that has a first bonding surface. The first bonding surface can include a first conductive bond pad and a first non-conductive material. The first conductive bond pad can be directly bonded to the first conductive pad without an intervening adhesive. The first non-conductive material can be directly bonded to a first portion of the non-conductive region. The bonded structure can also include a second integrated device die that is mounted to the interconnect structure. The second die can be spaced apart from the first integrated device die laterally along the upper surface of the interconnect structure. The bonded structure can also include a molding material that is disposed between the first integrated device die and the second integrated device die. The bonded structure can further include a dielectric layer that is disposed at least between the molding material and the first integrated device die or between the molding material and the upper surface of the interconnect structure.
In one embodiment, the dielectric layer has a coefficient of thermal expansion that is (CTE) lower than a CTE of the molding material
In one embodiment, the interconnect structure comprises a transfer redistribution layer (RDL).
In one embodiment, the dielectric layer includes a silicon oxide layer.
In one embodiment, the dielectric layer is disposed between the molding material and the first integrated device die and between the molding material and a portion of the upper surface of the interconnect structure. The dielectric layer can be disposed along a sidewall of the first integrated device die, a portion of the upper surface of the interconnect structure, and a sidewall of the second integrated device die.
In one embodiment, the first bonding surface of the first integrated device die includes an active surface of the first integrated device die. The second integrated device die can include a back side opposite the second bonding surface. The back side of the second integrated device die can include an active surface of the second integrated device die.
In one embodiment, the bonded structure further includes a support structure that is coupled to the first integrated device die and the second integrated device die such that the first integrated device die and the second integrated device die are positioned between the interconnect structure and the support structure.
In one embodiment, the interconnect structure includes a first conductive line connected to the first conductive pad by way of a first conductive via, and a second conductive line connected to the second conductive pad by way of a second conductive via.
In one embodiment, the second die comprises a second bonding surface. The second bonding surface can include a second conductive bond pad and a second non-conductive material. The second conductive bond pad can be bonded to the second conductive pad, and the second non-conductive material can be bonded to a second portion of the non-conductive region different from the first portion. The second conductive bond pad can be directly bonded to the second conductive pad without an intervening adhesive, and the second non-conductive material can be directly bonded to a second portion of the non-conductive region different from the first portion without an intervening adhesive.
In one embodiment, the second integrated device die is electrically connected with the first integrated device die at least partially through the interconnect structure.
In one embodiment, a method of manufacturing a bonded structure is disclosed. The method can include providing an interconnect structure that has conductors at least partially embedded in a non-conductive material and an upper surface. The upper surface includes a first conductive pad, a second conductive pad, and a non-conductive region. The method can also include directly bonding a first integrated device die to the interconnect structure. The first integrated device die has a first bonding surface. The first bonding surface can include a first conductive bond pad and a first non-conductive material. The first conductive bond pad can be directly bonded to the first conductive pad without an intervening adhesive, and the first non-conductive material can be directly bonded to a first portion of the non-conductive region. The method can also include directly bonding a second integrated device die to the interconnect structure. The second integrated device die can be spaced apart from the first integrated device die laterally along the upper surface of the interconnect structure. The second integrated device die can be electrically connected with the first integrated device die through at least the interconnect structure. The method can also include forming a dielectric layer over at least a portion of the upper surface of the interconnect structure. The method can further include disposing a molding material over at least a portion of the dielectric layer.
In one embodiment, forming the interconnect structure includes forming the interconnect structure on a carrier. The method can further include removing the carrier from the interconnect structure after mounting the first integrated device die.
In one embodiment, forming the dielectric layer include forming the dielectric layer along a sidewall of the first die, a portion of the upper surface, and a sidewall of the second die.
In one aspect, a bonded structure is disclosed. The bonded structure can include an interconnect structure that has conductors at least partially embedded in a non-conductive material and a upper surface. The upper surface includes a first conductive pad, a second conductive pad, and a non-conductive region between the first conductive pad and the second conductive pad. The bonded structure can also include a first die that has a first bonding surface. The first bonding surface can include a first conductive bond pad and a first non-conductive material. The first bonding surface of the first die can include an active surface of the first die. The first conductive bond pad can be directly bonded to the first conductive pad without an intervening adhesive, and the first non-conductive material can be directly bonded to a first portion of the non-conductive region. The bonded structure can also include a second die that has a second bonding surface facing the interconnect structure. The second die can be mounted to the interconnect structure. The second die can be spaced apart from the first die laterally along the upper surface of the interconnect structure. The second die includes a back side opposite the second bonding surface. The back side of the second die can include an active surface of the second die. The bonded structure can also include a molding material disposed between the first die and the second die. The bonded structure can further include a silicon oxide layer that is disposed between the molding material and the first die or between the molding material and the upper surface of the interconnect structure.
In one embodiment, the interconnect structure includes a redistribution layer, and the first die and the second die are electrically connected with each other at least partially through the interconnect structure.
In one embodiment, the silicon oxide layer is disposed between the molding material and the first die and between the molding material and a portion of the upper surface of the interconnect structure.
In one embodiment, the silicon oxide layer is disposed along a sidewall of the first die, a portion of the upper surface, and a sidewall of the second die.
In one embodiment, the interconnect structure includes a first conductive line connected to the first conductive pad by way of a first conductive via, and a second conductive line connected to the second conductive pad by way of a second conductive via.
In one embodiment, the second bonding surface includes a second conductive bond pad and a second non-conductive material, the second conductive bond pad bonded to the second conductive pad, and the second non-conductive material bonded to a second portion of the non-conductive region different from the first portion.
In one aspect, a bonded structure is disclosed. The bonded structure can include an interconnect structure that has conductors at least partially embedded in a non-conductive material and a upper surface. The upper surface can include a first conductive pad, a second conductive pad, and a non-conductive region surrounding the first conductive pad and the second conductive pad. The bonded structure can also include a first die having a first bonding surface. The first bonding surface can include a first conductive bond pad and a first non-conductive material surrounding the first conductive bond pad. The first bonding surface of the first die can include an active surface of the first die. The first conductive bond pad can be directly bonded to the first conductive pad, and the first non-conductive material can be directly bonded to a first portion of the non-conductive region. The bonded structure can also include a second die that has a second bonding surface facing the interconnect structure. The second die can be mounted to the interconnect structure. The second die can be spaced apart from the first die laterally along the upper surface of the interconnect structure. The bonded structure can further include a molding material disposed between the first die and the second die. A width of the molding material is less than 20% of a width of the first die or second die.
In one aspect, a bonded structure is disclosed. the bonded structure can include an interconnect structure that has conductors at least partially embedded in a non-conductive material and a upper surface. The upper surface includes a first conductive pad, a second conductive pad, and a non-conductive region surrounding the first conductive pad and the second conductive pad. The bonded structure can also include a first die that has a first bonding surface. The first bonding surface can include a first conductive bond pad and a first non-conductive material surrounding the first conductive bond pad. The first bonding surface of the first die can include an active surface of the first die. The first conductive bond pad can be directly bonded to the first conductive pad, and the first non-conductive material can be directly bonded to a first portion of the non-conductive region. The bonded structure can further include a second die that has a second bonding surface facing the interconnect structure. The second die can be mounted to the interconnect structure. The second die can be spaced apart from the first die laterally along the upper surface of the interconnect structure. A thickness of the interconnect structure is thinner than a thickness of the first die or the second die. The thickness of the interconnect structure can be less than 50% of the thickness of the first die or the second die.
Unless the context clearly requires otherwise, throughout the description and the claims, the words “comprise,” “comprising,” “include,” “including” and the like are to be construed in an inclusive sense, as opposed to an exclusive or exhaustive sense; that is to say, in the sense of “including, but not limited to.” The word “coupled”, as generally used herein, refers to two or more elements that may be either directly connected, or connected by way of one or more intermediate elements. Likewise, the word “connected”, as generally used herein, refers to two or more elements that may be either directly connected, or connected by way of one or more intermediate elements. Additionally, the words “herein,” “above,” “below,” and words of similar import, when used in this application, shall refer to this application as a whole and not to any particular portions of this application. Where the context permits, words in the above Detailed Description using the singular or plural number may also include the plural or singular number respectively. The word “or” in reference to a list of two or more items, that word covers all of the following interpretations of the word: any of the items in the list, all of the items in the list, and any combination of the items in the list.
Moreover, conditional language used herein, such as, among others, “can,” “could,” “might,” “may,” “e.g.,” “for example,” “such as” and the like, unless specifically stated otherwise, or otherwise understood within the context as used, is generally intended to convey that certain embodiments include, while other embodiments do not include, certain features, elements and/or states. Thus, such conditional language is not generally intended to imply that features, elements and/or states are in any way required for one or more embodiments.
While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the disclosure. Indeed, the novel apparatus, methods, and systems described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the methods and systems described herein may be made without departing from the spirit of the disclosure. For example, while blocks are presented in a given arrangement, alternative embodiments may perform similar functionalities with different components and/or circuit topologies, and some blocks may be deleted, moved, added, subdivided, combined, and/or modified. Each of these blocks may be implemented in a variety of different ways. Any suitable combination of the elements and acts of the various embodiments described above can be combined to provide further embodiments. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the disclosure.
This application claims priority to U.S. Provisional Patent Application No. 63/074,928, filed Sep. 4, 2020, titled “BONDED STRUCTURE WITH INTERCONNECT STRUCTURE,” the entire contents of each of which are hereby incorporated herein by reference.
Number | Name | Date | Kind |
---|---|---|---|
4998665 | Hayashi | Mar 1991 | A |
5019673 | Juskey et al. | May 1991 | A |
5051802 | Prost et al. | Sep 1991 | A |
5087585 | Hayashi | Feb 1992 | A |
5322593 | Hasegawa et al. | Jun 1994 | A |
5753536 | Sugiyama et al. | May 1998 | A |
5771555 | Eda et al. | Jun 1998 | A |
5854507 | Miremadi et al. | Dec 1998 | A |
5956605 | Akram et al. | Sep 1999 | A |
5985739 | Plettner et al. | Nov 1999 | A |
5998808 | Matsushita | Dec 1999 | A |
6008126 | Leedy | Dec 1999 | A |
6080640 | Gardner et al. | Jun 2000 | A |
6121688 | Akagawa | Sep 2000 | A |
6265775 | Seyyedy | Jul 2001 | B1 |
6374770 | Lee | Apr 2002 | B1 |
6423640 | Lee et al. | Jul 2002 | B1 |
6465892 | Suga | Oct 2002 | B1 |
6582991 | Maeda et al. | Jun 2003 | B1 |
6768208 | Lin et al. | Jul 2004 | B2 |
6782610 | Iijima et al. | Aug 2004 | B1 |
6887769 | Kellar et al. | May 2005 | B2 |
6908027 | Tolchinsky et al. | Jun 2005 | B2 |
7045453 | Canaperi et al. | May 2006 | B2 |
7078811 | Suga | Jul 2006 | B2 |
7105980 | Abbott et al. | Sep 2006 | B2 |
7126212 | Enquist et al. | Oct 2006 | B2 |
7193423 | Dalton et al. | Mar 2007 | B1 |
7319197 | Oggioni et al. | Jan 2008 | B2 |
7354798 | Pogge et al. | Apr 2008 | B2 |
7554203 | Zhou et al. | Jun 2009 | B2 |
7582971 | Kameyama et al. | Sep 2009 | B2 |
7589409 | Gibson et al. | Sep 2009 | B2 |
7663231 | Chang et al. | Feb 2010 | B2 |
7750488 | Patti et al. | Jul 2010 | B2 |
7759751 | Ono | Jul 2010 | B2 |
7786572 | Chen | Aug 2010 | B2 |
7803693 | Trezza | Sep 2010 | B2 |
7977789 | Park | Jul 2011 | B2 |
8049303 | Osaka et al. | Nov 2011 | B2 |
8064224 | Mahajan et al. | Nov 2011 | B2 |
8168458 | Do et al. | May 2012 | B2 |
8178963 | Yang | May 2012 | B2 |
8178964 | Yang | May 2012 | B2 |
8183127 | Patti et al. | May 2012 | B2 |
8193632 | Chang et al. | Jun 2012 | B2 |
8227904 | Braunisch et al. | Jul 2012 | B2 |
8241961 | Kim et al. | Aug 2012 | B2 |
8263434 | Pagaila et al. | Sep 2012 | B2 |
8314007 | Vaufredaz | Nov 2012 | B2 |
8349635 | Gan et al. | Jan 2013 | B1 |
8377798 | Peng et al. | Feb 2013 | B2 |
8441131 | Ryan | May 2013 | B2 |
8476146 | Chen et al. | Jul 2013 | B2 |
8476165 | Trickett et al. | Jul 2013 | B2 |
8482132 | Yang et al. | Jul 2013 | B2 |
8501537 | Sadaka et al. | Aug 2013 | B2 |
8519514 | Fujii | Aug 2013 | B2 |
8524533 | Tong et al. | Sep 2013 | B2 |
8620164 | Heck et al. | Dec 2013 | B2 |
8647987 | Yang et al. | Feb 2014 | B2 |
8691601 | Izuha | Apr 2014 | B2 |
8697493 | Sadaka | Apr 2014 | B2 |
8716105 | Sadaka et al. | May 2014 | B2 |
8791575 | Oganesian et al. | Jul 2014 | B2 |
8802538 | Liu | Aug 2014 | B1 |
8809123 | Liu et al. | Aug 2014 | B2 |
8841002 | Tong | Sep 2014 | B2 |
8878353 | Haba et al. | Nov 2014 | B2 |
8901748 | Manusharow et al. | Dec 2014 | B2 |
8912670 | Teh et al. | Dec 2014 | B2 |
8975726 | Chen et al. | Mar 2015 | B2 |
8987137 | Bachman et al. | Mar 2015 | B2 |
8988299 | Kam et al. | Mar 2015 | B2 |
9093350 | Endo et al. | Jul 2015 | B2 |
9126236 | Roos et al. | Sep 2015 | B2 |
9136293 | Yee et al. | Sep 2015 | B2 |
9142517 | Liu et al. | Sep 2015 | B2 |
9153552 | Teh et al. | Oct 2015 | B2 |
9159690 | Chiu | Oct 2015 | B2 |
9171756 | Enquist et al. | Oct 2015 | B2 |
9171816 | Teh et al. | Oct 2015 | B2 |
9184125 | Enquist et al. | Nov 2015 | B2 |
9190380 | Teh et al. | Nov 2015 | B2 |
9224704 | Landru | Dec 2015 | B2 |
9230941 | Chen et al. | Jan 2016 | B2 |
9252172 | Chow et al. | Feb 2016 | B2 |
9257399 | Kuang et al. | Feb 2016 | B2 |
9269701 | Starkston et al. | Feb 2016 | B2 |
9275971 | Chiu et al. | Mar 2016 | B2 |
9299736 | Chen et al. | Mar 2016 | B2 |
9312229 | Chen et al. | Apr 2016 | B2 |
9331149 | Tong et al. | May 2016 | B2 |
9337235 | Chen et al. | May 2016 | B2 |
9349703 | Chiu et al. | May 2016 | B2 |
9355997 | Katkar et al. | May 2016 | B2 |
9368866 | Yu | Jun 2016 | B2 |
9385024 | Tong et al. | Jul 2016 | B2 |
9394161 | Cheng et al. | Jul 2016 | B2 |
9437572 | Chen et al. | Sep 2016 | B2 |
9443796 | Chou et al. | Sep 2016 | B2 |
9443824 | We et al. | Sep 2016 | B1 |
9461007 | Chun et al. | Oct 2016 | B2 |
9466586 | Choi et al. | Oct 2016 | B1 |
9476898 | Takano | Oct 2016 | B2 |
9496239 | Edelstein et al. | Nov 2016 | B1 |
9536848 | England et al. | Jan 2017 | B2 |
9559081 | Lai et al. | Jan 2017 | B1 |
9601353 | Huang et al. | Mar 2017 | B2 |
9620481 | Edelstein et al. | Apr 2017 | B2 |
9627365 | Yu et al. | Apr 2017 | B1 |
9656852 | Cheng et al. | May 2017 | B2 |
9666502 | Chen et al. | May 2017 | B2 |
9666559 | Wang et al. | May 2017 | B2 |
9704827 | Huang et al. | Jul 2017 | B2 |
9722098 | Chung et al. | Aug 2017 | B1 |
9723716 | Meinhold | Aug 2017 | B2 |
9728521 | Tsai et al. | Aug 2017 | B2 |
9741620 | Uzoh et al. | Aug 2017 | B2 |
9799587 | Fujii et al. | Oct 2017 | B2 |
9852988 | Enquist et al. | Dec 2017 | B2 |
9881882 | Hsu et al. | Jan 2018 | B2 |
9893004 | Yazdani | Feb 2018 | B2 |
9899442 | Katkar | Feb 2018 | B2 |
9929050 | Lin | Mar 2018 | B2 |
9941241 | Edelstein et al. | Apr 2018 | B2 |
9941243 | Kim et al. | Apr 2018 | B2 |
9953941 | Enquist | Apr 2018 | B2 |
9960142 | Chen et al. | May 2018 | B2 |
9966360 | Yu et al. | May 2018 | B2 |
10008844 | Wang et al. | Jun 2018 | B2 |
10026605 | Doub et al. | Jul 2018 | B2 |
10032722 | Yu et al. | Jul 2018 | B2 |
10075657 | Fahim et al. | Sep 2018 | B2 |
10204893 | Uzoh et al. | Feb 2019 | B2 |
10269756 | Uzoh | Apr 2019 | B2 |
10269853 | Katkar et al. | Apr 2019 | B2 |
10276619 | Kao et al. | Apr 2019 | B2 |
10276909 | Huang et al. | Apr 2019 | B2 |
10418277 | Cheng et al. | Sep 2019 | B2 |
10446456 | Shen et al. | Oct 2019 | B2 |
10559507 | Saketi et al. | Feb 2020 | B1 |
10707087 | Uzoh et al. | Jul 2020 | B2 |
10727204 | Agarwal et al. | Jul 2020 | B2 |
10727219 | Uzoh et al. | Jul 2020 | B2 |
10790262 | Uzoh et al. | Sep 2020 | B2 |
10840135 | Uzoh | Nov 2020 | B2 |
10840205 | Fountain, Jr. et al. | Nov 2020 | B2 |
10854578 | Morein | Dec 2020 | B2 |
10879212 | Uzoh et al. | Dec 2020 | B2 |
10886177 | DeLaCruz et al. | Jan 2021 | B2 |
10892246 | Uzoh | Jan 2021 | B2 |
10923413 | DeLaCruz | Feb 2021 | B2 |
10950547 | Mohammed et al. | Mar 2021 | B2 |
10964664 | Mandalapu et al. | Mar 2021 | B2 |
10985133 | Uzoh | Apr 2021 | B2 |
10991804 | DeLaCruz et al. | Apr 2021 | B2 |
10998292 | Lee et al. | May 2021 | B2 |
11011503 | Wang et al. | May 2021 | B2 |
11031285 | Katkar et al. | Jun 2021 | B2 |
11056348 | Theil | Jul 2021 | B2 |
11056390 | Uzoh et al. | Jul 2021 | B2 |
11069734 | Katkar | Jul 2021 | B2 |
11088099 | Katkar et al. | Aug 2021 | B2 |
11127738 | DeLaCruz et al. | Sep 2021 | B2 |
11145626 | Hwang et al. | Oct 2021 | B2 |
11158606 | Gao et al. | Oct 2021 | B2 |
11171117 | Gao et al. | Nov 2021 | B2 |
11176450 | Teig et al. | Nov 2021 | B2 |
11256004 | Haba et al. | Feb 2022 | B2 |
11264357 | DeLaCruz et al. | Mar 2022 | B1 |
11276676 | Enquist et al. | Mar 2022 | B2 |
11329034 | Tao et al. | May 2022 | B2 |
11348898 | DeLaCruz et al. | May 2022 | B2 |
11355443 | Huang et al. | Jun 2022 | B2 |
11387214 | Wang et al. | Jul 2022 | B2 |
11462419 | Haba | Oct 2022 | B2 |
20020000328 | Motomura et al. | Jan 2002 | A1 |
20020003307 | Suga | Jan 2002 | A1 |
20020004288 | Nishiyama | Jan 2002 | A1 |
20020074668 | Hofstee et al. | Jun 2002 | A1 |
20040084414 | Sakai et al. | May 2004 | A1 |
20040238927 | Miyazawa | Dec 2004 | A1 |
20050040530 | Shi | Feb 2005 | A1 |
20050133930 | Savastisuk et al. | Jun 2005 | A1 |
20050153522 | Hwang et al. | Jul 2005 | A1 |
20050218518 | Jiang et al. | Oct 2005 | A1 |
20060057945 | Hsu et al. | Mar 2006 | A1 |
20060087042 | Kameyama et al. | Apr 2006 | A1 |
20060278331 | Dugas et al. | Dec 2006 | A1 |
20070080442 | Meyer-Berg | Apr 2007 | A1 |
20070096294 | Ikeda et al. | May 2007 | A1 |
20070111386 | Kim et al. | May 2007 | A1 |
20070158024 | Addison et al. | Jul 2007 | A1 |
20070158827 | Schuster | Jul 2007 | A1 |
20070222048 | Huang | Sep 2007 | A1 |
20070295456 | Gudeman et al. | Dec 2007 | A1 |
20080079105 | Chang et al. | Apr 2008 | A1 |
20080231311 | Condorelli et al. | Sep 2008 | A1 |
20080265421 | Brunnbauer et al. | Oct 2008 | A1 |
20080308928 | Chang | Dec 2008 | A1 |
20090068831 | Enquist et al. | Mar 2009 | A1 |
20090149023 | Koyanagi | Jun 2009 | A1 |
20090227089 | Plaut et al. | Sep 2009 | A1 |
20090252939 | Park et al. | Oct 2009 | A1 |
20090283898 | Janzen et al. | Nov 2009 | A1 |
20090321939 | Chandrasekaran | Dec 2009 | A1 |
20100081236 | Yang et al. | Apr 2010 | A1 |
20100123268 | Menard | May 2010 | A1 |
20100167534 | Iwata | Jul 2010 | A1 |
20100259166 | Cok et al. | Oct 2010 | A1 |
20100327424 | Braunisch et al. | Dec 2010 | A1 |
20110074033 | Kaltalioglu et al. | Mar 2011 | A1 |
20110290552 | Palmateer et al. | Dec 2011 | A1 |
20120074585 | Koo et al. | Mar 2012 | A1 |
20120187516 | Sato | Jul 2012 | A1 |
20120194719 | Churchwell et al. | Aug 2012 | A1 |
20120199960 | Cosue et al. | Aug 2012 | A1 |
20120212384 | Kam et al. | Aug 2012 | A1 |
20130037962 | Xue | Feb 2013 | A1 |
20130122655 | Yu et al. | May 2013 | A1 |
20130265733 | Herbsommer et al. | Oct 2013 | A1 |
20130299997 | Sadaka | Nov 2013 | A1 |
20140013606 | Nah et al. | Jan 2014 | A1 |
20140154839 | Ahn et al. | Jun 2014 | A1 |
20140175655 | Chen et al. | Jun 2014 | A1 |
20140225795 | Yu | Aug 2014 | A1 |
20140299981 | Goh et al. | Oct 2014 | A1 |
20140312511 | Nakamura | Oct 2014 | A1 |
20140370658 | Tong et al. | Dec 2014 | A1 |
20150021754 | Lin et al. | Jan 2015 | A1 |
20150064498 | Tong | Mar 2015 | A1 |
20150102468 | Kang et al. | Apr 2015 | A1 |
20150171050 | Chen et al. | Jun 2015 | A1 |
20150179481 | Lin | Jun 2015 | A1 |
20150194406 | Teh et al. | Jul 2015 | A1 |
20150262845 | Hwang et al. | Sep 2015 | A1 |
20150340285 | Enquest et al. | Nov 2015 | A1 |
20160126634 | Liu et al. | May 2016 | A1 |
20160163650 | Gao et al. | Jun 2016 | A1 |
20160260684 | Zhai et al. | Sep 2016 | A1 |
20160300813 | Zhai et al. | Oct 2016 | A1 |
20160300817 | Do et al. | Oct 2016 | A1 |
20160322330 | Lin et al. | Nov 2016 | A1 |
20160329284 | We et al. | Nov 2016 | A1 |
20160343682 | Kawasaki | Nov 2016 | A1 |
20160343685 | Lin et al. | Nov 2016 | A1 |
20170062366 | Enquist | Mar 2017 | A1 |
20170062383 | Yee et al. | Mar 2017 | A1 |
20170179078 | Yu et al. | Apr 2017 | A1 |
20170125379 | Chen et al. | May 2017 | A1 |
20170148764 | Wang et al. | May 2017 | A1 |
20170179029 | Enquist et al. | Jun 2017 | A1 |
20170194271 | Hsu et al. | Jul 2017 | A1 |
20170200711 | Uzoh et al. | Jul 2017 | A1 |
20170338214 | Uzoh | Nov 2017 | A1 |
20170365580 | Shih et al. | Dec 2017 | A1 |
20180005984 | Yu et al. | Jan 2018 | A1 |
20180005992 | Yu et al. | Jan 2018 | A1 |
20180012787 | Oka et al. | Jan 2018 | A1 |
20180026008 | Jeng et al. | Jan 2018 | A1 |
20180053746 | Yu et al. | Feb 2018 | A1 |
20180096931 | Huang et al. | Apr 2018 | A1 |
20180122774 | Huang et al. | May 2018 | A1 |
20180130769 | Tan et al. | May 2018 | A1 |
20180138101 | Yu et al. | May 2018 | A1 |
20180174995 | Wang et al. | Jun 2018 | A1 |
20180175012 | Wu et al. | Jun 2018 | A1 |
20180182639 | Uzoh et al. | Jun 2018 | A1 |
20180182666 | Uzoh et al. | Jun 2018 | A1 |
20180190580 | Haba et al. | Jul 2018 | A1 |
20180190583 | DeLaCruz et al. | Jul 2018 | A1 |
20180191047 | Huang et al. | Jul 2018 | A1 |
20180219038 | Gambino et al. | Aug 2018 | A1 |
20180226375 | Enquist et al. | Aug 2018 | A1 |
20180273377 | Katkar et al. | Sep 2018 | A1 |
20180286805 | Huang et al. | Oct 2018 | A1 |
20180323177 | Yu et al. | Nov 2018 | A1 |
20180323227 | Zhang et al. | Nov 2018 | A1 |
20180331066 | Uzoh et al. | Nov 2018 | A1 |
20180366437 | Chen et al. | Dec 2018 | A1 |
20180366442 | Gu et al. | Dec 2018 | A1 |
20180366446 | Haba et al. | Dec 2018 | A1 |
20190096741 | Uzoh et al. | Mar 2019 | A1 |
20190096842 | Fountain, Jr. et al. | Mar 2019 | A1 |
20190115277 | Yu et al. | Apr 2019 | A1 |
20190131277 | Yang et al. | May 2019 | A1 |
20190198407 | Huang et al. | Jun 2019 | A1 |
20190198409 | Katkar et al. | Jun 2019 | A1 |
20190221548 | Huang et al. | Jul 2019 | A1 |
20190265411 | Huang et al. | Aug 2019 | A1 |
20190333550 | Fisch | Oct 2019 | A1 |
20190333871 | Chen et al. | Oct 2019 | A1 |
20190348336 | Katkar et al. | Nov 2019 | A1 |
20190371763 | Agarwal et al. | Dec 2019 | A1 |
20190385935 | Gao et al. | Dec 2019 | A1 |
20190385966 | Gao et al. | Dec 2019 | A1 |
20190385981 | Chen et al. | Dec 2019 | A1 |
20200006309 | Chen | Jan 2020 | A1 |
20200013637 | Haba | Jan 2020 | A1 |
20200013765 | Fountain, Jr. et al. | Jan 2020 | A1 |
20200035641 | Fountain, Jr. et al. | Jan 2020 | A1 |
20200043853 | Kim et al. | Feb 2020 | A1 |
20200058617 | Wu et al. | Feb 2020 | A1 |
20200075520 | Gao et al. | Mar 2020 | A1 |
20200075534 | Gao et al. | Mar 2020 | A1 |
20200075553 | DeLaCruz et al. | Mar 2020 | A1 |
20200118973 | Wang et al. | Apr 2020 | A1 |
20200126906 | Uzoh et al. | Apr 2020 | A1 |
20200135684 | Kim et al. | Apr 2020 | A1 |
20200176419 | Dabral et al. | Jun 2020 | A1 |
20200194396 | Uzoh | Jun 2020 | A1 |
20200227367 | Haba et al. | Jul 2020 | A1 |
20200243380 | Uzoh et al. | Jul 2020 | A1 |
20200279821 | Haba et al. | Sep 2020 | A1 |
20200294908 | Haba et al. | Sep 2020 | A1 |
20200294920 | Hariri et al. | Sep 2020 | A1 |
20200328162 | Haba et al. | Oct 2020 | A1 |
20200328164 | DeLaCruz et al. | Oct 2020 | A1 |
20200328165 | DeLaCruz et al. | Oct 2020 | A1 |
20200335408 | Gao et al. | Oct 2020 | A1 |
20200371154 | DeLaCruz et al. | Nov 2020 | A1 |
20200395300 | Xie et al. | Dec 2020 | A1 |
20200395321 | Katkar et al. | Dec 2020 | A1 |
20200403006 | DeLaCruz et al. | Dec 2020 | A1 |
20200411483 | Uzoh et al. | Dec 2020 | A1 |
20210020577 | Hu | Jan 2021 | A1 |
20210028080 | Pietambaram et al. | Jan 2021 | A1 |
20210057343 | Chang et al. | Feb 2021 | A1 |
20210057352 | Agarwal et al. | Feb 2021 | A1 |
20210066219 | Chen et al. | Mar 2021 | A1 |
20210082797 | Lee et al. | Mar 2021 | A1 |
20210082822 | Aleksov et al. | Mar 2021 | A1 |
20210082825 | Strong et al. | Mar 2021 | A1 |
20210098412 | Haba et al. | Apr 2021 | A1 |
20210098421 | Wu et al. | Apr 2021 | A1 |
20210111125 | Chen et al. | Apr 2021 | A1 |
20210118864 | DeLaCruz et al. | Apr 2021 | A1 |
20210125933 | Chen et al. | Apr 2021 | A1 |
20210125965 | Lu | Apr 2021 | A1 |
20210134724 | Rubin et al. | May 2021 | A1 |
20210143125 | DeLaCruz et al. | May 2021 | A1 |
20210181510 | Katkar et al. | Jun 2021 | A1 |
20210183847 | Uzoh et al. | Jun 2021 | A1 |
20210193603 | Katkar et al. | Jun 2021 | A1 |
20210193624 | DeLaCruz et al. | Jun 2021 | A1 |
20210193625 | DeLaCruz et al. | Jun 2021 | A1 |
20210202396 | Wu et al. | Jul 2021 | A1 |
20210225780 | Wu et al. | Jul 2021 | A1 |
20210242152 | Fountain, Jr. et al. | Aug 2021 | A1 |
20210280507 | Aldrete et al. | Sep 2021 | A1 |
20210280517 | May et al. | Sep 2021 | A1 |
20210280522 | Liu | Sep 2021 | A1 |
20210296282 | Gao et al. | Sep 2021 | A1 |
20210305122 | Lai et al. | Sep 2021 | A1 |
20210305202 | Uzoh et al. | Sep 2021 | A1 |
20210335726 | Wu et al. | Oct 2021 | A1 |
20210366820 | Uzoh | Nov 2021 | A1 |
20210366970 | Katkar | Nov 2021 | A1 |
20210375708 | Kuo et al. | Dec 2021 | A1 |
20210375737 | Lin | Dec 2021 | A1 |
20210384133 | Ong et al. | Dec 2021 | A1 |
20210384135 | Kuan et al. | Dec 2021 | A1 |
20210391271 | Hsu et al. | Dec 2021 | A1 |
20210391272 | Tsai et al. | Dec 2021 | A1 |
20210391283 | Hsu et al. | Dec 2021 | A1 |
20210391284 | Hsu et al. | Dec 2021 | A1 |
20210407941 | Haba | Dec 2021 | A1 |
20220005787 | Han et al. | Jan 2022 | A1 |
20220077063 | Haba | Mar 2022 | A1 |
20220122934 | Haba | Apr 2022 | A1 |
20220139867 | Uzoh | May 2022 | A1 |
20220139869 | Gao et al. | May 2022 | A1 |
20220208650 | Gao et al. | Jun 2022 | A1 |
20220208702 | Uzoh | Jun 2022 | A1 |
20220208723 | Katkar et al. | Jun 2022 | A1 |
20220246497 | Fountain, Jr. et al. | Aug 2022 | A1 |
20220278084 | Ong et al. | Sep 2022 | A1 |
20220285303 | Mirkarimi et al. | Sep 2022 | A1 |
20220319901 | Suwito et al. | Oct 2022 | A1 |
20220320035 | Uzoh et al. | Oct 2022 | A1 |
20220320036 | Gao et al. | Oct 2022 | A1 |
20220375864 | Wang et al. | Nov 2022 | A1 |
20230005850 | Fountain, Jr. | Jan 2023 | A1 |
Number | Date | Country |
---|---|---|
103681646 | Mar 2014 | CN |
1011133 | Jun 2000 | EP |
2 685 491 | Jan 2014 | EP |
04-337694 | Nov 1992 | JP |
2000-100679 | Apr 2000 | JP |
2001-102479 | Apr 2001 | JP |
2001-284520 | Oct 2001 | JP |
2002-353416 | Dec 2002 | JP |
2002-359345 | Dec 2002 | JP |
2004-193493 | Jul 2004 | JP |
2008-130603 | Jun 2008 | JP |
2011-171614 | Sep 2011 | JP |
2013-33786 | Feb 2013 | JP |
2018-160519 | Oct 2018 | JP |
10-2001-0104643 | Nov 2001 | KR |
10-2010-0123755 | Nov 2010 | KR |
10-2015-0097798 | Aug 2015 | KR |
10-2020-0092236 | Aug 2020 | KR |
WO 2005043584 | May 2005 | WO |
WO 2006100444 | Sep 2006 | WO |
WO 2008112101 | Sep 2008 | WO |
WO 2010024678 | Mar 2010 | WO |
WO 2017034654 | Mar 2017 | WO |
WO 2017052652 | Mar 2017 | WO |
WO 2017151442 | Sep 2017 | WO |
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---|
Braunisch, H. et al., “High-speed performance of silicon bridge die-to-die interconnects,” 2011 IEEE, pp. 95-98. |
NASA SBIR/STTR Technologies, Proposal No. 09-1 S5.05-9060—Reliable Direct Bond Copper Ceramic Packages for High Temperature Power Electronics, Contract No. NNX10CE23P, PI: Ender Savrun, PhD, Sienna Technologies, Inc.—Woodinville, WA, 1 page. |
“Photo Etching DBC for Power Circuits—Direct Bond Copper (DBC) on Ceramic Used for Power Circuits,” Conard Corporation, 2021, downloaded Nov. 9, 2021, https://www.conardcorp.com/photo-etching-dbc-for-power-circuits/, 2 pages. |
Urteaga, M. et al., “THz bandwidth InP HBT technologies and heterogeneous integration with Si CMOS,” 2016 IEEE Bipolar/BICMOS Circuits and Technology Meeting (BCTM), 2016, pp. 35-41, doi: 10.1109/BCTM.2016.7738973. |
International Search Report and Written Opinion dated Dec. 8, 2021, issued in International Application No. PCT/US2021/046753, 9 pages. |
Amirfeiz et al., “Formation of silicon structures by plasma-activated wafer bonding,” Journal of The Electrochemical Society, 2000, vol. 147, No. 7, pp. 2693-2698. |
Chung et al., “Room temperature GaAseu + Si and InPeu + Si wafer direct bonding by the surface activate bonding method,” Nuclear Instruments and Methods in Physics Research Section B: Beam Interactions with Materials and Atoms, Jan. 2, 1997, vol. 121, Issues 1-4, pp. 203-206. |
Chung et al., “Wafer direct bonding of compound semiconductors and silicon at room temperature by the surface activated bonding method,” Applied Surface Science, Jun. 2, 1997, vols. 117-118, pp. 808-812. |
Farrens et al., “Chemical free room temperature wafer to wafer direct bonding,” J. Electrochem. Soc., The Electrochemical Society, Inc., Nov. 1995, vol. 142, No. 11. pp. 3949-3955. |
Farrens et al., “Chemical free wafer bonding of silicon to glass and sapphire,” Electrochemical Society Proceedings vol. 95-7, 1995, pp. 72-77. |
Frumusanu, Andrei, “TSMC's version of EMIB is ‘LSI’: Currently in pre-qualification,” AnaandTech, https://www.anandtech.com/show/16031/tsmcs-version-of-emib-lsi-3dfabric, Aug. 25, 2020, 6 pages. |
Fukushima, T. et al., “New three-dimensional integration technology using self-assembly technique,” International Electron Devices Meeting 5-7.12.2005, IEEE, Dec. 5, 2005, pp. 348-351. |
Gösele et al., “Semiconductor Wafer Bonding: A flexible approach to materials combinations in microelectronics; micromechanics and optoelectronics,” IEEE, 1997, pp. 23-32. |
Hosoda et al., “Effect of the surface treatment on the room-temperature bonding of Al to Si and SiO2,” Journal of Materials Science, Jan. 1, 1998, vol. 33, Issue 1, pp. 253-258. |
Hosoda et al., “Room temperature GaAs—Si and InP—Si wafer direct bonding by the surface activated bonding method,” Nuclear Inst. And Methods in Physics Research B, 1997, vol. 121, Nos. 1-4, pp. 203-206. |
Howlader et al., “A novel method for bonding of ionic wafers,” Electronics Components and Technology Conference, 2006, IEEE, pp. 7-pp. |
Howlader et al., “Bonding of p-Si/n-InP wafers through surface activated bonding method at room temperature,” Indium Phosphide and Related Materials, 2001, IEEE International Conference On, pp. 272-275. |
Howlader et al., “Characterization of the bonding strength and interface current of p-Si/ n-InP wafers bonded by surface activated bonding method at room temperature,” Journal of Applied Physics, Mar. 1, 2002, vol. 91, No. 5, pp. 3062-3066. |
Howlader et al., “Investigation of the bonding strength and interface current of p-SionGaAs wafers bonded by surface activated bonding at room temperature,” J. Vac. Sci. Technol. B 19, Nov./Dec. 2001, pp. 2114-2118. |
International Search Report and Written Opinion dated Apr. 22, 2019 in International Application No. PCT/US2018/064982, 13 pages. |
International Search Report and Written Opinion dated Oct. 25, 2019, issued in International Application No. PCT/US2019/040622, 12 pages. |
Itoh et al., “Characteristics of fritting contacts utilized for micromachined wafer probe cards,” 2000 American Institute of Physics, AIP Review of Scientific Instruments, vol. 71, 2000, pp. 2224. |
Itoh et al., “Characteristics of low force contact process for MEMS probe cards,” Sensors and Actuators A: Physical, Apr. 1, 2002, vols. 97-98, pp. 462-467. |
Itoh et al., “Development of Mems Ic probe card utilizing fritting contact,” Initiatives of Precision Engineering at the Beginning of a Millennium: 10th International Conference on Precision Engineering (ICPE) Jul. 18-20, 2001, Yokohama, Japan, 2002, Book Part 1, pp. 314-318. |
Itoh et al., “Room temperature vacuum sealing using surface activated bonding method,” The 12th International Conference on Solid State Sensors, Actuators and Microsystems, Boston, Jun. 8-12, 2003, 2003 IEEE, pp. 1828-1831. |
Ker, Ming-Dou et al., “Fully process-compatible layout design on bond pad to improve wire bond reliability in CMOS les,” IEEE Transactions on Components and Packaging Technologies, Jun. 2002, vol. 25, No. 2, pp. 309-316. |
Kim et al., “Low temperature direct Cu—Cu bonding with low energy ion activation method,” Electronic Materials and Packaging, 2001, IEEE, pp. 193-195. |
Kim et al., “Room temperature Cu—Cu direct bonding using surface activated bonding method,” J. Vac. Sci. Technol., 2003 American Vacuum Society, Mar./Apr. 2003, vol. 21, No. 2, pp. 449-453. |
Kim et al., “Wafer-scale activated bonding of Cu—Cu, Cu—Si, and Cu—SiO2 at low temperature,” Proceedings—Electrochemical Society, 2003, vol. 19, pp. 239-247. |
Matsuzawa et al., “Room-temperature interconnection of electroplated Au microbump by means of surface activated bonding method,” Electornic Components and Technology Confererence, 2001, 51st Proceedings, IEEE, pp. 384-387. |
Moriceau, H. et al., “Overview of recent direct wafer bonding advances and applications,” Advances in Natural Sciences-Nanoscience and Nanotechnology, 2010, 11 pages. |
Nakanishi, H. et al., “Studies on SiO2—SiO2 bonding with hydrofluoric acid. Room temperature and low stress bonding technique for MEMS,” Sensors and Actuators, 2000, vol. 79, pp. 237-244. |
Oberhammer, J. et al., “Sealing of adhesive bonded devices on wafer level,” Sensors and Actuators A, 2004, vol. 110, No. 1 -3, pp. 407-412, see pp. 407-412, and Figures 1 (a)-1(I), 6 pages. |
Onodera et al., “The effect of prebonding heat treatment on the separability of Au wire from Ag-plated Cu alloy substrate,” Electronics Packaging Manufacturing, IEEE Transactions, Jan. 2002, vol. 25, Issue 1, pp. 5-12. |
Plobi, A. et al., “Wafer direct bonding: tailoring adhesion between brittle materials,” Materials Science and Engineering Review Journal, 1999, R25, 88 pages. |
Reiche et al., “The effect of a plasma pretreatment on the Si/Si bonding behaviouir,” Electrochemical Society Proceedings, 1998, vol. 97-36, pp. 437-444. |
Roberds et al., “Low temperature , in situ, plasma activated wafer bonding,” Electrochecmical Society Proceedings, 1997, vol. 97-36, pp. 598-606. |
Shigetou et al., “Room temperature bonding of ultra-fine pitch and low-profiled Cu electrodes for bump-less interconnect,” 2003 Electronic Components and Technology Conference, pp. 848-852. |
Shigetou et al., “Room-temperature direct bonding of CMP-Cu film for bumpless interconnection,” Electronic Components and Technology Confererence, 51st Proceedings, 2001, IEEE, pp. 755-760. |
Shingo et al., “Design and fabrication of an electrostatically actuated MEMS probe card,” TRANDUCERS, Solid-State Sensors, Actuators and Microsystems, 12th International Conference, Jun. 8-12, 2003, vol. 2, pp. 1522-1525. |
Suga et al., “A new approach to Cu—Cu direct bump bonding,” IEMT/IMC Symposium, 1997, Joint International Electronic Manufacturing Symposium and the International Microelectronics Conference, Apr. 16-18, 1997, IEEE, pp. 146-151. |
Suga et al., “A new bumping process using lead-free solder paste,” Electronics Packaging Manufacturing, IEEE Transactions on (vol. 25, Issue 4), IEEE, Oct. 2002, pp. 253-256. |
Suga et al., “A new wafer-bonder of ultra-high precision using surface activated bonding (SAB) concept,” Electronic Components and Technology Conference, 2001, IEEE, pp. 1013-1018. |
Suga et al., “Bump-less interconnect for next generation system packaging,” Electronic Components and Technology Conference, 2001, IEEE, pp. 1003-1008. |
Suga, T., “Feasibility of surface activated bonding for ultra-fine pitch interconnection—A new concept of bump-less direct bonding for system level packaging,” The University of Tokyo, Research Center for Science and Technology, 2000 Electronic Components and Technology Conference, 2000 IEEE, pp. 702-705. |
Suga, T., “Room-temperature bonding on metals and ceramics,” Proceedings of the Second International Symposium on Semiconductor Wafer Bonding: Science, Technology and Applications, The Electrochemical Society Proceedings, vol. 93-29 (1993), pp. 71-80. |
Suga et al., “Surface activated bonding—an approach to joining at room temperature,” Ceramic Transactions: Structural Ceramics Joining II, The American Ceramic Society, 1993, pp. 323-331. |
Suga et al., “Surface activated bonding for new flip chip and bumpless interconnect systems,” Electronic Components and Technology Conference, 2002, IEEE, pp. 105-111. |
Suga, “UHV room temperature joining by the surface activated bonding method,” Advances in science and technology, Techna, Faenza, Italie, 1999, pp. C1079-C1089. |
Takagi et al., “Effect of surface roughness on room-temperature wafer bonding by Ar beam surface activation,” Japanese Journal of Applied Physics, 1998, vol. 37, Part 1, No. 1, pp. 4197. |
Takagi et al., “Low temperature direct bonding of silicon and silicon dioxide by the surface activation method,” Solid State Sensors and Actuators, 1997, TRANSDUCERS '97 Chicago, 1997 International Conference, vol. 1, pp. 657-660. |
Takagi et al., “Room-temperature bonding of lithium niobate and silicon wafers by argon-beam surface activation,” Appl. Phys. Lett., 1999. vol. 74, pp. 2387. |
Takagi et al., “Room temperature silicon wafer direct bonding in vacuum by Ar beam irradiation,” Micro Electro Mehcanical Systems, MEMS '97 Proceedings, 1997, IEEE, pp. 191-196. |
Takagi et al., “Room-temperature wafer bonding of Si to LiNbO3, LiTaO3 and Gd3Ga5O12 by Ar-beam surface activation,” Journal of Micromechanics and Microengineering, 2001, vol. 11, No. 4, pp. 348. |
Takagi et al., “Room-temperature wafer bonding of silicon and lithium niobate by means of arbon-beam surface activation,” Integrated Ferroelectrics: An International Journal, 2002, vol. 50, Issue 1, pp. 53-59. |
Takagi et al., “Surface activated bonding silicon wafers at room temperature,” Appl. Phys. Lett. 68, 2222 (1996). |
Takagi et al., “Wafer-scale room-temperature bonding between silicon and ceramic wafers by means of argon-beam surface activation,” Micro Electro Mechanical Systems, 2001, MEMS 2001, The 14th IEEE International Conference, Jan. 25, 2001, IEEE, pp. 60-63. |
Takagi et al., “Wafer-scale spontaneous bonding of silicon wafers by argon-beam surface activation at room temperature,” Sensors and Actuators A: Physical, Jun. 15, 2003, vol. 105, Issue 1, pp. 98-102. |
Tong et al., “Low temperature wafer direct bonding,” Journal of Microelectomechanical systems, Mar. 1994, vol. 3, No. 1, pp. 29-35. |
Topol et al., “Enabling technologies for wafer-level bonding of 3D Mems and integrated circuit structures,” 2004 Electronics Components and Technology Conference, 2004 IEEE, pp. 931-938. |
Uhrmann, T. et al., “Heterogeneous integration by collective die-to-wafer bonding,” Chip Scale Review, Nov./Dec. 2018, vol. 22, No. 6, pp. 10-12. |
Wang et al., “Reliability and microstructure of Au—Al and Au—Cu direct bonding fabricated by the Surface Activated Bonding,” Electronic Components and Technology Conference, 2002, IEEE, pp. 915-919. |
Wang et al., “Reliability of Au bump—Cu direct interconnections fabricated by means of surface activated bonding method,” Microelectronics Reliability, May 2003, vol. 43, Issue 5, pp. 751-756. |
Weldon et al., “Physics and chemistry of silicon wafer bonding investigated by infrared absorption spectroscopy,” Journal of Vacuum Science & Technology B, Jul./Aug. 1996, vol. 14, No. 4, pp. 3095-3106. |
Xu et al., “New Au—Al interconnect technology and its reliability by surface activated bonding,” Electronic Packaging Technology Proceedings, Oct. 28-30, 2003, Shanghai, China, pp. 479-483. |
Ceramic Microstructures: Control at the Atomic Level, Recent Progress in Surface Activated Bonding, 1998, pp. 385-389. |
Number | Date | Country | |
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20220077087 A1 | Mar 2022 | US |
Number | Date | Country | |
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63074928 | Sep 2020 | US |