The present application is based on, and claims priority from, Korean Application Numbers 10-2007-0050202 filed May 23, 2007, the disclosure of which is incorporated herein by reference in its entirety.
The following description relates generally to a chip embedded printed circuit board and a fabricating method thereof.
As electronic products are being made smaller and lighter, represented by the trends of smaller, thinner, higher-density, packaged, and portable products, so also is the multilayer printed circuit board (PCB) undergoing a trend towards finer patterns and smaller and packaged products. Accordingly, along with changes in the raw materials for forming fine patterns on the multilayer printed circuit board (PCB) and for improving reliability and design density (the number of chips mounted on a single circuit board or substrate), there is a change towards integrating the layer composition of circuits. Components are also undergoing a change from DIP (dual in-line package) types to SMT (surface mount technology) types, so that the mounting density is also being increased.
Generally, a method of packaging semiconductor chips on PCBs may include one or more of the following features. For example, a semiconductor chip may be stacked on the PCB, bonded and connected by a metal wire, or connected to the PCB using a flip chip bump.
Meanwhile, as functionality required by the electronic devices increases, an increased number of functional chips must be packaged on a limited space (or “real estate”) of the PCB, and this demand may suffer from a problem of causing the fabricated chip modules to be bulky as the thickness of the PCB is increased by thickness of semiconductor chips packaged to the PCB.
Flip chip PCBs are typically constructed with a 4-layer {1+2 (core)+1} structure or a 6-layer {2+2 (core)+2} structure. Usually, flip chip packaging places a high importance on flatness of substrate, such that thickness of a substrate for a core layer is approximately 400 μm. A semiconductor chip may be two dimensionally packaged on a surface of the PCB to have shocks on surroundings thereof and to create cracks on semiconductor chips due to differences of coefficient of thermal expansion with the PCB.
To solve or obviate these problems, chip embedded PCB technology has been researched where the semiconductor chips are embedded inside the PCB for integration there between. However, such embedding techniques bring about the following problems.
A fabricating method for chip embedded printed circuit board according to the present disclosure comprises: forming a circuit pattern on a support layer; packaging a high temperature fired high permittivity material on the support layer; packaging a semiconductor chip on the support layer, wrapping the semiconductor chip and forming an insulation layer; drilling the insulation layer for electrical connection to form a via hole; and selectively removing part of the support layer and using as a plated heat sink. According to the present inventive disclosure, a support layer of a sufficient thickness is used to enable a packaging process on a planar state, and the radiation plate may be integrally formed with the printed circuit board.
a to 1h are cross-sectional views illustrating a fabricating method of chip embedded printed circuit board.
a and 2b are schematic views illustrating forming a radiation plate following anodizing treatment of a support layer.
a to 3e are schematic views illustrating a fabricating method of chip embedded printed circuit board according to another exemplary implementation.
a, 5b and 5c are cross-sectional views illustrating a fabricating method of chip embedded printed circuit board according to still another exemplary implementation.
Now, exemplary implementations of the present inventive disclosure will be described in detail with reference to the accompanying drawings.
a to 1h are cross-sectional views illustrating a fabricating method of chip embedded printed circuit board.
Referring to
The support layer (100) preferably has a sufficient thickness of 500 μm˜2000 μm for providing a planar state in the fabricating method of chip embedded printed circuit board, and the first metal layer (110) is formed on the support layer (100) by deposition process or plating process.
Next, photolithography process is used to form a first bonding pad (113) and a first circuit pattern (115) on the support layer (100) (
Furthermore, part of the first circuit pattern (115) may be deposited with high temperature fired (high temperature of 300° C. or more, mainly 300° C.˜1000° C.) permittivity material, and fired at a high temperature, and additionally formed with a metal layer to thereby embed a capacitor element inside the PCB.
As noted above, the high temperature fired permittivity material may be deposited using the metal support layer (100) instead of polymer-based substrate to easily treat the high permittivity material during co-firing and to prevent bending from occurring due to differences of coefficient of heat expansion with the high permittivity material.
Successively, a first semiconductor chip (120) is bonded to an upper surface of the first bonding pad (113) using flip-chip bonding method (
Although an implementation using flip-chip bonding method for packaging the first semiconductor chip (120) onto the support layer (100) has been exemplified, other various methods such as, for example, wire bonding method and ACF (Anisotrofic Conductive Film) method may be employed.
Successively, the first circuit pattern (115) and the first semiconductor chip (120) on the support layer (100) may be wrapped to form a first isolation layer (130), and a second metal layer (140) is formed on the first isolation layer (130) (
The first isolation layer (130) is typically formed of a half-hardened prepreg, and the prepreg is typically made of glass fiber hardened by a predetermined heat and pressure and thermosetting resin.
A cavity may be formed about the first semiconductor chip (120) in order to prevent the first semiconductor chip (120) from being damaged when the first isolation layer (130) and the second metal layer (140) are stacked.
Next, a first via hole (150) is formed on the first circuit pattern (115) and a first plating layer (155) is formed on an inner wall of the first via hole (150) (
Successively, a second bonding pad (143) and a second circuit pattern (145) may be formed on the first isolation layer (130) using the photolithographic process, and a second semiconductor chip (160) may be packaged using the flip-chip bonding method, a second isolation layer (170) and a third metal layer (180) are sequentially stacked on the first isolation layer (130), and a second via hole (190) and a second plating layer (195) are formed on the second circuit pattern (145) (
In other words, the processes from
Now, a third bonding pad (183) and a third circuit pattern (185) are formed on the second isolation layer (170) using photolithographic process part of the support layer (100) is selectively removed to form a plated heat sink (200) (
In other words, a portion formed at a bottom surface of the first semiconductor chip (120) in the support layer (100) is left, while other remaining portions are removed to form the plated heat sink (200) underneath the first semiconductor chip (120). The integral formation of a plated heat sink with the PCB can dispense with an additive between the PCB and the plated heat sink to improve the heat dissipation characteristic, to make the process of separately bonding the plated heat sink unnecessary, and to thereby simplify the fabricating process.
Thereafter, a solder ball (210) is bonded onto the third bonding pad (183) for electrically connecting with the outside (
Meanwhile, in case aluminum is used for the support layer (100) in the forming process of the plated heat sink in
Referring to
Successively, when the remaining photo-resist (205) may be removed to etch the support layer (100) with aluminum etching solution, only an Al2O3 layer may remain to function as the heat sink (200) (
Although only the portion underneath the first semiconductor chip (120) in the support layer (100) may be anodized in the present exemplary implementation, an entire support layer (100) may be anodized for use as a heat sink.
According to the instant inventive concept, semiconductor chips may be embedded inside the PCBs up to a desired layer using a support layer, and the support layer may be selectively etched for use as a plated heat sink, thereby enabling to integrally form the plated heat sink with the PCB. Furthermore, a very planar packaging process may be performed due to sufficiently thick support layer, such that there is no need of a thick core layer like that of the conventional flip chip PCB.
a to 3e are schematic views illustrating a fabricating method of chip embedded printed circuit board according to another exemplary implementation.
Now, referring to
Successively, a first circuit pattern (315) may be formed on the support layer (300) using the photolithographic process, a high temperature fired high permittivity material may be deposited on part of the first circuit pattern (315) and fired at a high temperature to form a capacitor element (
Thereafter, the first circuit pattern (315) and the capacitor element (317) on the support layer (300) may be wrapped to sequentially form a first isolation layer (320) and a second metal layer (330) via a thermal lamination, a first via hole (340) may be formed on the first circuit pattern (315) and the capacitor element (317), and a first plating layer (345) may be formed inside the first via hole (340) (
Successively, a second circuit pattern (335) and a bonding pad (333) may be formed on the first isolation layer (320) using the photolithographic process (
Thereafter, part of the support layer (300) may be selectively etched for use as a plated heat sink to integrally form the PCB with the plated heat sink.
The present implementation has shown a case where semiconductor chips are packaged from a second layer instead of a first layer in a multilayer PCB, and besides this implementation, other various methods may be employed to package the semiconductor chips.
Meanwhile, in
In other words, as shown in
a, 5b and 5c are cross-sectional views illustrating a fabricating method of chip embedded printed circuit board according to still another exemplary implementation.
Referring to
First, a support layer (400) may be formed thereon with a circuit pattern (415) and a semiconductor chip (420) may be bonded to the circuit pattern (415) using epoxy (425) (
Next, the first circuit pattern (415) and the semiconductor chip (420) on the support layer (400) may be wrapped to form an isolation layer (430), and a second metal layer (440) may be formed on the isolation layer (430) (
Successively, a via hole (450) may be formed on a circuit pattern (not shown) on the circuit pattern (415) and the semiconductor chip (420) of the support layer (400), and a plating layer (455) may be formed at an inner wall of the via hole (450) to electrically connect the semiconductor chip (420) to the PCB (
Referring to
The support layer (500) functions as a plated heat sink for discharging outside the heat generated by the semiconductor chip (520). The support layer (500) therefore may be comprised of any one of the conductivity excellent metals consisting of, for example, Al, Au and Ag. The support layer (500) preferably has a thickness in the range of 500 μm˜2000 μm and may be formed underneath the semiconductor chip (520).
Furthermore, the support layer (500) may be further formed thereon with a capacitor made of high temperature fired high permittivity material, and may be further formed with a solder ball on the second circuit pattern (545).
Referring to
As apparent from the foregoing, a sufficiently thick support layer can be employed to perform a packaging process on a planar state to stably treat a PCB during fabrication process. A semiconductor chip can be embedded inside the PCB to a desired layer using the support layer, and the support layer can be selectively etched for use as a plated heat sink to integrate the plated heat sink to the PCB.
Furthermore, a metal support layer instead of polymer-based substrate can be used to deposit a high temperature fired high permittivity material, such that the high temperature fired high permittivity material can be easily treated to thereby prevent a bending from generating due to differences of heat expansion coefficient with the high permittivity material.
Still furthermore, a plated heat sink can be integrally formed with the PCB, and there is no need of additive between the PCB and the plated heat sink to enable to enhance the heat dissipation feature, and as no separate process of bonding the plated heat sink is needed to enable to simplify the manufacturing process.
As the present disclosure may be embodied in several forms without departing from the spirit or essential characteristics thereof it should also be understood that the above-described implementations are not limited by any of the details of the foregoing description, unless otherwise specified, but rather should be construed broadly within its spirit and scope as defined in the appended claims, and therefore it will be understood by those of ordinary skill in the art that all changes and modifications that fall within the metes and bounds of the claims, or equivalents of such metes and bounds are therefore intended to be embraced by the appended claims.
Number | Date | Country | Kind |
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10-2007-0050202 | May 2007 | KR | national |