Circuit structure having islands between source and drain and circuit formed

Abstract

A method of making a circuit structure includes growing a bulk layer over a substrate, and growing a donor-supply layer over the bulk layer. The method further includes depositing a doped layer over the donor-supply layer, and patterning the doped layer to form a plurality of islands. The method further includes forming a gate structure over the donor-supply layer, wherein the gate structure is partially over a largest island of the plurality of islands. The method further includes forming a drain over the donor-supply layer, wherein at least one island of the plurality of islands is between the gate structure and the drain.

Description

TECHNICAL FIELD

This disclosure relates generally to semiconductor circuit manufacturing processes and, more particularly, to a group-III group-V (III-V) compound semiconductor based transistor.

BACKGROUND

Group-III group-V compound semiconductors (often referred to as III-V compound semiconductors), such as gallium nitride (GaN) and its related alloys, have been under intense research in recent years due to their promising applications in power electronic and optoelectronic devices. The large band gap and high electron saturation velocity of many III-V compound semiconductors also make them excellent candidates for applications in high temperature, high voltage, and high-speed power electronics. Particular examples of potential electronic devices employing III-V compound semiconductors include high electron mobility transistor (HEMT) and other heterojunction bipolar transistors.

During operation, a HEMT forms a large surface electric field around the gate edge, which affects the depletion region curve between the gate structure and the drain. While large electric field is one of the benefits of HEMT for use in power applications, the distribution of the depletion region during operation can negatively affect the breakdown voltage for the device. When negative bias is applied to the gate of the HEMT, depletion region curve is formed directly under the gate and causes high surface electric field around the gate edge. The high electric field concentration around the gate reduces breakdown voltage for the device.

In order to improve breakdown voltage (i.e., to increase it), a metallic field plate is sometimes added over or next to the gate structure over the passivation layer between the gate structure and the drain. The field plate modulates the surface electric field distribution reducing the peak electric field, and thus increases the breakdown voltage. However, new structures with high breakdown voltage for III-V compound semiconductor based transistors and methods for forming them continue to be sought.

BRIEF DESCRIPTION OF THE DRAWINGS

For a more complete understanding of the present disclosure, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:

FIG. 1A is a cross sectional view of a high electron mobility transistor (HEMT) structure in accordance with various embodiments of the present disclosure.

FIG. 1B is a flow chart of a method of forming a HEMT structure in accordance with certain embodiments according to FIG. 1A of the present disclosure.

FIGS. 2A, 2B, 2C, 2D, and 2E are top views of a HEMT structure in accordance with various embodiments of the present disclosure.

FIGS. 3A, 3B, and 3C are cross-sectional views of a HEMT depletion regions under different operating conditions.

FIGS. 4A, 4B, and 4C are cross-sectional views of a HEMT depletion regions in accordance with various embodiments of the present disclosure under different operating conditions.

FIG. 5 is a plot of simulated peak surface electric field as a function of distance on the HEMT structures in accordance with various embodiments of the present disclosure.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

The making and using of the present embodiments are discussed in detail below. It should be appreciated, however, that the present disclosure provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are illustrative of specific ways to make and use the disclosed embodiments and do not limit the scope of the disclosure.

A novel structure for group-III to group-V (referred to as III-V hereinafter) semiconductor based transistors and methods for forming the structures are provided. Throughout the description, the term “III-V compound semiconductor” refers to compound semiconductor materials comprising at least one group III element and one group-V element. The term “III-N compound semiconductor” refers to a III-V compound semiconductor in which the group V element is nitrogen. Example stages of manufacturing an illustrative embodiment of the present disclosure are discussed. Those skilled in the art will recognize that other manufacturing steps may take place before or after the described stages in order to produce a complete device. Other stages of manufacturing that may substitute some of the example stages may be discussed. Those skilled in the art will recognize that other substitute stages or procedures may be used. Throughout the various views and illustrative embodiments of the present disclosure, like reference numbers are used to designate like elements.

The present disclosure provides a structure and a method to form III-V compound semiconductor based transistors having high breakdown voltage. FIG. 1A shows an example power transistor device 100 according to various embodiments of the present disclosure. The power transistor 100 may be a high-electron mobility transistor (HEMT). The HEMT includes a substrate 101, a bulk layer GaN layer 109 over the substrate 101, an active layer 111 over the bulk GaN layer 109, and source 115, drain 117, and gate 119 over the active layer 111. An interface of active layer 111 and bulk GaN layer 109 is a high-electron mobility region 113, also known as a channel layer. In a drift region 107 between the gate 119 and the drain 117, a number of islands 103 and 105 are formed over the active layer. Each of these transistor elements are discussed further below together with methods for forming them.

FIG. 1B shows a flowchart 150 of a method of making the power transistor device 100 of FIG. 1A. In operation 151, a substrate 101 is provided, as shown in FIG. 1A. Although silicon wafers are used, other suitable substrates include silicon carbide and sapphire. A number of layers are grown over the substrate 101 using an epitaxial process. The layers may include a nucleation layer of aluminum nitride, a buffer, and a bulk gallium nitride layer 109 grown over the buffer layer. The bulk gallium nitride layer 109 is a channel layer for the power transistor device 100.

The bulk layer of undoped gallium nitride 109 is epitaxially grown over the substrate, which may include a buffer layer (not shown) in operation 153 of FIG. 1B. The bulk layer of gallium nitride 109 does not include any dopant, but may include contaminants or impurities that are incorporated in the film unintentionally. The bulk layer of gallium nitride may be referred to as unintentionally doped gallium nitride (UID GaN) layer. The UID GaN layer is about 0.5 microns to about 5 micron thick. The bulk GaN layer is grown under high temperature conditions. The process may be metal organic CVD (MOCVD), metal organic vapor phase epitaxy (MOVPE), plasma enhanced CVD (PECVD), remote plasma enhanced CVD (RP-CVD), molecular beam epitaxy (MBE), hydride vapor phase epitaxy (HVPE), chloride vapor-phase epitaxy (Cl-VPE), and liquid phase epitaxy (LPE). The metal organic vapor phase epitaxy (MOVPE) process uses gallium-containing precursor and nitrogen-containing precursor. The gallium-containing precursor includes trimethylgallium (TMG), triethylgallium (TEG), or other suitable chemical. The nitrogen-containing precursor includes ammonia (NH₃), trimethylalaluminum (TMA), phenyl hydrazine, or other suitable chemical.

FIG. 1A shows an active layer 111 on top of the bulk GaN layer 109. The active layer 111, also referred to as donor-supply layer, is grown on the channel layer 109 in operation 155 of FIG. 1B. An interface is defined between the channel layer 109 and the donor-supply layer 111. A carrier channel 113 of two-dimensional electron gas (2-DEG) is located at the interface, which is discussed in further detail below. In at least one embodiment, the donor-supply 111 refers to an aluminum gallium nitride (AlGaN) layer (also referred to as the AlGaN layer 111). The AlGaN layer 111 has a formula of Al_xGa_(1-x)N. It has a thickness in a range from about 5 nanometers to about 50 nanometers, wherein x varies between about between about 10% to 100%. In other embodiments, the donor-supply layer 111 may include an AlGaAs layer or AlInP layer.

The AlGaN layer 111 can be epitaxially grown on the GaN layer 109 in operation 155 of FIG. 1B by MOVPE using an aluminum-containing precursor, a gallium-containing precursor, and/or a nitrogen-containing precursor. The aluminum-containing precursor includes Tri-Methyl AluminumTMA, triethyl Aluminum (TEA), or other suitable chemical. The gallium-containing precursor includes Trimethyl Gallium TMG, Triethyl Gallium TEG, or other suitable chemical. The nitrogen-containing precursor includes ammonia, tertiarybutylamine (TBAm), phenyl hydrazine, or other suitable chemical.

Referring back to FIG. 1A, a band gap discontinuity exists between the AlGaN layer 111 and the GaN layer 109. The electrons from a piezoelectric effect in the AlGaN layer 111 drop into the GaN layer 109, creating a very thin layer 113 of highly mobile conducting electrons in the GaN layer 109. This thin layer 113 is referred to as a two-dimensional electron gas (2-DEG), forming a carrier channel (also referred to as the carrier channel 113). The thin layer 113 of 2-DEG is located at an interface of the AlGaN layer 111 and the GaN layer 109. Thus, the carrier channel has high electron mobility because the GaN layer 109 is undoped or unintentionally doped, and the electrons can move freely without collision or substantially reduced collision with the impurities.

According to various embodiments of the present disclosure, a gate structure 119 partially overlaps one or more islands 103 formed over the AlGaN layer 111 between the gate structure 119 and a drain 117 or at least adjoins at least a portion of one of the islands. The region between the gate structure 119 and the drain 117 is the drift region 107 on which the islands 103 and 105 are formed. The islands 103 and 105 are formed before the gate structure 119 but may be formed before or after a source 115 and drain 117.

In certain embodiments, a portion of the gate structure 119 overlaps a part of the one or more islands 103, as shown in FIG. 1A. In other embodiments, the gate structure 119 covers the entirety of the one or more islands 103 while a portion of the bottom of the gate structure 119 does not contact the one or more islands. In other words, the gate structure 119, the one or more islands 103, or both can partially overlap the other. In still other embodiments, the gate structure 119 adjoins a portion of one or more of the islands without overlapping each other.

According to certain embodiments, the islands 103 and 105 are p-type doped islands. Referring to FIG. 1B, in operation 157 a p-type doped GaN film is grown epitaxially over the AlGaN layer 111. The islands may be p-type doped gallium nitride or aluminum gallium nitride islands. The p-type doping may occur by adding a dopant during the epitaxial growth process. P-type dopant candidates include carbon, iron, magnesium, calcium, beryllium, and zinc. The p-type doping may also be performed by other processes such as ion implantation; however, care must be taken not to incorporate the dopant in underlying layers, which may adversely affect the electrical property of the transistor. The dopant concentration may be about from 1E15/cm³ to 1E17/cm³.

In other examples, the islands 103 and 105 may also be deposited, for example, using a metal chemical vapor deposition (MCVD) process or a sputtering process, and defined on the AlGaN layer 111. The islands may be p-type doped nickel oxide or zinc oxide. The p-type doping may occur by adding a dopant during the deposition process. P-type dopant candidates include carbon, iron, magnesium, calcium, beryllium, and zinc. The p-type doping may also be performed by other processes such as ion implantation; however, care must be taken not to incorporate the dopant in underlying layers, which may adversely affect the electrical property of the transistor. Note that while the dopant candidates may be the same for the epitaxially grown islands and the deposited islands, but the chemicals used may be different. The dopant concentration may be from about 1E15/cm³ to 1E17/cm³.

Referring to FIG. 1B, the p-type doped film is deposited in operation 157. Thereafter, a photolithographic process is employed to protect the island portions of the p-type doped film. The p-type doped film is etched into islands in operation 159. In at least one embodiment, a plasma etch process is used to removed unwanted portions of the p-type doped film. In one example, the plasma etch process is a reactive ion etch process employing chlorine containing etchants. In some embodiments, care is taken to not overetch into the donor-supply layer 111.

The light p-type doping of the islands creates p-n junctions at the AlGaN layer 111 surface. During operation, the p-n junctions modulate the surface electric field and reduce effective peak electric field at the gate edge. The lower peak electric field results in a higher breakdown voltage.

According to some embodiments, the islands 103 and 105 are formed of Schottky materials, such as titanium, tungsten, titanium nitride, or titanium tungsten. Other Schottky materials may include nickel, gold, or copper. These materials may be deposited using physical vapor deposition (PVD) processes such as sputtering or electron gun, or using MCVD processes. The materials may be deposited first and then unwanted parts are defined and etched away or are deposited over defined film such as a photoresist and then unwanted parts lifted off with the defined film.

A thickness of the islands 103 and 105 may be about 3 nm to about 100 nm. In some cases, the thickness of the islands 103 and 105 may be about 10 nm or be about 20 nm. The thickness of the islands 103 and 105 depends on the electrical properties and the physical dimensions of the semiconductor structure 100. For example, thin islands 103 and 105 may be used when the bulk gallium nitride layer 109 is thick and the drift region 107 is very large as compared to the region between the gate structure 119 and the source 115. In these circumstances, the breakdown voltage is naturally high and little modulation of the surface electric field may be sufficient for reaching a predetermined breakdown voltage. On the other hand, when the bulk gallium nitride layer 109 is thin or when the bulk layer is of a material with a low critical electrical field (Ec) value, the island 103 and 105 may be thicker. During operation when the drain is subjected to a high voltage, the depletion region formed may extend past a thin gallium nitride layer 109 and interact with the underlying substrate. Similar rationale applies when the distance between the gate structure 119 and the drain 117 is small. During operation when the drain is subjected to a high voltage, the depletion region curve may extend past a short drift region 107. Thus thicker islands 103 and 105 may be used to effectively modulate the surface electrical field. According to various embodiments, island thickness between about 3 nm to 100 nm and a drift region that is at least half the size of the device, i.e., half of the donor-supply layer, form a HEMT with good breakdown voltage at or over 600 volts.

The source 115, drain 117, and gate structures 119 are formed in operation 161 of FIG. 1B. The source feature 115 and a drain feature 117 are disposed on the AlGaN layer 111 and configured to electrically connect to the carrier channel 113. Each of the source feature 115 and the drain feature 117 comprises a corresponding intermetallic compound. The intermetallic compound is at least partially embedded in the AlGaN layer 111 and may be embedded in a top portion of the GaN layer 109. In one example, the intermetallic compound comprises Al, Ti, or Cu. In another example, the intermetallic compound comprises AlN, TiN, Al₃Ti or AlTi₁N.

The intermetallic compound may be formed by constructing a patterned metal layer in a recess of the AlGaN layer 111. Then, a thermal annealing process may be applied to the patterned metal layer such that the metal layer, the AlGaN layer 111 and the GaN layer 109 react to form the intermetallic compound. The intermetallic compound contacts the carrier channel 113 located at the interface of the AlGaN layer 111 and the GaN layer 109. Due to the formation of the recess in AlGaN layer 111, the metal elements in the intermetallic compound may diffuse deeper into the AlGaN layer 111 and the GaN layer 109. The intermetallic compound may improve electrical connection and form ohmic contacts between the source/drain features 115 or 117 and the carrier channel 113. In one example, the intermetallic compound is formed in the recess of the AlGaN layer 111 thereby the intermetallic compound has a non-flat top surface. In another example, intermetallic compound overlies a portion of the AlGaN layer 111.

The semiconductor structure 100 also includes a gate structure 119 disposed on the AlGaN layer 111 between the source 115 and drain 117 features. The gate 119 includes a conductive material layer which functions as the gate electrode configured for voltage bias and electrical coupling with the carrier channel 113. In various examples, the conductive material layer may include a refractory metal or its compounds, e.g., tungsten (W), titanium nitride (TiN) and tantalum (Ta). Other commonly used metals in the conductive material layer include nickel (Ni) and gold (Au). The gate structure may include one or many layers.

FIGS. 2A to 2D are example top views of various islands in accordance with various embodiments of the present disclosure. FIG. 2A shows a total of four islands 203 and 205 in the drift region, between source 215 and drain 217, with island 203 being partially covered by the gate 219. The edge of island 203 covered by the gate structure 219 is shown as a dotted line. As shown in FIG. 2A, three islands 205 are dispersed between the island 203 and drain 217, although fewer or more islands may be used.

FIGS. 2A to 2D are example top views of various islands in accordance with various embodiments of the present disclosure. FIG. 2A shows a total of four islands 203 and 205 in the drift region with island 203 being partially covered by the gate 219. The edge of island 203 covered by the gate structure 219 is shown as a dotted line. As shown in FIG. 2A, three islands 205 are dispersed between the island 203 and drain 217, although fewer or more islands may be used.

In FIG. 2A, the first island 203 that is partially under the gate structure 219 is the largest island. Islands 205 have the same size. Each island has a width. Island 203 has a width 221. Islands 205 have widths 223. The distance between island 203 and the adjacent island 205 is distance 222. The distances between the islands 205 are distances 224. Finally, a distance between the drain 217 and adjacent island 205 is distance 225. Adequate distance 225 must be maintained to ensure isolation of the drain 217 from an adjacent island 205.

According to certain embodiments, a largest of the islands 203 and 205 is partially disposed under the gate structure 119. While not required for the present disclosure to reduce breakdown voltage of the transistor 100, the island material has the largest effect to modulate surface electric field at the gate edge. Thus, embodiments having larger islands at least partially under the gate structure 119 results in greater reductions of breakdown voltages.

In some embodiments, the islands 203 and 205 are the same sizes and may be equally spaced. In some examples, the widths of adjacent island and drift region 207 not occupied by an island may be between about 3:1 to about 1:3. For example, a ratio of distance 221 to distance 222 may be about 3:1, while a ratio of distance 222 to distance 223 may be about 1:2. A ratio of distance 223 to distance 224 may be about 1:1.

In other embodiments, a sum of total island widths may be compared to the total drift region 207 width. A total island width may be about 40% to about 75% of the total drift region 207 width. In other words a sum of widths 221 and 223s may be compared to the total width of the drift region 207.

In yet other embodiments, a total island area is compared to the drift region area. In FIG. 2A, the features all have the same length so that the widths are a proxy for area. However, the islands need not have same lengths, shapes or sizes. A total island area may be about 40% to about 75% of the total drift region area.

FIG. 2B shows checkered pattern islands 203 and 205 as another example. The islands 203 are again larger than islands 205 (width 221 is larger than width 223), but not all of the gate structure edge overlaps an island 203. This design may be used to smooth the surface electric field. A ratio of an island and adjacent drift region (such as 221/222 or 223/222) that is not occupied by an island may be about 3:1 to about 1:3. Thus, the checkers need not be the same size. As shown in FIG. 2B, the ratio is about 1:1.

FIG. 2C shows trapezoidal islands 203 and 205 as another example. The trapezoidal islands 203 and 205 have a shorter width, such as width 220, and a longer width, such as width 221. The gate structure edge overlaps a portion of the trapezoidal island 203.

FIG. 2D shows an irregular island distribution. The various islands 229 and 231 are all differently shaped and may be irregularly shaped. In this example the overall island area, shown as cross hatched regions, is compared to the total drift region area. A total island area may be about 40% to about 75% of the total drift region area. Another comparison is the total island area, shown as cross hatched regions, to the drift region that is not occupied by an island, shown as hatched regions. This ratio may be about 30% to about 300%.

FIG. 2E shows yet another example where the islands 203 and 205 have different shapes. Island 203 adjoins the gate structure 219 without overlapping each other. In other words, no part of island 203 is under a portion of the gate structure 219. Islands 203 and 205 are located within drift region 207, which starts at the gate structure edge. With non-overlapping embodiments, the width 221 of the adjoining island 203 may be larger to have the same effect as the “disposed under” island 203 of FIGS. 2A to 2D.

The various islands shown in FIGS. 2A to 2D are merely examples. The islands may be polygons, such as quadrilaterals such as those in FIGS. 2A, 2B, and 2C. The islands may have more than four sides or may be circular or irregular, such as those in FIG. 2D.

FIGS. 3A to 3C are cross-sectional views of a HEMT structure and depletion regions formed during various operations for an III-V semiconductor material based transistor without the islands of the present disclosure. FIG. 3A shows a small depletion region 301 under the gate structure 311 when the gate voltage is greater than the threshold voltage (a negative value), with no bias applied to the drain 313. The device of FIG. 3A is in an on state (normally on) and a current flows along the 2-DEG carrier channel 315.

In FIG. 3B, a gate voltage less than the threshold voltage is applied, with no bias at the drain 313, such that a larger depletion region 303 is formed. The depletion region 303 crosses the 2-DEG carrier channel boundary so that no current flows through the 2-DEG carrier channel 315. The device of FIG. 3B is in an off state.

FIG. 3C shows a device with a gate voltage less than the threshold voltage and bias at the drain so that the drain voltage is greater than zero. A much larger depletion region 305 is formed, the size of which correspond to the bias at the drain 313. When the drain 313 bias is sufficiently large, for example, larger than the breakdown voltage of the device, a large enough electric field is formed that is greater than a critical electrical field (Ec) of the material, either the bulk layer 317 or the donor-supply layer 319. The device can breakdown or pop and be rendered inoperable.

FIGS. 4A to 4C are cross-sectional views of a HEMT structure and depletion regions formed during various operations for an III-V semiconductor material based transistor with the islands of the present disclosure. FIG. 4A shows a small depletion region 401 under the gate structure 411 when the gate voltage is greater than the threshold voltage (a negative value), with no bias applied to the drain 413. Small depletion regions 402 are also shown under the islands 421. Note that the depletion region 401 under the gate 411 incorporates the effect of island 423. The device of FIG. 4A is in an on state (normally on) and a current flows along the 2-DEG carrier channel 415 because none of the depletion regions 401 and 402 crosses the 2-DEG carrier channel 415.

In FIG. 4A, a gate voltage less than the threshold voltage is applied, with no bias at the drain 313, such that a larger depletion region 403 and smaller depletion regions 402 are formed. The depletion region 403 cross the 2-DEG carrier channel boundary so that no current flows through the 2-DEG carrier channel 415. The device of FIG. 4B is in an off state.

FIG. 4C shows a device with a gate voltage less than the threshold voltage and bias at the drain so that the drain voltage is greater than zero. A much larger depletion region 405 is formed combining the smaller depletion regions under the islands 421. In some embodiments, depletion region 405 extends into the bulk layer 417 through the 2-DEG carrier channel 415 and the donor-supply layer 419. The size of depletion region 405 corresponds to the bias at the drain 413. For the same bias at the drain 413, the maximum depth of the depletion region 405 is smaller than that of depletion region 305 from FIG. 3C because the depletion region 405 is more distributed across the drift region.

FIG. 5 is a plot of simulated peak surface electric field as a function of distance on the HEMT structures in accordance with various embodiments of the present disclosure. Electric field in volts per centimeter is plotted against a distance along line across the HEMT. The simulation models a gate voltage of −5 volts and drain bias of 600 volts. The peak corresponds to the gate structure edge closest to the drain. Line 501 is a simulated result for a HEMT without the islands as disclosed herein. The peak electric field for line 501 is about 6E6 V/cm. Line 503 is a simulated result for a HEMT having three islands between the gate structure and the drain. The peak electric field for line 503 is about 5E6 V/cm, for a reduction of about 20%. This simulated result shows that the island structures disclosed herein do indeed reduce peak surface electric field in the HEMT. While the peak electric field value would vary depending on the structure modeled in the simulation, the relative effect of the islands is clear.

The embodiments of the present disclosure may have other variations. For example, the islands may include more than one material, such as a layer of nickel oxide over a layer of gallium nitride. Certain embodiments of the present disclosure have several advantageous features. The use of various doping species allows fine-tuning of the islands, and hence the breakdown voltage, while minimizing adverse effects to other electrical properties, such as maximum forward current or leakage current.

Once aspect of this description relates to a method of making a circuit structure. The method includes growing a bulk layer over a substrate, and growing a donor-supply layer over the bulk layer. The method further includes depositing a doped layer over the donor-supply layer, and patterning the doped layer to form a plurality of islands. The method further includes forming a gate structure over the donor-supply layer, wherein the gate structure is partially over a largest island of the plurality of islands. The method further includes forming a drain over the donor-supply layer, wherein at least one island of the plurality of islands is between the gate structure and the drain.

Another aspect of this description relates to a method of making a circuit structure. The method includes growing a III-V compound layer over a substrate, and growing a donor-supply layer over the III-V compound layer. The method further includes forming a plurality of p-doped islands over the donor-supply layer. The method further includes forming a gate structure over the donor-supply layer, wherein an entirety of a bottom surface of the gate structure is below a top surface of each p-doped island of the plurality of p-doped islands, and the gate structure adjoins at least one p-doped island of the plurality of p-doped islands. The method further includes forming a drain over the donor-supply layer, wherein each of the plurality of islands is between the drain and the gate structure, and a drift region of the donor-supply layer occupies at least 50% of the donor-supply layer.

Still another aspect of this description relates to a circuit structure. The circuit structure includes a substrate, and an unintentionally doped (UID) III-V compound layer over the substrate. The circuit structure further includes an active layer over the UID III-V compound layer, and a plurality of doped islands over the active layer. The circuit structure further includes a gate structure and a drain over the active layer. At least one doped island of the plurality of doped islands is between the gate structure and the drain. A first portion of the gate structure is separated from the active layer by a doped island of the plurality of doped islands. A second portion the gate structures contacts the active layer, and the first portion is spaced from the second portion in a direction perpendicular to a direction from the gate structure to the drain.

Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the disclosure as defined by the appended claims. Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, and composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the present disclosure, processes, machines, manufacture, compositions of matter, means, methods, or steps that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present disclosure. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.

Claims

1. A circuit structure comprising: a substrate;a III-V compound layer over the substrate;an active layer over the III-V compound layer;a plurality of doped islands over the active layer; anda gate structure and a drain over the active layer, wherein at least one doped island of the plurality of doped islands is between the gate structure and the drain, a first portion of the gate structure is separated from the active layer by a doped island of the plurality of doped islands, a second portion the gate structures contacts the active layer, and the first portion is spaced from the second portion in a direction perpendicular to a direction from the gate structure to the drain, wherein the at least one doped island is a first doped island of the plurality of doped islands and the plurality of doped islands further includes a second doped island between the drain and the gate structure, the first and second doped islands being different in at least one of shape and size.

2. The circuit structure of claim 1, wherein the gate structure contacts a surface of the active layer between adjacent doped islands of the plurality of doped islands.

3. The circuit structure of claim 1, further comprising a source over the active layer, wherein a space between the gate structure and the source is free of the plurality of doped islands.

4. The circuit structure of claim 1, wherein the doped island is a polygon-shape having at least four sides.

5. The circuit structure of claim 1, wherein the plurality of doped islands further includes a third island between the drain and the gate structure, the first and third doped islands being different in at least one of shape and size.

6. The circuit structure of claim 1, wherein the first doped island is larger than the second doped island.

7. A semiconductor device structure, the structure comprising: a III-V compound layer over a substrate;an active layer over the III-V compound layer;a source and a drain over the active layer;a plurality of polygon shaped islands disposed over the active layer and interposing a gate structure and the drain;the gate structure over the active layer, wherein a first portion of the gate structure directly interfaces a first island of the plurality of polygon shaped islands and a second portion of the gate structure directly interfaces the active layer; andwherein the first island of the plurality of polygon shaped islands is a polygon having four or more sides.

8. The structure of claim 7, wherein the first portion of the gate structure that directly interfaces the first island is a sidewall of the gate structure.

9. The structure of claim 7, wherein the first portion of the gate is disposed on a top surface of the first island and is separated from the active layer by the first island.

10. The structure of claim 7, wherein the plurality of polygon shaped islands includes a second island, wherein the second island is smaller than the first island.

11. The structure of claim 10, wherein the second island is a different shape than the first island.

12. The structure of claim 7, wherein the plurality of polygon shaped islands are a p-doped material.

13. The structure of claim 7, wherein the plurality of polygon shaped islands are disposed directly on the active layer.

14. The structure of claim 7, wherein the plurality of polygon shaped islands are configured in a checker-board shape.

15. A circuit structure, the structure comprising: a bulk layer over a substrate;a donor-supply layer over the bulk layer;a plurality of islands disposed over the donor-supply layer;a gate structure over the donor-supply layer, wherein the gate structure is at least partially over a first island of the plurality of islands; anda drain over the donor-supply layer, wherein a second island of the plurality of islands is between the gate structure and the drain, the second island being smaller than the first island.

16. The circuit structure of claim 15, wherein the first island is a largest island of the plurality of islands.

17. The circuit structure of claim 15, wherein the first and second islands have a same shape.

18. The circuit structure of claim 15, further comprising a third island between the gate structure and the drain, wherein the first island is larger than the second island, and the second island is larger than the third island.

19. The circuit structure of claim 15, wherein the plurality of islands includes GaN material doped with a p-type dopant.

20. The circuit structure of claim 19, wherein the bulk layer includes GaN and the donor-supply layer includes AlGaN.