Patent Application
20070148875
The present invention relates generally to power semiconductor packaging and more particularly to a common drain dual MOSFET chip scale package and method of fabricating same.
With the increased use of mobile devices such as cellular telecommunication products, portable digital assistants, and tablet PCs, the size, weight and cost of individual electronic components and devices are factors critical to a successful design. For example, battery pack protection for such devices may require a printed circuit board (PCB) incorporating a few discrete chips occupying a small land pattern.
One such prior art battery protection circuit board is disclosed in U.S. Patent Application Publication No. US 2004/0256738 A1 entitled “Battery Protection Circuit with Integrated Passive Components”. In order to achieve space conservation and efficiency, the disclosed PCB, which carries the active devices such a charge MOSFET and a discharge MOSFET connected in a common drain configuration, and the control IC for controlling the devices, has passive elements embedded in the body of the PCB. Interconnections to the surface mounted devices and the embedded passive element are made by suitable conductive vias and the like. The charge MOSFET and the discharge MOSFET define a bidirectional MOSFET chip scale package.
Chip scale packaging (CSP) is a wafer level packaging process which reduces the size of package structures to die-sized packages. In CSP as applied to an integrated circuit (IC), peripheral pads of the integrated circuit are connected to I/O solder balls by redistribution layer routing. These conductive I/O solder balls or bumps enable connection of the IC to higher level circuit structures such as PCBs by flip chip or tape automated bonding attachment.
Consistent with the need to reduce the size, weight and cost of individual electronic components including the common drain dual MOSFET chips package, there is a need in the art for this kind of the device package having a small footprint. There is a further need for a common drain dual MOSFET device package that has a low profile and good thermal dissipation. There is also a need for a common drain dual MOSFET package that is light weight. There is also a need for a common drain dual MOSFET package having low or no inductance. There is a further need for a common drain dual MOSFET package having low Rds(on). There also a need for a low cost process for making such a common drain dual MOSFET package.
The present inventors have discovered and developed a novel wafer level process for fabricating a common drain dual MOSFET chip scale package having a common drain configuration which addresses the needs in the art. The process includes a step in which a back drain metal surface of the wafer is insulated with a dielectric material coating. The dielectric material coating provides protection to the back drain metal surface from subsequent processes including ball grid array bumping. The coating further adds mechanical strength of the wafer which advantageously provides increased throughput and yield in the fabrication of the common drain dual MOSFET chip scale packages.
In accordance with one aspect of the invention, a method of fabricating a plurality of common drain dual MOSFET chip scale packages includes the steps of providing a wafer having a plurality of common drain dual MOSFET devices disposed thereon, insulating a back drain metal surface of the wafer, under bump metallizing ball grid array pads on each of the common drain dual MOSFET devices, stenciling a solder mask to the wafer to expose the ball grid array pads, reflowing solder paste or pre-formed solder balls to form ball grid arrays of solder bumps, and dicing the wafer into the plurality of chip scale packages.
In accordance with another aspect of the invention, a common drain dual MOSFET chip scale package includes an insulating layer, the insulating layer being disposed adjacent a back drain metal surface of the dual MOSFET chip scale package.
There has been outlined, rather broadly, the more important features of the invention in order that the detailed description thereof that follows may be better understood, and in order that the present contribution to the art may be better appreciated. There are, of course, additional features of the invention that will be described below and which will form the subject matter of the claims appended herein.
In this respect, before explaining at least one embodiment of the invention in detail, it is to be understood that the invention is not limited in its application to the details of functional components and to the arrangements of these components set forth in the following description or illustrated in the drawings. The invention is capable of other embodiments and of being practiced and carried out in various ways. Also, it is to be understood that the phraseology and terminology employed herein, as well as the abstract, are for the purpose of description and should not be regarded as limiting.
As such, those skilled in the art will appreciate that the conception upon which this disclosure is based may readily be utilized as a basis for the designing of other methods and systems for carrying out the several purposes of the present invention. It is important, therefore, that the claims be regarded as including such equivalent constructions insofar as they do not depart from the spirit and scope of the present invention.
The present disclosure may be better understood and its numerous features and advantages made apparent to those skilled in the art by referencing the accompanying drawings.
The present invention discloses a wafer level method of fabricating a plurality of common drain dual MOSFET chip scale packages. The method advantageously provides for a process whereby common drain dual MOSFET chip scale packages may be formed from thin wafers including wafers of 7 to 8 mil thicknesses. Problems encountered in prior art processes including yield loss due to wafer warping are overcome by the novel process of the invention.
With reference to
An under bump metallization (UBM) step 120 may include a Ni/Au metallization process as described in commonly assigned U.S. patent application Ser. No. 11/242,625, filed on Sep. 30, 2004 and entitled “Wafer-Level Method for Metallizing Source, Gate and Drain Contact Areas of a Semiconductor Die”. The Ni/Au metallization process advantageously provides for a Ni layer formed on bump grid arrays and an Au layer to protect the Ni layer. As Ni does not diffuse into the Al of the bump grid array contact areas, an inter-metallic layer comprised of NI/Al provides for high density layers to which solder bumps may be attached.
In a step 130 a solder mask 133 may be stenciled to provide a mask for solder paste or pre-formed solder ball reflow to form solder BGA solder bumps in a step 140. The individual die may be diced in a step 150. The common drain dual MOSFET chip scale packages are then ready for surface mounting to a PCB.
Under bump metallization may include the metallization of bump grid arrays 167 with Ni/Au. A solder mask 170 may be stenciled to provide the mask for solder paste or pre-formed solder ball reflow to form solder BGA solder bumps 173. The wafer 155 may then be diced to form the plurality of common drain dual MOSFET chip scale packages 210.
As shown schematically in
The wafer level method of fabricating a plurality of common drain dual MOSFET chip scale packages of the invention provides for a process whereby common drain dual MOSFET chip scale packages may be formed from thin wafers including 7 to 8 mil wafers. The wafer level method further provides a reliable and cost effective package. The common drain dual MOSFET chip scale package in accordance with the invention has good thermal dissipation and short interconnect paths. The package of the invention also provides for low inductance and resistance as well as a compact package structure. The package is amenable to current surface mount assembly processes
It should be understood, of course, that the foregoing relates to preferred embodiments of the invention and that modifications may be made without departing from the spirit and scope of the invention as set forth in the following claims.
