Patent Application
20160086880
The present invention is directed to semiconductor devices and, more particularly, to electrical connections made using through silicon vias.
So-called “2.5D” integrated circuit packages have a silicon interposer for coupling active dies to package substrates. Current methods for fabricating silicon interposers and the overall packages are lengthy and expensive. For example, silicon interposers are typically manufactured having plated vias, requiring silicon etching, plating, chemical mechanical polishing (CMP), and other fabrication steps, which adds to manufacturing time and increases the cost. In addition, the silicon wafer used for the interposer much be relatively thin (e.g., less than 100 μm) to ease the depth of silicon etching and via plating required. On the other hand thought, thinner silicon wafers pose challenges for wafer handling.
It therefore would be desirable to have a method for manufacturing a silicon interposer and an integrated circuit package containing the same that reduces the number of overall fabrication steps and reduces the cost, yet still provides a reliable interconnection for 2.5D or other integrated circuit packages.
The present invention is illustrated by way of example and is not limited by embodiments thereof shown in the accompanying figures, in which like references indicate similar elements. Elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. Notably, certain vertical dimensions have been exaggerated relative to certain horizontal dimensions.
In the drawings:
In one embodiment, the present invention provides a semiconductor device including a semiconductor substrate having opposing first and second main surfaces, a via extending from the first main surface of the semiconductor substrate to the second main surface of the semiconductor substrate, a plurality of first electrical connectors formed proximate the first main surface of the semiconductor substrate and a plurality of second electrical connectors formed proximate the second main surface of the semiconductor substrate, a plurality of insulated bond wires, each extending through the via and having a first end bonded to a respective one of the plurality of first electrical connectors and a second end bonded to a respective one of the plurality of second electrical connectors, and an encapsulating material disposed at least within the via and encapsulating the plurality of insulated bond wires.
In another embodiment, the present invention provides a method of forming a semiconductor device. The method includes providing a semiconductor substrate having opposing first and second main surfaces, forming a plurality of first electrical connectors on the first main surface of the semiconductor substrate and a plurality of second electrical connectors on the second main surface of the semiconductor substrate, forming a via extending from the first main surface of the semiconductor substrate to the second main surface of the semiconductor substrate, wire bonding a first end of each of a plurality of insulated bond wires to a respective one of the plurality of first electrical connectors and a second end of each of the plurality of insulated bond wires to a respective one of the plurality of second electrical connectors such that each of the plurality of bond wires extends through the via, and encapsulating the plurality of bond wires in an encapsulating material. The encapsulating material is disposed at least within the via.
Referring now to the drawings, wherein the same reference numerals are used to designate the same components throughout the several figures, there is shown in
A plurality of first electrical connectors or contacts 14 is formed proximate, and preferably on, the first main surface 12a of the semiconductor substrate 12. The first electrical contacts 14 are preferably in the form of bonding pads, although other types of contacts may also be used. The first electrical contacts 14 may be made from copper (Cu) and/or other conductive materials, and may be coated, alloyed or pre-plated with a metal layer or layers such as gold (Au), nickel (Ni), palladium (PD), tin (Sn) or the like. Although the first electrical contacts 14 are shown in
In one embodiment, after the first electrical contacts 14 (i.e., redistribution traces) are deposited on the first main surface 12a of the substrate 12, the substrate 12 is thinned to about 200 um or other suitable thickness.
A plurality of second electrical connectors or contacts 16 is formed proximate the second main surface 12b of the semiconductor substrate 12. That is, as will be described later, a redistribution layer 30 is formed on the second main surface 12b of the substrate 12.
A via 18 (often referred to as a Through Silicon Via or TSV) is provided through the semiconductor substrate 12 extending from the first main surface 12a to the second main surface 12b thereof. To form the TSV or via 18, the substrate 12 (and RDL 30) may be attached to a support wafer (not shown) using suitable temporary adhesive and then an etching process performed. The via 18 provides a channel for connecting the first electrical contacts 14 with respective ones of the second electrical contacts 16. The connections are facilitated by a plurality of bond wires 20, which preferably comprise insulated or coated bond wires. In one embodiment, the bond wires 20 are preferably an insulated copper wire, gold wire, or the like, as are known in the art. For example, a typical insulated copper bond wire may have a diameter of 18-25 μm, such as insulated PdCu and insulated Cu bond wires available from W. C. Heraeus GmbH of Hanau, Germany. Coated bond wires may also be used, where an insulated coating is sprayed or otherwise formed over a conductive metal such as copper, gold or aluminum.
Each of the bond wires 20 extends through the via 18 and includes a first end 20a bonded to one of the first electrical contacts 14 and a second end 20b bonded to one of the second electrical contacts 16. The via 18 preferably has dimensions sized to accommodate the plurality of bond wires 20. For example, the via 18 may have a diameter of about 200 um in order to accommodate from 6-10 of the bond wires 20. The size of the via 18 is calculated based on the pitch of the wire bond pads 16 and the wirebond capillary dimensions.
As shown in
In one embodiment, a first encapsulation material 22 encapsulates the plurality of bond wires 20. The first encapsulation material 22 is preferably an epoxy, although other insulating materials may be used as well. It is preferred that the first encapsulation material 22 is disposed at least within the via 18. In
Subsequent to the wire bonding and filling of the via 18 with the first encapsulation material 22, the support wafer is removed from the substrate 12.
The device 10 further preferably includes one, and preferably a plurality of external electrical contacts 24a and 24b for connection to other components. For example, a plurality of first external electrical contacts 24a are provided on the first main surface 12a of the semiconductor substrate 12 in
The semiconductor die 26 is typically in the form of an integrated circuit (IC) or the like. The semiconductor die 26 may be made from any semiconductor material or combinations of materials, such as gallium arsenide, silicon germanium, silicon-on-insulator (SOI), silicon, monocrystalline silicon, the like, and combinations of the above. In
Also in
In other embodiments, a redistribution layer (not shown) may also or alternatively be provided on the first main surface 12a of the semiconductor substrate 12.
It is noted that more than one via 18 may be utilized, as shown in
After the vias 18 are formed, the bond wires 20 are threaded through the vias 18 (using conventional bonding wire apparatus) and the die 26 is attached to the first main surface 12a of the substrate 12, a second encapsulation material 34 may be formed over the die 26 and first main surface 12a of the substrate 12 using known techniques such as transfer molding. It also is noted the instead of two encapsulation materials 22 and 34 and two encapsulation steps, the vias 18 could be filled in the same step and with the same encapsulation material as when the die 26 and substrate first surface 12a are encapsulated.
There is shown in
The redistribution layer 30 may also be formed as necessary at this stage. The redistribution layer 30 shown in
Referring to
Referring to
Referring to
In addition, other solder balls 32 may be bonded to the appropriate second or external electrical connectors 16, 24b using conventional methods. The solder balls 32 may be attached before or after the encapsulating materials 22 and 34 are applied. The solder balls 32 may also be attached earlier or later in the process, as desired.
The semiconductor die 26 may be attached to the structure shown in
In the foregoing specification, the invention has been described with reference to specific examples of embodiments of the invention. It will, however, be evident that various modifications and changes may be made therein without departing from the broader spirit and scope of the invention as set forth in the appended claims.
Those skilled in the art will recognize that boundaries between the above-described operations are merely illustrative. The multiple operations may be combined into a single operation, a single operation may be distributed in additional operations and operations may be executed at least partially overlapping in time. Further, alternative embodiments may include multiple instances of a particular operation, and with the exception of expressly ordered steps, the order of operations may be altered in various other embodiments.
The terms “front,” “back,” “top,” “bottom,” “over,” “under” and the like in the description and in the claims, if any, are used for descriptive purposes and not necessarily for describing permanent relative positions. It is understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the invention described herein are, for example, capable of operation in other orientations than those illustrated or otherwise described herein.
In the claims, the word ‘comprising’ or ‘having’ does not exclude the presence of other elements or steps then those listed in a claim. Further, the terms “a” or “an,” as used herein, are defined as one or more than one. Also, the use of introductory phrases such as “at least one” and “one or more” in the claims should not be construed to imply that the introduction of another claim element by the indefinite articles “a” or “an” limits any particular claim containing such introduced claim element to inventions containing only one such element, even when the same claim includes the introductory phrases “one or more” or “at least one” and indefinite articles such as “a” or “an.” The same holds true for the use of definite articles. Unless stated otherwise, terms such as “first” and “second” are used to arbitrarily distinguish between the elements such terms describe. Thus, these terms are not necessarily intended to indicate temporal or other prioritization of such elements. The fact that certain measures are recited in mutually different claims does not indicate that a combination of these measures cannot be used to advantage.
