Patent Application
20250006488
The present disclosure relates to a deposition device, a semiconductor structure, and a method for manufacturing a semiconductor structure.
The integration density of various electronic components, such as transistors, diodes, resistors, capacitors, etc., is being improved continuously in the semiconductor industry by continual reduction in minimum feature sizes. As the feature sizes are decreased, the distance between metal features is continually reduced. As the distance between the metal features reduces, the resulting parasitic capacitance between the metal features increases, leading to higher power consumption and larger resistance-capacitance (RC) time delays for an integrated chip. To improve performance and reduce the parasitic capacitance between the metal features, materials having low dielectric (k) values are used. However, such dielectric materials encounter a lot of processing problems that prevent further improvement of the dielectric constant.
In the process of manufacturing semiconductor devices, there is a need to deposit low-K spacers (LKS) on different substrate surfaces with good uniformity. These different surfaces can constitute different materials, for example a metal and a dielectric. Uniform deposition of one material on two or more different substrate surfaces could be beneficial, for example by reducing the number of steps in device fabrication. There is also a need for dielectric materials with low dielectric constant (k) values and low etch rates, for example in acid-based etching solutions such as HF.
The disclosure provides a deposition device. The deposition device includes a first chamber, a substrate support, a second chamber, a showerhead, a first reactant inlet, a second reactant, and a precursor inlet. The first chamber includes a diffusion zone and a reaction zone, and the diffusion zone is above the reaction zone. The substrate support is disposed in the reaction zone. The second chamber is disposed over the first chamber. The showerhead is disposed between the first chamber and the second chamber. The first reactant inlet communicates with the second chamber. The second reactant inlet communicates with the reaction zone of the first chamber. The precursor inlet communicates with the showerhead.
In some embodiments, the deposition device further includes a first power source connected to the second chamber.
In some embodiments, the first power source comprises a radio frequency source and a remote plasma generator coupling to the radio frequency source.
In some embodiments, the deposition device further includes a second power source connected to the showerhead.
In some embodiments, the second power source is a radio frequency source.
In some embodiments, the deposition device further includes a fluid conduit partially covering an outside of the showerhead.
In some embodiments, a fluid transfer fluid flowing in the fluid conduit includes perfluoropolyether.
In some embodiments, the deposition device further includes a pump connected to the first chamber.
The disclosure provides a method for manufacturing a semiconductor structure. The method includes the following steps. A first conductive feature structure is formed over a substrate. A first spacer covers a sidewall of the first conductive feature structure, and a material of the first spacer includes SiCO. A second spacer covers a sidewall of the first spacer, and a material of the second spacer is different from the material of the first spacer. A third spacer covers a sidewall of the second spacer, and a material of the third spacer is different from the materials of the first spacer and the second spacer. A second conductive feature structure is formed adjacent to the third spacer.
In some embodiments, the step of forming the first spacer covering the sidewall of the first conductive feature structure includes the following steps. First, a structure with the first conductive feature structure over the substrate is placed on a substrate support in a deposition device. The deposition device includes a first chamber, a substrate support, a second chamber, a showerhead, a first reactant inlet, a second reactant, and a precursor inlet. The first chamber includes a diffusion zone and a reaction zone, and the diffusion zone is above the reaction zone. The substrate support is disposed in the reaction zone. The second chamber is disposed over the first chamber. The showerhead is disposed between the first chamber and the second chamber. The first reactant inlet communicates with the second chamber. The second reactant inlet communicates with the reaction zone of the first chamber. The precursor inlet communicates with the showerhead. Then, a first reactant gas flows from the first reactant inlet into the second chamber. A second reactant gas flows from the second reactant inlet into the first chamber. A precursor flows from the precursor inlet into the showerhead. Next, an atomic layer deposition is performed so that the first spacer covering the sidewall of the first conductive feature structure.
In some embodiments, the first reactant gas comprises H2, He, and O2.
In some embodiments, the second reactant gas comprises NF3, Ar, and O2.
The disclosure provides a semiconductor structure. The semiconductor structure includes a substrate, a bit line structure, a first spacer, a second spacer, a third spacer, and a contact. The bit line structure is disposed on the substrate. The first spacer is disposed on a sidewall of the first conductive feature structure, and a material of the first spacer includes SiCO. The second spacer is disposed on a sidewall of the first spacer. The third spacer is disposed on a sidewall of the second spacer. Materials of the second spacer and the third spacer are different from the material of the first spacer. The contact is disposed adjacent to the third spacer.
In some embodiments, the semiconductor structure further includes a landing pad disposed on the bit line structure and the first spacer.
In some embodiments, the landing pad is in direct contact to the bit line structure, the first spacer and the buried contact.
In some embodiments, the landing pad is in direct contact to one portion top surface of the first spacer.
In some embodiments, another portion top surface of the first spacer is exposed.
In some embodiments, the exposed another portion top surface of the first spacer is lower than the one portion top surface of the first spacer contacting with the landing pad.
It is to be understood that both the foregoing general description and the following detailed description are by examples, and are intended to provide further explanation of the disclosure as claimed.
The present disclosure can be more fully understood by reading the following detailed description of the embodiment, with reference made to the accompanying drawings as follows.
Reference will now be made in detail to the present embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.
The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
According to some embodiments, the deposition device 10 is a plasma chemical vapor deposition device such as a remote high density plasma atomic layer deposition (RHDALD). Referring to
Referring to
Although not all specifically shown in detail, the first chamber 110 and the second chamber 130 are typically coupled to facilities when installed in either a clean room or a fabrication facility. Facilities include plumbing that provide, among other things, processing gases, vacuum, temperature control, and environmental particle control. These facilities are coupled to the first chamber 110 and the second chamber 130, when installed in the target fabrication facility. Additionally, the first chamber 110 may be coupled to a transfer chamber that will enable robotics to transfer substrates (e.g., semiconductor wafers) into and out of the first chamber 110 using automation.
Referring to
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In some embodiments, the deposition device 10 further includes a fluid conduit 192 partially covering an outside of the showerhead 140. More specifically, a transfer fluid flowing in the fluid conduit 192 includes perfluoropolyether. The fluid conduit 192 has a serpentine shape in top view, consisting of a series of parallel equally spaced pipelines. In other words, the fluid conduit 192 is defined by a continuous pipeline that traces a path back and forth over the process region.
In some embodiments, the deposition device 10 further includes a pump 194 connecting to the first chamber 110. The pump 194 may be used to control pressure and/or evacuate reactants from the first chamber 110. More specifically, gases (e.g. process gases, inert gas, reaction byproducts, etc.) are evacuated from the diffusion zone 114 by the vacuum pump 194. It will be appreciated that the diffusion zone 114 and the reaction zone 112 can be maintained under vacuum by the vacuum pump 194.
According to another aspect of the present disclosure, a method for manufacturing a semiconductor structure (e.g., semiconductor structure 20 shown in
Various operations of embodiments are provided herein. The order in which some or all of the operations are described should not be construed to imply that these operations are necessarily order dependent. Alternative ordering will be appreciated having the benefit of this description. Further, it will be understood that not all operations are necessarily present in each embodiment provided herein. Also, it will be understood that not all operations are necessary in some embodiments.
Referring to
The substrate 200 may include a plurality of isolation areas (not shown) and a plurality of active areas (not shown). More specifically, the active areas are spaced apart by the isolation areas. The substrate 200 may include, for example, silicon (e.g., polycrystalline silicon, crystalline silicon, or amorphous silicon). In some embodiments, the substrate 200 may include other elementary semiconductor such as germanium. In some embodiments, the substrate 200 may include an alloy semiconductor such as silicon germanium carbide, silicon germanium, gallium indium phosphide and the like. In some embodiments, the substrate 200 may include compound semiconductor such as silicon carbide, gallium arsenic, indium phosphide, indium arsenide and the like. Further, the substrate 200 may optionally include a semiconductor-on-insulator (SOI) structure.
In some embodiments, the isolation areas may be formed through a shallow trench isolation (STI) process. The isolation areas may include, for example, a material including at least one of silicon oxide, silicon nitride, and silicon oxynitride. The isolation areas may be a single layer including one kind of insulator, a double layer including two kinds of insulators, or a multilayer including a combination of at least three kinds of insulators. For example, the isolation areas may include silicon oxide and silicon nitride. For example, the isolation areas may include a triple layer including silicon oxide, silicon nitride, and silicon oxynitride.
In some embodiments, an insulation layer 204 is formed over the substrate 200 to cover a top surface of the active area and isolation area within the substrate 200. The insulation layer 204 is made of any suitable dielectric material, such as silicon oxide, boro-phospho silicate glass (BPSG), or traethylorthosilicate(TEOS), but the present disclosure is not limited to the above material.
During a formation of the insulation layer 204, an opening (not shown) may expose a portion of active area of the substrate 200 and define a direct contact 206. The opening (not shown) is then filled with a conductive material to form the direct contact 206. The direct contact 206 directly contacts the portion of the active area of the substrate 200, leading to an electrical connection between the direct contact 206 and the active area.
In some embodiments, a plurality of first conductive feature structure 210 (e.g., bit line structures) protrudes from the substrate 200 as shown in
The formation of the conductive layer 212 and the insulation layer 214 may include forming a conductive material layer and an insulation material layer sequentially over the substrate 200. The insulation material layer may be formed on the conductive material layer. In one embodiment, both of the conductive material layer and the insulation material layer may be substantially simultaneously etched to form the conductive layer 212 and the insulation layer 214. Thus, the first conductive feature structure 210 including the conductive layer 212 and the insulation layer 214 may be spaced apart from each other in a first direction (e.g., the X direction) and extend in parallel with each other along a second direction (e.g., the Y direction). In yet another embodiment, the insulation material layer is etched with desirable patterned and served as a mask pattern on the conductive material layer. Using the patterned insulation material layer as an etch mask, the conductive material layer is etched to form the conductive layer 212.
In some embodiments, the conductive layer 212 includes at least one material selected from semiconductor with impurities doped thereon, metal, conductive metal nitride, and metal silicide. In some embodiments, the conductive layer 212 may have a stacked structure. For example, the conductive layer 212 may be stacked with materials including doped polysilicon as well as metal nitride or metal such as tungsten, tungsten nitride, and/or titanium nitride.
In some embodiments, the insulation layer 214 includes silicon nitride. A vertical length (e.g., a length along the Z axis) of the insulation layer 214 may be greater than that of the conductive layer 212.
Referring to
It should be noted that the first spacer 222 consists of SiCO for the SiCO with a dielectric constant (k) of approximate 4.3 reducing parasitic capacitance between the first conductive feature 210 and the second conductive feature structure 230 (shown in
The first spacer 222 is formed by the aforementioned deposition device 10 (shown in
The second spacer 224 and the third spacer 226 may be formed by any suitable deposition approaches such as chemical vapor deposition (CVD) techniques, atomic layer deposition (ALD), or physical vapor deposition (PVD) techniques. In other embodiment, any suitable etching approaches such as reactive ion etching (RIE) techniques may be implemented on the first spacer 222, the second spacer 224, and/or the third spacer 226 to form a particular configuration depending on a design of a semiconductor device. For example, the second spacer 224 may not be as high as the first spacer 222 and/or the third spacer 226.
Referring to
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In some embodiments, the landing pad material 240 includes a conductive material. For example, the conductive material is a void-free structure. To achieve the void-free structure, forming the conductive material may include several deposition processes and etching processes. In some embodiments, deposition/etch-back/deposition (dep/etch/dep) process is employed to deposit the conductive material into a gap (not shown) between two adjacent first conductive feature structures 210. The dep-etch-dep process involves depositing conductive material, followed by etching some of the conductive material back to widen an opening (not shown) of the gap, and followed by re-depositing conductive material.
The landing pad material 240 may be deposited by using CVD, ALD, PVD, or other suitable deposition process. In some embodiments, a deposition temperature used in the deposition process is in a range of about 280° C. to about 320° C. For example, the deposition temperature used in the deposition process can be 280° C., 290° C., 300° C., 310° C., or 320° C. The etching process performed after the deposition process includes using any suitable dry etching processes and/or wet etching processes. The landing pad material 240 may be stacked with materials including metal nitride or metal such as tungsten, tungsten nitride, and/or titanium nitride.
Referring to
According to yet aspect of the present disclosure, a semiconductor structure 20 is provided.
In some embodiments, the semiconductor structure 20 further includes a landing pad 250 disposed on the bit line structure 210, the first spacer 222, the second spacer 224, the third spacer 226, and the buried contact 230. The landing pad 250 is in direct contact to the bit line structure 210, the first spacer 222 and the buried contact 230. More specifically, the landing pad 250 is in direct contact to one portion top surface of the first spacer 222 and another portion top surface of the first spacer 222 is exposed. In some embodiments, the exposed another portion top surface of the first spacer 222 is lower than the one portion top surface of the first spacer 222 contacting with the landing pad 250. The materials and forming methods of each element have been described in detail above, and will not be repeated here.
The original SiN spacer in the semiconductor structure is replaced with a SiCO spacer by a novel deposition device of the present disclosure to reduce parasitic capacitance. In addition, the SiCO spacer formed by the novel deposition device of the present disclosure may reduce plasma induced damage to prevent semiconductor structure damage and reduce film pinhole, thereby having better conformity and film quality.
Although the present disclosure has been described in considerable detail with reference to certain embodiments thereof, other embodiments are possible. Therefore, the spirit and scope of the appended claims should not be limited to the description of the embodiments contained herein.
It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present disclosure without departing from the scope or spirit of the disclosure. In view of the foregoing, it is intended that the present disclosure cover modifications and variations of this disclosure provided they fall within the scope of the following claims.
