Patent Application
20250046710
This disclosure relates generally to electronic systems including dual die assemblies utilized on an electronic system.
Multiple semiconductor dies are frequently integrated into a single package using Die-to-Die (D2D) packaging techniques. One such packaging technique includes D2D packaging with a passive interposer, also referred to as “DDP” packaging. In some examples, a pair of semiconductor dies are packaged together in a face-to-face (F2F) arrangement relative to one another. A F2F arrangement can permit a single conductive RDL structure to be utilized for accessing each of the semiconductor dies, which can enhance access speeds as compared to configurations in which the semiconductor dies are provided in a back-to-face (B2F) arrangement relative to one another. Conventional conductive RDL structures for F2F arrangements can require complex patterns to facilitate desired electrical connection of pads of neighboring semiconductor dies. In some examples, due to packaging constraints and tight pad pitch, it is difficult or impractical to desirably electrically connect pads of neighboring semiconductor dies using conventional conductive RDL structure configurations.
The illustrations presented herein are not actual views of any dual die assembly, electronic systems, or any component thereof, but are merely idealized representations, which are employed to describe embodiments of the present invention.
As used herein, a “memory device” means and includes microelectronic devices exhibiting memory functionality, but not necessarily limited to memory functionality. Stated another way, and by way of non-limiting example only, the term “memory device” includes not only conventional memory (e.g., conventional non-volatile memory; conventional volatile memory), but also includes an application specific integrated circuit (ASIC) (e.g., a system on a chip (SoC)), a microelectronic device combining logic and memory, and a graphics processing unit (GPU) incorporating memory.
As used herein, the terms “configured” and “configuration” refers to a size, a shape, a material composition, a material distribution, orientation, and arrangement of at least one feature (e.g., one or more of at least one structure, at least one material, at least one region, at least one device) facilitating use of the at least one feature in a pre-determined way.
As used herein, the singular forms following “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise.
As used herein, “and/or” includes any and all combinations of one or more of the associated listed items.
As used herein, the term “may” with respect to a material, structure, feature, or method act indicates that such is contemplated for use in implementation of an embodiment of the disclosure, and such term is used in preference to the more restrictive term “is” so as to avoid any implication that other compatible materials, structures, features, and methods usable in combination therewith should or must be excluded.
As used herein, spatially relative terms, such as “beneath,” “below,” “lower,” “bottom,” “above,” “upper,” “top,” “front,” “rear,” “left,” “right,” and the like, may be used for ease of description to describe one element's or feature's relationship to another element(s) or feature(s) as illustrated in the drawings. Unless otherwise specified, the spatially relative terms are intended to encompass different orientations of the materials in addition to the orientation depicted in the figures. For example, if materials in the figures are inverted, elements described as “below” or “beneath” or “under” or “on bottom of” other elements or features would then be oriented “above” or “on top of” the other elements or features. Thus, the term “below” can encompass both an orientation of above and below, depending on the context in which the term is used, which will be evident to one of ordinary skill in the art. The materials may be otherwise oriented (e.g., rotated 90 degrees, inverted, flipped) and the spatially relative descriptors used herein interpreted accordingly.
As used herein, the terms “vertical,” “longitudinal,” “horizontal,” and “lateral” are in reference to a major plane of a structure and are not necessarily defined by earth's gravitational field. A “horizontal” or “lateral” direction is a direction that is substantially parallel to the major plane of the structure, while a “vertical” or “longitudinal” direction is a direction that is substantially perpendicular to the major plane of the structure. The major plane of the structure is defined by a surface of the structure having a relatively large area compared to other surfaces of the structure.
As used herein, features (e.g., structures, materials, regions, devices) described as “neighboring” one another means and includes features of the disclosed identity (or identities) that are located most proximate (e.g., closest to) one another. Additional features (e.g., additional regions, additional structures, additional devices) not matching the disclosed identity (or identities) of the “neighboring” features may be disposed between the “neighboring” features. Put another way, the “neighboring” features may be positioned directly adjacent one another, such that no other feature intervenes between the “neighboring” features; or the “neighboring” features may be positioned indirectly adjacent one another, such that at least one feature having an identity other than that associated with at least one the “neighboring” features is positioned between the “neighboring” features. Accordingly, features described as “vertically neighboring” one another means and includes features of the disclosed identity (or identities) that are located most vertically proximate (e.g., vertically closest to) one another. Moreover, features described as “horizontally neighboring” one another means and includes features of the disclosed identity (or identities) that are located most horizontally proximate (e.g., horizontally closest to) one another.
As used herein, the term “substantially” in reference to a given parameter, property, or condition means and includes to a degree that one skilled in the art would understand that the given parameter, property, or condition is met with a small degree of variance, such as within acceptable manufacturing tolerances. By way of example, depending on the particular parameter, property, or condition that is substantially met, the parameter, property, or condition may be least 90.0 percent met, at least 95.0 percent met, at least 99.0 percent met, at least 99.9 percent met, or even 100.0 percent met.
As used herein, “about” or “approximately” in reference to a numerical value may include additional numerical values within a range of from 90.0 percent to 110.0 percent of the numerical value, such as within a range of from 95.0 percent to 105.0 percent of the numerical value, within a range of from 97.5 percent to 102.5 percent of the numerical value, within a range of from 99.0 percent to 101.0 percent of the numerical value, within a range of from 99.5 percent to 100.5 percent of the numerical value, or within a range of from 99.9 percent to 100.1 percent of the numerical value.
As used herein, the phrase “coupled to” refers to structures operatively connected with each other, such as electrically connected through a direct Ohmic connection or through an indirect connection (e.g., by way of another structure).
As used herein, “conductive material” means and includes electrically conductive material such as one or more of a metal (e.g., tungsten (W), titanium (Ti), molybdenum (Mo), niobium (Nb), vanadium (V), hafnium (Hf), tantalum (Ta), chromium (Cr), zirconium (Zr), iron (Fe), ruthenium (Ru), osmium (Os), cobalt (Co), rhodium (Rh), iridium (Ir), nickel (Ni), palladium (Pd), platinum (Pt), copper (Cu), silver (Ag), gold (Au), aluminum (Al)), an alloy (e.g., a Co-based alloy, an Fe-based alloy, an Ni-based alloy, an Fe- and Ni-based alloy, a Co- and Ni-based alloy, an Fe- and Co-based alloy, a Co- and Ni- and Fe-based alloy, an Al-based alloy, a Cu-based alloy, a magnesium (Mg)-based alloy, a Ti-based alloy, a steel, a low-carbon steel, a stainless steel), a conductive metal-containing material (e.g., a conductive metal nitride, a conductive metal silicide, a conductive metal carbide, a conductive metal oxide), and a conductively doped semiconductor material (e.g., conductively doped polysilicon, conductively doped germanium (Ge), conductively doped silicon germanium (SiGe)). In addition, a “conductive structure” means and includes a structure formed of and including conductive material.
As used herein, “insulative material” means and includes electrically insulative material, such one or more of at least one dielectric oxide material (e.g., one or more of a silicon oxide (SiOx), phosphosilicate glass, borosilicate glass, borophosphosilicate glass, fluorosilicate glass, an aluminum oxide (AlOx), a hafnium oxide (HfOx), a niobium oxide (NbOx), a titanium oxide (TiOx), a zirconium oxide (ZrOx), a tantalum oxide (TaOx), and a magnesium oxide (MgOx)), at least one dielectric nitride material (e.g., a silicon nitride (SiNy)), at least one dielectric oxynitride material (e.g., a silicon oxynitride (SiOxNy)), at least one dielectric oxycarbide material (e.g., silicon oxycarbide (SiOxCy)), at least one hydrogenated dielectric oxycarbide material (e.g., hydrogenated silicon oxycarbide (SiCxOyHz)), and at least one dielectric carboxynitride material (e.g., a silicon carboxynitride (SiOxCzNy)). Formulae including one or more of “x,” “y,” and “z” herein (e.g., SiOx, AlOx, HfOx, NbOx, TiOx, SiNy, SiOxNy, SiOxCy, SiCxOyHz, SiOxCzNy) represent a material that contains an average ratio of “x” atoms of one element, “y” atoms of another element, and “z” atoms of an additional element (if any) for every one atom of another element (e.g., Si, Al, Hf, Nb, Ti). As the formulae are representative of relative atomic ratios and not strict chemical structure, an insulative material may comprise one or more stoichiometric compounds and/or one or more non-stoichiometric compounds, and values of “x,” “y,” and “z” (if any) may be integers or may be non-integers. As used herein, the term “non-stoichiometric compound” means and includes a chemical compound with an elemental composition that cannot be represented by a ratio of well-defined natural numbers and is in violation of the law of definite proportions. In addition, an “insulative structure” means and includes a structure formed of and including insulative material.
In some examples, apparatuses are configured to have a pair of dies oriented in a F2F arrangement relative with one another while still enabling desired coupling of predetermined pads of the dies with one another. The F2F arrangement may permit relatively fewer and/or less tortuous conductive RDL structure to be utilized for accessing predetermined circuitries of the dies, which may improve access speeds as compared to conventional configurations.
The second die 130 may include a back surface 132 and a facing surface 134. The facing surface 134 may be relatively more proximate the first die 110 than the back surface 132. The back surface 132 may be vertically positioned opposite the facing surface 134. The second die 130 may further comprise a first pad 136a and a second pad 136b on the facing surface 134. The first pad 136a and the second pad 136b may be coupled to a first additional conductive RDL structures 138a (e.g., first additional conductive routing) and second additional conductive RDL structures 138b (e.g., second additional conductive routing) conductive RDL structure 138b, respectively.
The first and second conductive RDL structure 118a, 118b of the first die 110 are coupled to the first and second additional conductive RDL structure 138a, 138b, respectively, of the second die 130. The coupling may be facilitated by at least one first conductive interconnect 150a coupling the first conductive RDL structure 118a of the first die 110 to the first additional conductive RDL structure 138a of the second die 130, and by at least one second conductive interconnect 150b coupling the second conductive RDL structure 118b of the first die 110 to the second additional conductive RDL structure 138b of the second die 130. The first and second conductive interconnects 150a, 150b may comprise solder bumps, conductively filled vias, and/or another conductive structure.
When the first die 110 and the second die 130 are in a F2F arrangement as shown in
The first and second conductive RDL structures 118a, 118b and the first and second additional conductive RDL structures 138a, 138b are configured to resolve the horizontal misalignment of the corresponding first pads 116a, 136a and the horizontal misalignment of the corresponding second pads 116b, 136b. For example, as shown in
With corresponding first pads 116a, 136a coupled to one another via the first conductive RDL structures 118a, 138a, both of the first pads 116a, 136a of the first and second dies 110, 130 may be electrically connected to a substrate 170 by way of a first wire 174a. Similarly, with corresponding second pads 116b, 136b coupled to one another via the second conductive RDL structures 118b, 138b, both of the second pads 116b, 136b of the first and second dies 110, 130 may be electrically connected to the substrate 170 by way of a second wire 174b. The first and second wires 174a, 174b may be coupled to first circuitries 172a and second circuitries 172b of the substrate 170, respectively. The first circuitries 172a and second circuitries 172b may be located in, on, or over the substrate 170. The substrate 170 may also include interconnect structures 176a, 176b, such as solder balls or any other structure suitable for coupling the substrate 170, and thus the dual die assembly 100, to external circuitry.
In some die configurations, packaging of dies may create constraints that make it difficult to route conductive RDL structures such that the conductive RDL structures cross over one another, as described above. In some configurations, tight pad pitch may make such cross-over configurations challenging or impractical. However, it may still be advantageous to arrange dies in a face-to-face configuration even when such configurations of the conductive RDL structures are impractical.
The second die 230 may include a back surface 232 and a facing surface 234 (also referred to herein as a “face surface”). The facing surface 234 may be relatively more proximate the first die 210 than the than the back surface 232. The back surface 232 may be vertically positioned opposite the facing surface 234. The second die 230 may further include a first pad 236a and a second pad 236b on the facing surface 234. The first pad 236a and the second pad 236b are horizontally offset from one another in the Y-direction. The first pad 236a and the second pad 236b may be coupled to a first additional conductive RDL structure 238a (e.g., first additional conductive routing) and second additional conductive RDL structure 238b (e.g., second additional conductive routing), respectively.
Similar to the dual die assembly 100 previously described with reference to
In shown in
In dual die assembly 200, at least the second die 230 may include mirror function circuitry 240 based on the specifications of the first and second dies 210, 230. For example, for first and second dies 210, 230 configured according to a DDR5 specification, the second die 230 may include a mirror function circuitry 240 that may be operable to swap functionality of pairs of pads of the second die 230. For example, if the second die 230 includes pairs of pads identified as (CA0, CA1), (CA2, CA3), (CA4, CA5), . . . (CAn-1, CAn), then the mirror function circuitry 240 may be operable to effectively swap the assignments of these pairs of pads to effectively operate as (CA1, CA0), (CA3, CA2), (CA5, CA4), . . . (CAn, CAn-1). The mirror function circuitry 240 may be configured to selectively swap circuitry that one pad of an individual pair of pads is electrically connected to (e.g., by way of the mirror function circuitry 240) with additional circuitry that the other pad of the individual pair of pads is electrically connected to (e.g., also by way of the mirror function circuitry 240), and vice versa. Such a mirror function circuitry 240 may be beneficial in a variety of circumstances, such as for two-sided module clamshell component placements.
In
In addition, the second pad 216b of the first die 210 may be coupled to the first pad 236a of the second die 230. The first pad 236a of the second die 230 may be imparted with the functionality of the second pad 236b of the second die 230 by way of the mirror function circuitry 240. The second pad 216b of the first die 210 may be coupled to the first pad 236a of the second die 230 by way of the second conductive RDL structure 218b of the first die 210, the first additional conductive RDL structures 238a of the second die 230, and a second interconnect 250b. For example, the second pad 216b may be coupled to the second conductive RDL structure 218b, the first pad 236a may be coupled to the first additional conductive RDL structures 238a, and the second conductive RDL structure 218b may be coupled to the firs first additional conductive RDL structures 238a by way of the second interconnect 250b.
As shown in
With the first pad 216a of the first die 210 and the second pad 236b (effectively serving as the first pad 236a through use and operation of the mirror function circuitry 240) coupled to one another via the first conductive RDL structure 218a and the second additional conductive RDL structure 238b, the first pad 216a and the second pad 236b may be electrically connected to a substrate 270 by way of a first wire 274a. Similarly, with the second pad 216b of the first die 210 and the first pad 236a (effectively serving as the second pad 236b through use and operation of the mirror function circuitry 240) coupled to one another via the second conductive RDL structure 218b and the first additional conductive RDL structures 238a, the second pad 216b and the first pad 236a may be electrically connected to the substrate 270 by way of a second wire 274b. The first and second wires 274a, 274b may be coupled to first circuitries 272a and second circuitries 272b of the substrate 270, respectively. The first circuitries 272a and second circuitries 272b may be located in, on, or over the substrate 270. The substrate 270 may also include interconnect structures 276a, 276b, such as solder balls or any other structure suitable for coupling the substrate 270, and thus the dual die assembly 200, to external circuitry.
Thus, in accordance with embodiments of the disclosure, an assembly includes a first die, and a second die arranged face-to-face with the first die. The first die includes a first pad on a facing surface of the first die, a second pad on the facing surface of the first die, and mirror function circuitry configured to swap functionalities of the first pad and the second pad. The second die includes an additional first pad on an additional facing surface of the second die, the additional first pad corresponding to the first pad of the first die, and an additional second pad on the additional facing surface of the second die, the additional second pad corresponding to the second pad of the first die. The additional first pad is coupled to the second pad of the first die. The additional second pad is coupled to the first pad of the first die.
Since mirror function circuitry for a die is part of a specification of the die, dual die assemblies (e.g., the dual die assembly 200) of the disclosure may be operable to utilize the mirror function circuitry (e.g., the mirror function circuitry 240) of a die (e.g., the second die 230) thereof to facilitate a F2F arrangement of dies (e.g., the first die 210 and the second die 230) of the dual die assembly while also maintaining normal use and operation of the mirror function circuitry. In other words, the dies of the dual die assembly can utilize the mirror function circuitry of one of the dies to facilitate coupling of pads of the dies without complex conductive RDL structure configurations (e.g., horizontal cross-over configurates) with either of the dies, while also maintaining normal use of operation of the mirror function circuitry for the dies.
When the die 330 is incorporated into a dual die assembly (e.g., the dual die assembly 200 (
When two (2) dies of a dual die assembly (e.g., the dual die assembly 200 (
Similar to the die 330 discussed above with reference to
With the first and second dies 410, 430 in a F2F arrangement relative to one another, signals output by the mirror function circuitry 420, 440 of one of the first and second dies 410, 430 may be inverted to facilitate desired coupling of the pads 416a, 436b, 416b, 436a. The first die 410 may include a mirror function inverter 424 configured to receive a mirror function signal output by the mirror function circuitry 420, and to output a mirror signal to a first pad input buffer 428a and a second pad input buffer 428b. The mirror signal output by the mirror function inverter 424 may be the same as the signal received from the mirror function circuitry 420, or may be inverted relative to the signal received from the mirror function circuitry 420. Whether the mirror function inverter 424 inverts the signal received from the mirror function circuitry 420 may be based on a signal received from the inverter trigger 422. The inverter trigger 422 may be used to identify which of the first die 410 and the second die 430 is the top or bottom die in the stack of the dual die assembly 400.
Output driver supply (VDDQ) potential or ground (VSS) potential may be utilized to control how the inverter trigger 422 effects whether signals output from mirror function circuitry 420 are inverted by the mirror function inverter 424. For example, the inverter trigger 422 may include a bond pad positioned to receive one of a VDDQ potential and a VSS potential to determine whether the mirror function inverter 424 should be activated. For example, when the bond pad of the inverter trigger 422 is supplied with a VDDQ potential, the inverter trigger 422 may signal the mirror function inverter 424 to invert the signal input to the mirror function inverter 424 from the mirror function circuitry 420. When the bond pad of the inverter trigger 422 supplied with a VSS potential, the inverter trigger 422 may signal the mirror function inverter 424 to remain inactive and to not invert the input signal to the mirror function inverter 424 from the mirror function circuitry 420. In
Similar to the first die 410, the second die 430 may include a mirror function inverter 444 configured to receive a mirror function signal output by the mirror function circuitry 440, and to output a mirror signal to a first pad input buffer 448a and a second pad input buffer 448b. The mirror signal output by the mirror function inverter 444 may be the same as the signal received from the mirror function circuitry 440, or may be inverted relative to the signal received from the mirror function circuitry 440. Whether the mirror function inverter 444 inverts the signal input to it from the mirror function circuitry 440 may be based on a signal received from the inverter trigger 442.
VDDQ potential or VSS potential may be utilized to control how the inverter trigger 442 effects whether signals output from the mirror function circuitry 440 are inverted by the mirror function inverter 444. For example, the inverter trigger 442 may include a bond pad positioned to receive one of a VDDQ potential and a VSS potential to determine whether the mirror function inverter 444 should be activated. In
By utilizing the inverter triggers 422, 442, the first and second dies 410, 430 may be provided in a F2F arrangement relative to one another and may employ the mirror function circuitries 420, 440 to alleviate routing complexity relative to conventional configurations, without adversely affecting desirable mirror functionality in the dual die assembly 400. In the example shown in
In additional embodiments, an inverter trigger of a die of an assembly of the disclosure may be configured provide a signal to a mirror function inverter of the die without the use of a bond pad. For instance, the positioning of additional features within the die may make the positioning of a bond pad for the inverter trigger within the die challenging or impractical. Accordingly,
In
Thus, in accordance with embodiments of the disclosure, an assembly includes a die and an additional die vertically overlying the die. The die includes a face side, a back side vertically opposing the face side, a first bond pad on the face side, a second bond pad on the face side, and mirror function circuitry coupled to the first bond pad and the second bond pad, the mirror function circuitry configured to swap which additional circuitries the first bond pad and the second bond pad are respectively coupled to with one another. The additional die includes an additional face side relatively more proximate to the face side of the die than the back side of the die, an additional back side vertically opposing the additional face side, a first additional bond pad on the additional face side and horizontally overlapping the second bond pad of the die in a first direction, a second additional bond pad on the additional face side and horizontally overlapping the first bond pad of the die in the first direction, and additional mirror function circuitry coupled to the first additional bond pad and the second additional bond pad.
Assemblies (e.g., the dual die assemblies 200, 400, 500) may be employed in embodiments of electronic systems of the disclosure. For example,
The electronic system 600 may further include one or more input devices 630 for inputting information into the electronic system 600 by a user, such as, for example, a mouse or other pointing device, a keyboard, a touchpad, a button, or a control panel. The electronic system 600 may further include one or more output devices 640 for outputting information (e.g., visual or audio output) to a user such as, for example, a monitor, a display, a printer, an audio output jack, and/or a speaker. In some embodiments, the input device 630 and the output device 640 may comprise a single touchscreen device that can be used both to input information to the electronic system 600 and to output visual information to a user. The input device 630 and the output device 640 may communicate electrically with one or more of the memory device 620 and the electronic signal processor device 610.
Thus, in accordance with embodiments of the disclosure, an electronic system includes a dual die assembly including a first die and a second die overlying the first die. The first die includes a face side, a back side, and mirror function circuitry. The face side includes a first conductive pad and a second conductive pad horizontally offset from the first conductive pad. The back side opposes the face side. The mirror function circuitry is coupled to the first conductive pad, the second conductive pad, first circuitry, and second circuitry different than the first circuitry. The mirror function circuitry is configured to selectively change electrical connections of the first circuitry and the second circuitry between the first conductive pad and the second conductive pad. The second die includes an additional face side, an additional back side, and additional mirror function circuitry. The additional face side opposes the face side of the first die and includes a first additional conductive pad, and a second additional conductive pad horizontally offset from the first additional conductive pad. The additional back side opposes the additional face side. The additional mirror function circuitry is coupled to the first additional conductive pad, the second additional conductive pad, first additional circuitry, and second additional circuitry different than the first additional circuitry. The additional mirror function circuitry is configured to selectively change electrical connections of the first additional circuitry and the second additional circuitry between the first additional conductive pad and the second additional conductive pad.
The embodiments of the disclosure described above and illustrated in the accompanying drawings do not limit the scope of the disclosure, which is encompassed by the scope of the appended claims and their legal equivalents. Any equivalent embodiments are within the scope of this disclosure. Indeed, various modifications of the disclosure, in addition to those shown and described herein, such as alternate useful combinations of the elements described, will become apparent to those skilled in the art from the description. Such modifications and embodiments also fall within the scope of the appended claims and equivalents.
This application claims the benefit under 35 U.S.C. § 119(e) of U.S. Provisional Patent Application Ser. No. 63/516,833, filed Jul. 31, 2023, the disclosure of which is hereby incorporated herein in its entirety by this reference.
| Number | Date | Country | |
|---|---|---|---|
| 63516833 | Jul 2023 | US |
