Patent Application
20250140733
The disclosure relates to die bonding technology, in particular, to die bonding structures with nano-twinned layers and a method of manufacturing the same.
This application claims priority of Taiwan Patent Application No. 112211673, filed on Oct. 30, 2023, the entirety of which is incorporated by reference herein.
In the fabrication process of power integrated circuit (IC) modules and high-power light-emitting diode (LED) packaging, there is a step to die bonding between the chip and the ceramic substrate. The existing die bonding technology includes eutectic bonding, adhesive bonding, solder bonding, and the like, which cannot withstand the high temperature operation of the chip and have poor reliability. Therefore, silver sintering and copper sintering are currently becoming more and more popular die bonding technologies, especially in electric vehicle power module packaging. However, the thermal stress generated by the high temperature of die bonding in silver sintering and copper sintering will cause extremely severe damage, so that the bonding strength is generally lower than 20 MPa.
The backside of the chip needs to be coated with a metal layer before bonding, whether it is a power IC module or high-power LED packaging. The traditional structure of the backside metal layer is Ti/Ni/Ag, in which the outermost silver layer is composed of equi-axial coarse grains, and its grain boundaries have chaotic lattice orientations.
Taiwan Patent No. 1432613 discloses a method of electroplating copper nano-twinned. Taiwan Patent No. 1703226 also discloses a method of sputtering silver nano-twinned. Taiwan Patent No. 1810631 further discloses a method of evaporating silver nano-twinned by using ion beam bombardment. These existing techniques have confirmed that high-density (111) crystal orientation of the nano-twinned layers can be obtained, and the atomic diffusion rate of (111) crystal orientation is higher than that of (100) and (110) crystal orientations by 3 to 5 orders of magnitude.
For the application of the above-mentioned method, Taiwan Patent No. 1686518 discloses a method of direct bonding at low temperatures by using copper nano-twinned. Taiwan Patent No. 1432613 further discloses a method of direct bonding between a chip and a ceramic substrate at low temperatures by using silver nano-twinned. However, the bonding interface of the existing nano-twinned direct stacking bonding technology only has a thin film structure below 10 mm, and its bonding strength is generally only 20 to 40 MPa, which raises extremely serious concerns about reliability. In the case of the die bonding between the chip and the ceramic substrate, the existing method of nano-twinned direct stacking is to directly insert the nano-twinned film between the chip and the ceramic substrate, but it easily causes cracks in the bonding interface and is still not widely used, especially for high-power automotive modules with extremely demanding requirements.
An embodiment of the present disclosure provides a die bonding structure. The die bonding structure includes a carrier substrate, a sintered layer, a nano-twinned layer, an adhesive layer and a chip. The sintered layer is located on the carrier substrate. The nano-twinned layer is located on the sintered layer, in which the surface of the nano-twinned layer has crystal orientation with a density greater than 80%, in which the nano-twinned layer comprises parallel-arranged twin boundaries, the parallel-arranged twin boundaries comprise more than 40% crystal orientation, and the spacing between the parallel-arranged twin boundaries is 10 to 100 nm. The adhesive layer is located on the nano-twinned layer. The chip is located on the adhesive layer.
An embodiment of the present disclosure provides a method of manufacturing a die bonding structure. The method includes providing a chip, forming an adhesive layer on the nano-twinned layer, forming a nano-twinned layer on the sintered layer, and performing a bonding process to bond the nano-twinned layer to a carrier substrate through a sintered layer. The surface of the nano-twinned layer has [111] crystal orientation with a density greater than 80%. The nano-twinned layer comprises parallel-arranged twin boundaries. The parallel-arranged twin boundaries comprise more than 40% [111] crystal orientation. The spacing between the parallel-arranged twin boundaries is 10 to 100 nm.
Aspects of the present disclosure are better understood from the following detailed description when read with the accompanying figures. It is worth noting that some features may not be drawn to scale in accordance with the standard practice in the industry. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. It is also emphasized that the drawings appended illustrate only typical embodiments of this disclosure and are therefore not to be considered limiting in scope, for the disclosure may apply equally well to other embodiments.
The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Some variations of the embodiments are described. Throughout the various views and illustrative embodiments, like reference numerals are used to designate like elements. It should be understood that additional operations can be provided before, during, and after the method, and some of the operations described can be replaced or eliminated for other embodiments of the method.
Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. When a spatially relative term, such as those listed above, is used to describe a first element with respect to a second element, the first element may be directly on the other element, or intervening elements or layers may be present. When an element or layer is referred to as being “on” another element or layer, it is directly on and in contact with the other element or layer.
The terms used in the present specification are merely used to describe particular embodiments, and are not intended to limit the inventive concept. An expression used in the singular encompasses the expression of the plural, unless it has a clearly different meaning in the context. In the present specification, it is to be understood that the terms such as “including,” “having,” or “comprising,” etc. are intended to indicate the existence of the features, numbers, steps, actions, components, parts, or combinations thereof disclosed in the specification, and are not intended to preclude the possibility that one or more other features, numbers, steps, actions, components, parts, or combinations thereof may exist or may be added.
The present disclosure provides a die bonding structure having a nano-twinned layer, which allows the chip to be bonded to the carrier substrate at a low temperature of about 150° C. to 350° C. to ensure the process yield and desirable bonding strength (such as higher than 20 MPa) of the power module packaging. Meanwhile, the interface cracking problem of nano-twinned direct bonding (directly inserting the nano-twinned film between the chip and the ceramic substrate) is avoided due to the existence of the sintered layer, thereby effectively improving the reliability of the packaged product. Furthermore, the adhesive layer can provide a better bonding force for preventing the nano-twinned layer from peeling from the chip and has a lattice buffering effect to reduce the impact of the lattice of the chip on the growth of the silver nano-twinned structure. In addition, undesired diffusion caused by high temperatures can be avoided, so that the diffusion barrier layer can be omitted between the adhesive layer and the nano-twinned layer while preventing the possibility of a poor bonding force between the nano-twinned layer and the diffusion barrier layer at the same time.
Referring to
Referring to
In some embodiments, the adhesive layer 104 can provide a better bonding force between the chip 102 and the nano-twinned layer 106 (as shown in
In some embodiments, the adhesive layer 104 has a lattice buffering effect. If the nano-twinned layer 106 is formed directly on the chip 102, the crystal orientation of the nano-twinned layer 106 will be influenced by the crystal orientation of the chip 102. For example, a film formed on the chip with (100) orientation is not likely to have a (111) crystal orientation. Therefore, the nano-twinned layer 106 with a high twin density can be formed on the chip 102 with the (111) orientation, and the nano-twinned structure formed on the chip 102 with the (110) orientation has an extremely low twin density. However, the adhesive layer 104 of the present disclosure allows the nano-twinned structures formed on the chip 102 with various crystal orientations due to the lattice buffering effect. Specifically, whether the crystal orientation of the chip 102 is (100), (110), or (111), the formed nano-twinned layer 106 has more than 40% crystal orientation. It should be understood that the existence of the adhesion layer 104 not only allows the formation of the nano-twinned layer 106 with the (111) crystal orientation on the chip 102 with the above-mentioned (100), (110), or (111) orientation, but also reduces the influence of the crystal orientation of other types of chips (such as SiC, GaAs, or the like) on the crystal orientation of the subsequently deposited nano-twinned layer structure.
In an embodiment, the adhesive layer 104 may include titanium (Ti), aluminum titanium (TiAl), chromium (Cr), or titanium tungsten (TiW). In an embodiment, the thickness of the adhesive layer 104 is 0.01 um to 10 um (such as 0.02 um to 0.2 um). It should be understood that the thickness of the adhesive layer 104 can be appropriately adjusted according to practical applications, but the disclosure is not limited thereto.
In some embodiments, the adhesive layer 104 may be formed by sputtering, evaporation, or electroplating. In accordance with some embodiments, the adhesive layer 104 may be formed on the chip 102 by sputtering. In some embodiments, the sputtering may use a single sputtering gun or multiple sputtering guns. In the sputtering process, the power source may be direct current (DC), DC pulse, RF, high-power impulse magnetron sputtering (HIPIMS), or the like. The power may be, for example, about 100 W to about 200 W. The processing temperature is room temperature, but during the sputtering process, it will rise by about 50° C. to about 200° C. The background pressure of the sputtering process is less than 1×10−5 torr. The working pressure may be, for example, about 1×10−3 torr to about 1×10−2 torr. The argon flow may be, for example, about 10 sccm to about 20 sccm. The rotation speed of the chuck may be, for example, about 5 rpm to about 20 rpm. The bias voltage applied to the substrate during the sputtering process is about −100V to about −200V. The deposition rate of the adhesive layer 104 may be, for example, about 0.5 nm/s to about 3 nm/s. It should be understood that the sputtering process parameters described above may be appropriately adjusted according to practical applications, and the disclosure is not limited thereto.
In accordance with other embodiments, the adhesive layer 104 may be formed on the chip 102 by evaporation coating. The background pressure of the evaporation coating process is less than 1×10−5 torr, and the working pressure of the process may be, for example, about 1×10−4 torr to about 5×10−4 torr. The argon flow may be about 2 sccm to about 10 sccm. The rotation speed of the chuck may be, for example, about 5 rpm to about 20 rpm. The evaporation coating rate of the adhesive layer 104 may be, for example, about 1 nm/s to about 5 nm/s. It should be understood that the evaporation coating process parameters described above may be appropriately adjusted according to practical applications, and the disclosure is not limited thereto.
Referring to
The formation of a twin structure is due to the accumulated strain energy inside a material. The strain energy drives uniform atomic shear to unsheared atoms at some regions inside the grain to form lattice positions that are mirror-symmetrical to each other. The twins may be annealing twins or mechanical twins. The mutually symmetrical interface is the twin boundary.
Twins are mainly formed in face centered cubic (FCC) or hexagonal closed-packed (HCP) crystalline materials with the closest lattice arrangement. In addition to the crystal structure with the closest lattice arrangement, twins are more likely formed in materials with small stacking fault energy.
Twin boundaries are coherent crystal structures and are classified as Σ3 and Σ9 special grain boundaries with low interfacial energy. The crystal orientations are all {111}. Compared with high-angle grain boundaries formed by general annealing and recrystallization, the interfacial energy of twin boundaries is about 5% of the interfacial energy of high-angle grain boundaries (George E. Dieter, Mechanical Metallurgy, MCGRAW-HILL Book Company, 1976, P. 135-141).
Due to the low interfacial energy of the twin boundaries, oxidation, sulfurization, and chloride ion corrosion may be avoided. Therefore, the silver nano-twinned thin film exhibits better resistance to oxidation and corrosion. In addition, the symmetrical lattice arrangement of twins is less likely to impede electron transportation. Therefore, the silver nano-twinned thin film exhibits better electrical and thermal conductivity. Because the twin boundaries inhibit the movement of dislocation, materials may still maintain high tensile strength. The characteristics of high tensile strength and electrical conductivity have been proven in the copper thin film. (See Ultrahigh Strength and High Electrical Conductivity in Copper, Science, vol. 304, 2004, p. 422-426 issued to L. Lu, Y. Shen, X. Chen, L. Qian, and K. Lu).
In terms of high-temperature stability, twin boundaries are more stable than high-angle grain boundaries due to the low interfacial energy of twin boundaries. Twin boundaries are less likely to move at high temperatures. Twin boundaries may have an effect on locking surrounding high-angle grain boundaries, making the high-angle grain boundaries unable to move. Therefore, the grains may not grow significantly at high temperatures, which enable the tensile strength of the material to be maintained at high temperatures.
In terms of current reliability, since atoms have a low diffusion rate when passing through twin boundaries with low interfacial energy, it is difficult to move atoms inside the wire at a high current density during operation of electronic devices. As such, the electromigration that often occurs when current passes through a wire is inhibited. It has been proven that twins can inhibit electromigration in copper thin film. (See Observation of Atomic Diffusion at Twin-Modified Grain Boundaries in Copper, Science, vol. 321, 2008, p. 1066-1069 issued to K. C. Chen, W. W. Wu, C. N. Liao, L. J. Chen, and K. N. Tu).
In an embodiment, the nano-twinned layer 106 may include silver, copper, or a silver-copper alloy. In an embodiment, the thickness of the nano-twinned layer 106 is 0.1 um to 100 um (such as 0.5 um to 10 um). If the thickness of the nano-twinned layer 106 is less than 0.1 um, the nano-twinned layer 106 may quickly react with the bonding material and is completely consumed during the subsequent bonding process, and an interfacial intermetallic compound thus formed cannot be bonded to the chip 102, resulting in interface detachment, rendering it impractical for applications. On the other hand, if the thickness of the nano-twinned layer 106 is greater than 100 um, the nano-twinned layer 106 is easily peeled from the adhesive layer 104 located on the chip 102.
In some embodiments, the nano-twinned layer 106 may be formed by sputtering, evaporation or electroplating. In accordance with some embodiments, the sputtering may use a single sputtering gun or multiple sputtering guns. In the sputtering process, the power source may be direct current (DC), DC pulse, RF, or high-power impulse magnetron sputtering (HIPIMS). The power of the sputtering of the nano-twinned layer 106 may be, for example, about 100 W to about 500 W. The processing temperature is room temperature, but during the sputtering process, it will rise by about 50° C. to about 200° C. The deposition rate of the nano-twinned layer 106 may be, for example, about 0.5 nm/s to about 3 nm/s. The background pressure of the sputtering process is less than 1×10−5 torr. The working pressure may be, for example, about 1×10−3 torr to about 1×10−2 torr. The argon flow may be, for example, about 10 sccm to about 20 sccm. The rotation speed of the chuck may be, for example, 5 rpm to 20 rpm. The bias voltage applied to the substrate during the sputtering process is about −100V to about −200V. It should be understood that the sputtering process parameters described above may be appropriately adjusted according to practical applications, and the disclosure is not limited thereto.
In accordance with other embodiments, the nano-twinned layer 106 may be formed on the adhesive layer 104 by evaporation coating. In some embodiments, the background pressure of the evaporation coating process is less than 1×10−5 torr, and the working pressure of the process may be, for example, about 1×10−4 torr to about 5×10−4 torr. The argon flow may be about 2 sccm to about 10 sccm. The rotation speed of the chuck may be, for example, about 5 rpm to about 20 rpm. The evaporation coating rate of the nano-twinned layer 106 may be, for example, about 1 nm/s to about 5 nm/s. During the evaporation process, ion bombardment is applied to the nano-twinned layer 106. The voltage is about 10V to about 300V, and the current is about 0.1 A to about 1.0 A. It should be understood that the evaporation coating process parameters described above may be appropriately adjusted according to practical applications, and the disclosure is not limited thereto.
Referring to
In an embodiment, the bonding process may include, first disposing the sintering material on the carrier substrate 110, bonding the nano-twinned layer 106 to the sintering material, and heating the sintering material to form the sintered layer 108, but the present disclosure is not limited thereto. In other embodiments, the bonding process may include, first disposing the sintering material on the nano-twinned layer 106, bonding the carrier substrate 110 to the sintering material, and heating the sintering material to form the sintered layer 108.
In some embodiments, the sintered layer 108 can be used as a buffer to prevent interface cracks caused by the direct bonding of the nano-twinned layer 106 and the carrier substrate 110, thereby effectively improving the reliability of the packaged product. In an embodiment, the sintering material may include a silver paste, a copper paste, or a copper paste covered with silver to result in a sintered layer 108 including silver, copper, or a silver-copper composite, respectively, after heating and sintering.
In an embodiment, the carrier substrate 110 may include a metal heat sink, and the metal heat sink may include aluminum or copper. In another embodiment, the carrier substrate 110 may include a printed circuit board (PCB) having a copper circuit layer and a protective layer thereon, or a ceramic substrate having the copper circuit layer and the protective layer thereon. In some embodiments, the protective layer is located on the copper circuit layer to prevent the copper circuit layer from rusting (sulfidation or oxidation) due to exposure to the atmosphere. In an embodiment, the protective layer may include an organic solderability preservative (OSP) or a metal film such as Ni, Ni/Pd, Ni/Au, Ni/Pd/Au, or the like. In an embodiment, the ceramic substrate may include aluminum oxide (Al2O3), aluminum nitride (AlN), or silicon nitride (Si3N4).
The bonding process can be performed under vacuum, a protective atmosphere, or an ambient atmosphere. In some embodiments, the bonding process is performed under a pressure of 5 MPa to 30 MPa (such as 10 MPa to 25 MPa or 15 MPa to 20 MPa) and at a temperature of 100° C. to 350° C. (such as 100° C. to 250° C., 150° C. to 200° C., or 120° C. to 180° C.). Such a pressure range can prevent damage to both the chip 102 and the nano-twinned layer 106. Although the existing techniques can perform the bonding process under a low pressure of 0.8 MPa to 3 MPa, it is necessary to perform chemical mechanical polishing (CMP) on the nano-twinned thin film before bonding to reduce the surface roughness, which not only complicates the process but also destroys the nano-twinned thin film. Under the premise of not damaging the chip 102 and the nano-twinned layer 106, the present disclosure applies a pressure of about 5 MPa to about 30 MPa (which is higher than the existing techniques) to make the protruding surface structure of the nano-twinned layer 106 undergo nano-level plastic deformation to achieve close contact. It not only solves the surface roughness problem of the nano-twinned layer 106 but also eliminates the need for additional complicated chemical mechanical polishing steps in existing techniques, which greatly improves throughput and yield, and the disclosure is not limited thereto. In other embodiments, the die bonding structure 100 can be bonded without the application of pressure.
Referring back to
Test results of Examples and Comparative Examples of the die bonding structures of the present disclosure are described below.
The structures of Comparative Example 1 and Example 1 as described above were respectively bonded with the silver paste (as the sintering layer 108) and the direct bond copper (DBC) ceramic substrate in a vacuum, and the sintering was performed under a pressure of 10 MPa or without applying pressure at various bonding temperatures (such as 150° C., 180° C., and 225° C.).
As shown in
After die bonding, the bonding strength was measured using a welding strength tester (DAGE 4000), manufactured by Nordson. The results with the application of 10 MPa of pressure are shown in Table 1 and
According to Table 1, Table 2,
As shown in
The structures of Comparative Example 2 and Example 2 as described above were used to measure the bonding strength using a welding strength tester (DAGE 4000) manufactured by Nordson. The results are shown in Table 3 and
According to Table 3 and
It should be noted that after sintering the structure of Comparative Example 2 at a bonding temperature of 150° C., its bonding strength was too low for practical use; on the contrary, the structure of Example 2 was nearly 20 MPa. In addition, after sintering the structures of Comparative Example 2 and Example 2 at a bonding temperature of 250° C., the bonding strength of Example 2 was almost twice that of Comparative Example 2.
The Si/Ti/Ni/Cu structure is a further example of the die bonding structure 200 in
The Si/Ti/nt-Cu structure is a further example of the die bonding structure 100 in
The structures of Comparative Example 3 and Example 3 as described above were respectively bonded with the silver paste (as the sintering layer 108) and the direct bond copper (DBC) ceramic substrate in a vacuum, and the sintering was performed under a pressure of 15 MPa or not and at various bonding temperatures (such as 150° C., 200° C., and 250° C.). After die bonding, the bonding strength was measured using a welding strength tester (DAGE 4000), manufactured by Nordson. The results with the application of 15 MPa of pressure are shown in Table 4 and
According to Table 4, Table 5,
Embodiments of the present disclosure have several advantageous features. The adhesive layer located between the chip and the nano-twinned layer provides a better bonding force for preventing the nano-twinned layer from peeling from the chip and has a lattice buffering effect to prevent the impact of the lattice of the chip on the growth of the silver nano-twinned structure. The present disclosure provides a die bonding structure having a nano-twinned layer, which utilizes the high diffusion rate of (111) crystal orientation of the nano-twinned to indirectly promote the progress of interface sintering reaction to assist silver- or copper-sintered die bonding for the power IC modules and the high-power LED packaging. Not only can decrease the bonding temperature as the nano-twinned direct bonding, but the bonding strength can be increased. Meanwhile, the interface cracking problem of nano-twinned direct bonding is avoided due to the presence of the sintered layer. In addition, undesired diffusion caused by high temperatures can be avoided, so that the diffusion barrier layer can be omitted between the adhesive layer and the nano-twinned layer while preventing the possibility of a poor bonding force between the nano-twinned layer and the diffusion barrier layer at the same time.
While the present disclosure has been described by way of example and in terms of the preferred embodiments, it should be understood that the present disclosure is not limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.
| Number | Date | Country | Kind |
|---|---|---|---|
| 112211673 | Oct 2023 | TW | national |
