Patent Application
20240413028
The semiconductor industry has experienced rapid growth due to ongoing improvements in the integration density of a variety of electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). For the most part, improvement in integration density has resulted from iterative reduction of minimum feature size, which allows more components to be integrated into a given area. As the demand for shrinking electronic devices has grown, a need for smaller and more creative packaging techniques of semiconductor dies has emerged.
Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
According to various embodiments, die structures each include a lower substrate, upper integrated circuit dies bonded to the lower substrate, and one or more buffer layer(s) around the upper integrated circuit dies. An encapsulant is around the buffer layer(s) and the upper integrated circuit dies. The buffer layer(s) are formed of a stress reduction compound that may help reduce stress exerted on the bonding interfaces of the upper integrated circuit dies and the lower substrate during expansion of the encapsulant at high temperatures. The yield and reliability of the die structures may thus be improved.
The integrated circuit die 50 may be formed in a wafer, which may include different device regions that are singulated to form a plurality of integrated circuit dies. The integrated circuit die 50 may be processed according to applicable manufacturing processes to form integrated circuits. For example, the integrated circuit die 50 includes a semiconductor substrate 52, which may be a substrate of silicon, doped or undoped, or an active layer of a semiconductor-on-insulator (SOI) substrate. The semiconductor substrate 52 may include other semiconductor materials, such as germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor including silicon-germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and/or gallium indium arsenide phosphide; or combinations thereof. Other substrates, such as multi-layered or gradient substrates, may also be used. The semiconductor substrate 52 has an active surface (e.g., the surface facing upward in
An interconnect structure 54 is disposed over the active surface of the semiconductor substrate 52, and is used to electrically connect the devices of the semiconductor substrate 52 to form an integrated circuit. The interconnect structure 54 may include one or more dielectric layer(s) and respective metallization layer(s) in the dielectric layer(s). The dielectric layer(s) may be, e.g., low-k dielectric layer(s). The metallization layer(s) may include conductive vias and/or conductive lines to interconnect the devices of the semiconductor substrate 52. The metallization layer(s) may be formed of a conductive material, such as a metal, such as copper, cobalt, aluminum, gold, combinations thereof, or the like. The metallization layer(s) of the interconnect structure 54 may be formed by a damascene process, such as a single damascene process, a dual damascene process, or the like.
Optionally, conductive vias 56 extend into the interconnect structure 54 and/or the semiconductor substrate 52. The conductive vias 56 are electrically coupled to the metallization layer(s) of the interconnect structure 54. As an example to form the conductive vias 56, recesses can be formed in the interconnect structure 54 and/or the semiconductor substrate 52 by, for example, etching, milling, laser techniques, a combination thereof, or the like. A thin barrier layer may be conformally deposited in the recesses, such as by chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), thermal oxidation, a combination thereof, or the like. The barrier layer may be formed of an oxide, a nitride, combinations thereof, or the like. A conductive material may be formed over the barrier layer and in the recesses. The conductive material may be formed by an electro-chemical plating process, CVD, ALD, PVD, a combination thereof, or the like. Examples of conductive materials include copper, tungsten, aluminum, silver, gold, a combination thereof, or the like. Excess conductive material and barrier layer is removed from a surface of the interconnect structure 54 or the semiconductor substrate 52 by, for example, a chemical-mechanical polish (CMP). The remaining portions of the barrier layer and conductive material in the recesses form the conductive vias 56. After their initial formation, the conductive vias 56 may be buried in the semiconductor substrate 52. The semiconductor substrate 52 may be thinned in subsequent processing to expose the conductive vias 56 at the inactive surface of the semiconductor substrate 52. After the exposure process, the conductive vias 56 are through-substrate vias (TSVs), such as through-silicon vias, that extend through the semiconductor substrate 52.
A dielectric layer 62 is over the interconnect structure 54, at the front-side of the integrated circuit die 50. The dielectric layer 62 may be formed of an oxide such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), a tetraethyl orthosilicate (TEOS) based oxide, or the like; a nitride such as silicon nitride or the like; a polymer such as polybenzoxazole (PBO), polyimide, a benzocyclobutene (BCB) based polymer, or the like; a combination thereof; or the like. The dielectric layer 62 may be formed, for example, by CVD, spin coating, lamination, or the like. Optionally, one or more passivation layer(s) (not separately illustrated) are disposed between the dielectric layer 62 and the interconnect structure 54.
Die connectors 64 extend through the dielectric layer 62. The die connectors 64 may include conductive pillars, pads, or the like, to which external connections can be made. In some embodiments, the die connectors 64 include bond pads at the front-side of the integrated circuit die 50, and include bond pad vias that connect the bond pads to an upper metallization layer of the interconnect structure 54. In such embodiments, the die connectors 64 (including the bond pads and the bond pad vias) may be formed by a damascene process, such as a single damascene process, a dual damascene process, or the like. The die connectors 64 may be formed of a suitable conductive material, such as copper, tungsten, aluminum, silver, gold, a combination thereof, or the like, which can be formed by, for example, plating or the like.
Optionally, solder regions (not separately illustrated) may be disposed on the die connectors 64 during formation of the integrated circuit die 50. The solder regions may be used to perform chip probe (CP) testing on the integrated circuit die 50. For example, the solder regions may be solder balls, solder bumps, or the like, which are used to attach a chip probe to the die connectors 64. Chip probe testing may be performed on the integrated circuit die 50 to ascertain whether the integrated circuit die 50 is a known good die (KGD). Thus, only integrated circuit dies 50, which are KGDs, undergo subsequent processing are packaged, and dies which fail the chip probe testing are not packaged. After testing, the solder regions may be removed. In some embodiments, a planarization process such as a chemical mechanical polish (CMP), an etch-back process, combinations thereof, or the like is utilized.
A die structure 100 (see
In
The wafer 110 may be processed according to applicable manufacturing processes to form devices. For example, the wafer no includes a substrate 112, an interconnect structure 114, conductive vias 116, a dielectric layer 122, and die connectors 124, which may be similar to, respectively, the semiconductor substrate 52, the interconnect structure 54, the conductive vias 56, the dielectric layer 62, and the die connectors 64 (previously described for
In
The integrated circuit dies 50 are directly bonded to the wafer 110. In this embodiment, the integrated circuit dies 50 and the wafer 110 are directly bonded in a face-to-face manner, such that the front-sides of the integrated circuit dies 50 are bonded to the front-side of the wafer 110. The integrated circuit dies 50 may be bonded to the wafer 110 by hybrid bonding. In hybrid bonding, the dielectric layers 62 of the integrated circuit dies 50 are bonded to the dielectric layer 122 of the wafer 110 through dielectric-to-dielectric bonding, without using any adhesive material (e.g., die attach film), and the die connectors 64 of the integrated circuit dies 50 are bonded to the die connectors 124 of the wafer 110 through metal-to-metal bonding, without using any eutectic material (e.g., solder). The bonding may include a pre-bonding and an annealing. During the pre-bonding, a small pressing force is applied to press the integrated circuit dies 50 against the wafer 110. The pre-bonding is performed at a low temperature, such as room temperature, and after the pre-bonding, the dielectric layers 62 are bonded to the dielectric layer 122. The bonding strength is then improved in a subsequent annealing step, in which the dielectric layers 62, 122 are annealed at a high temperature, such as a temperature in the range of about 150° C. to about 300° C. The annealing forms bonds, such as fusions bonds, that bond the dielectric layers 62 to the dielectric layer 122. For example, the bonds can be covalent bonds between the material of the dielectric layers 62 and the material of the dielectric layer 122. The die connectors 64 are connected to the die connectors 124 with a one-to-one correspondence. The die connectors 64 may be in physical contact with the die connectors 124 after the pre-bonding, or may expand to be brought into physical contact during the annealing. Further, during the annealing, the material of the die connectors 64, 124 (e.g., copper) intermingles, so that metal-to-metal bonds are also formed. Hence, the resulting bonds between the integrated circuit dies 50 and the wafer 110 include both dielectric-to-dielectric bonds and metal-to-metal bonds.
In
The buffer layers 132 are formed of a stress reduction compound that helps reduce stress exerted on the bonding interfaces of the integrated circuit dies 50 and the wafer 110. The stress reduction compound includes a polymer material and optionally includes a filler. The polymer material may be a polyester, a polyamide, a polycarbonate, a polyurethane, or the like. For example, the polymer material may be a thermoplastic polymer such as polyethylene terephthalate. The filler is formed of a material that provides mechanical strength for the buffer layers 132, such as particles of silica (SiO2). The stress reduction compound may be applied in liquid or semi-liquid form by deposition (e.g., CVD), capillary flow, lamination, or the like, and then subsequently cured.
The buffer layers 132 may have fillet portions 132F and gap portions 132G. The gap portions 132G are disposed in the gaps between the integrated circuit dies 50 within the respective package regions 110P. The fillet portions 132F are disposed along the outer edges of the integrated circuit dies 50 within the respective package regions 110P, and include fillets.
A liner layer 130 may be formed between the buffer layers 132 and the integrated circuit dies 50 and the wafer 110. The liner layer 130 may protect the various components from moisture that is released during a subsequent encapsulation process, which may increase the reliability of the die structures 100. The liner layer 130 may be formed of a dielectric material such as a nitride (e.g., silicon nitride), an oxide (e.g., silicon oxide), combinations thereof (e.g., silicon oxynitride), multi-layers thereof, or the like, which may be formed by a suitable deposition method such as ALD, CVD, or the like. The dielectric material may be inorganic. In some embodiments, the liner layer 130 includes an oxide layer and a nitride layer over the oxide layer, which may be advantageous when the nitride layer has a large hardness. In some embodiments, the liner layer 130 has a thickness in the range of 0.2 μm to 0.4 μm.
In this embodiment, the buffer layers 132 are formed on the liner layer 130. Thus, the liner layer 130 physically contacts the sidewalls of the integrated circuit dies 50 and the top surface of the wafer 110, while the buffer layers 132 physically contacts the sidewalls and top surfaces of the liner layer 130. The liner layer 130 is optional. In another embodiment (subsequently described for
In
The CTE of the integrated circuit dies 50 may be largely determined by the CTE of the semiconductor substrates 52, which are formed of a semiconductor material. The encapsulant 134 surrounds and protects the integrated circuit dies 50. However, the molding compound of the encapsulant 134 has a large CTE as compared to the semiconductor material of the integrated circuit dies 50. As a result, the encapsulant 134 may expand more than the integrated circuit dies 50 at high temperatures. Expansion of the encapsulant 134 at high temperatures can exert stress on the bonding interfaces of the integrated circuit dies 50 and the wafer 110. The buffer layers 132 are formed of a stress reduction compound that may reduce stress exerted on those bonding interfaces as a result of CTE mismatch. Specifically, the CTE of the stress reduction compound of the buffer layers 132 is between the CTE of the molding compound of the encapsulant 134 and the CTE of the semiconductor material of the integrated circuit dies 50. In other words, the CTE of the stress reduction compound of the buffer layers 132 is greater than the CTE of the semiconductor material of the integrated circuit dies 50, while the CTE of the molding compound of the encapsulant 134 is greater than the CTE of the stress reduction compound of the buffer layers 132. In some embodiments, the semiconductor material of the integrated circuit dies 50 has a CTE in the range of 2 ppm/° C. to 3 ppm/° C., the stress reduction compound of the buffer layers 132 has a CTE in the range of 5 ppm/° C. to 20 ppm/° C., and the molding compound of the encapsulant 134 has a CTE in the range of 30 ppm/° C. to 40 ppm/° C. Thus, the buffer layers 132 may reduce stress caused by a CTE mismatch between the encapsulant 134 and the integrated circuit dies 50, which may reduce the risk of the dielectric layers 62, 122 delaminating (specifically, at the edges of the integrated circuit dies 50). The yield and reliability of the die structures 100 may thus be improved.
As previously noted, the stress reduction compound of the buffer layers 132 optionally includes a filler. When a filler is used, the CTE of the stress reduction compound may be tuned to a desired amount by controlling the filler type (e.g., material), filler load (e.g., quantity of filler), and/or average filler particle size. In some embodiments where the stress reduction compound of the buffer layers 132 includes a filler, the filler is particles of silica having a load in the range of 60% to 90% and having an average particle size in the range of 5 μm to 30 μm. Thus, the stress reduction compound may be formed with a desired CTE (previously described).
In
The encapsulant 134 may have edge portions 134E and gap portions 134G. The gap portions 134G are disposed in the gaps between the integrated circuit dies 50 within the respective package regions 110P, e.g., over the gap portions 132G of the buffer layers 132. The edge portions 134E are disposed along the outer edges of the integrated circuit dies 50 within the respective package regions 110P, e.g., over the fillet portions 132F of the buffer layers 132. In some embodiments, the gap portions 134G of the encapsulant 134 remaining after the removal process have a thickness in the range of 0 μm to 40 μm. More generally, the gap portions 134G of the encapsulant 134 may (or may not) remain after the removal process. In this embodiment, the gap portions 134G of the encapsulant 134 remain after the removal process. Thus, the gap portions 132G of the buffer layers 132 are below the top surface of the encapsulant 134. In another embodiment (subsequently described for
The liner layer 130 (if present) and the integrated circuit dies 50 are exposed through the encapsulant 134 while the fillet portions 132F of the buffer layers 132 remain covered by the encapsulant 134. Thus, the thickness of the encapsulant 134 is greater than the thickness of the fillet portions 132F of the buffer layers 132. In some embodiments, the thickness of the encapsulant 134 is in the range of 300 μm to 500 μm, such as about 400 μm, while the thickness of the fillet portions 132F of the buffer layers 132 is in the range of 210 μm to 350 μm, such as about 280 μm. The thickness of the fillet portions 132F of the buffer layers 132 may be at least half the thickness of the encapsulant 134. Additionally, the thickness of the gap portions 132G of the buffer layer 132 may (or may not) be greater than the thickness of the fillet portions 132F of the buffer layer 132. The thicknesses of the buffer layers 132 and the encapsulant 134 are measured in a direction that is perpendicular to a major surface of the wafer 110.
In
In
In
The dielectric layer(s) 142 are formed of suitable dielectric material(s). In some embodiments, the dielectric layer(s) 142 are formed of a polymer, which may be a photosensitive material such as PBO, polyimide, a BCB-based polymer, or the like, which may be patterned using a lithography mask. In other embodiments, the dielectric layer(s) 142 are formed of an oxide such as silicon oxide, PSG, BSG, BPSG; a nitride such as silicon nitride; a combination thereof such as silicon oxynitride; or the like. The dielectric layer(s) 142 may be formed by spin coating, lamination, CVD, the like, or a combination thereof. After each dielectric layer 142 is formed, it is then patterned to expose underlying conductive features, e.g. underlying portions of the conductive vias 116 or the metallization layer(s) 144. The patterning may be by an acceptable process, such as by exposing the dielectric layer 142 to light when it is a photosensitive material, or by etching using, for example, an anisotropic etch. If the dielectric layer 142 is formed of a photosensitive material, it can be developed after the exposure.
The metallization layer(s) 144 each include conductive vias and/or conductive lines. The conductive vias extend through the dielectric layer(s) 142, and the conductive lines extend along the dielectric layer(s) 142. As an example to form a metallization layer 144, a seed layer (not separately illustrated) is formed over the respective underlying features. For example, the seed layer can be formed on a respective dielectric layer 142 and in the openings through the respective dielectric layer 142, or can be formed on the conductive vias 116 and the insulating layer 126 (if present) or the substrate 112. In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer including a plurality of sub-layers formed of different materials. In some embodiments, the seed layer includes a titanium layer and a copper layer over the titanium layer. The seed layer may be formed using a deposition process, such as PVD or the like. A photoresist is then formed and patterned on the seed layer. The photoresist may be formed by spin coating or the like and may be exposed to light for patterning. The pattern of the photoresist corresponds to the metallization layer 144. The patterning forms openings through the photoresist to expose the seed layer. A conductive material is formed in the openings of the photoresist and on the exposed portions of the seed layer. The conductive material may be formed by plating, such as electroplating or electroless plating, or the like. The conductive material may include a metal or a metal alloy, such as copper, titanium, tungsten, aluminum, the like, or combinations thereof. Then, the photoresist and portions of the seed layer on which the conductive material are not formed are removed. The photoresist may be removed by an acceptable ashing or stripping process, such as using an oxygen plasma or the like. Once the photoresist is removed, exposed portions of the seed layer are removed, such as by an acceptable etching process, such as by wet or dry etching. The remaining portions of the seed layer and conductive material form the metallization layer 144.
When the substrate 112 is thinned, the redistribution structure 140 and the wafer 110 may have small combined thickness. In some embodiments, the combined thickness of the redistribution structure 140 and the wafer 110 is in the range of 50 μm to 80 μm, such as less than about 100 μm. The combined thickness of the redistribution structure 140 and the wafer 110 may be less than the thickness of the encapsulant 134.
Optionally, additional features may be formed for attaching the die structures 100 to package components. In some embodiments, under bump metallurgies (UBMs) 146 are formed for external connection to the redistribution structure 140. Further, conductive connectors 148 may be formed on the UBMs 146. The conductive connectors 148 may be used to connect the UBMs 146 to a package component such as an interposer, a package substrate, or the like.
The UBMs 146 may be formed through a lower dielectric layer 142 of the redistribution structure 140. The UBMs 146 have bump portions on and extending along the major surface of the lower dielectric layer 142, and have via portions extending through the lower dielectric layer 142 to physically and electrically couple the lower metallization layer 144 of the redistribution structure 140. As a result, the UBMs 146 are electrically coupled to the conductive vias 116 and the integrated circuit dies 50. The UBMs 146 may be formed of the same material(s) as the metallization layer(s) 144. In some embodiments, the UBMs 146 have a different size than the metallization layer(s) 144.
The conductive connectors 148 may be formed on the UBMs 146. The conductive connectors 148 may be ball grid array (BGA) connectors, solder balls, metal pillars, controlled collapse chip connection (C4) bumps, micro bumps, electroless nickel-electroless palladium-immersion gold technique (ENEPIG) formed bumps, or the like. The conductive connectors 148 may include a conductive material such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, the like, or a combination thereof. In some embodiments, the conductive connectors 148 are formed by initially forming a layer of a reflowable material (e.g., solder) through evaporation, electroplating, printing, solder transfer, ball placement, or the like. Once a layer of solder has been formed on the structure, a reflow may be performed in order to shape the material into the desired bump shapes. In another embodiment, the conductive connectors 148 include metal pillars (such as copper pillars) formed by a sputtering, printing, electro plating, electroless plating, CVD, or the like. The metal pillars may be solder-free and have substantially vertical sidewalls. In some embodiments, a metal cap layer is formed on the top of the metal pillars. The metal cap layer may include nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, the like, or a combination thereof, which may be formed by a plating process.
In
In
In this embodiment, the dies of the die structure 100 are directly bonded in a face-to-face manner, such that the front-sides of the integrated circuit dies 50 are bonded to the front-side of the lower device 150. Thus, the lower device 150 includes conductive vias 116, and the redistribution structure 140 is on the back-side of the lower device 150. In another embodiment (subsequently described for
The gap portion 132G of the buffer layer 132 has a width W1, measured between the integrated circuit dies 50. The fillet portion 132F of the buffer layer 132 has a length L1, measured from an edge of an integrated circuit die 50 to an edge of the buffer layer 132. In some embodiments, the width W1 is in the range of 40 μm to 100 μm, while the length L1 is in the range of 100 μm to 300 μm. Each of the integrated circuit dies 50 is disposed a distance D1 from the edges of the die structure 100 (e.g., from the edges of the encapsulant 134). The distance D1 is large, which provides space for dispensing the buffer layer 132. In some embodiments, the distance D1 is in the range of 300 μm to 500 μm, such as about 500 μm. As a result, the buffer layer 132 may not be sawed/cut during singulation of the die structure 100 (previously described for
The buffer layers 132 may include outer buffer layers 132A and inner buffer layer(s) 132B. The outer buffer layers 132A are disposed along the outer edges of the integrated circuit dies 50, such as around the outer corners of the integrated circuit dies 50. The inner buffer layer(s) 132B are disposed in the gap(s) between the integrated circuit dies 50. In this embodiment, the outer buffer layers 132A lack fillets. In another embodiment (not separately illustrated), the outer buffer layers 132A include fillets. The outer buffer layers 132A may (or many not) have a different thickness than the inner buffer layer(s) 132B. For example, the inner buffer layer(s) 132B may have a greater thickness than the outer buffer layers 132A. In some embodiments, the outer buffer layers 132A have a thickness in the range of 100 μm to 200 μm, while the inner buffer layer(s) 132B have a thickness in the range of 150 μm to 400 μm.
The inner buffer layer(s) 132B have a width W1, which may (or may not) be similar to that previously described for
Generally, the previously described die structures 100 include a plurality of upper integrated circuit dies bonded to a lower substrate. The lower substrate may be a lower device 150 (e.g., an integrated circuit die, interposer, or the like) or may be a redistribution structure 140. In some embodiments where the lower device 150 is an integrated circuit die, the die structure 100 includes a plurality of upper integrated circuit dies bonded to a lower integrated circuit die. In some embodiments where the lower device 150 is an interposer, the die structure 100 includes a plurality of upper integrated circuit dies bonded to an interposer. In some embodiments where the lower device 150 is omitted, the die structure 100 includes a plurality of upper integrated circuit dies bonded to a redistribution structure. The buffer layer(s) 132 are around the upper integrated circuit dies.
The previously described die structures 100 are components that may be subsequently implemented in an integrated circuit package. The integrated circuit dies of a die structure 100 may be heterogeneous dies. Packaging the die structure 100 in lieu of or in addition to packaging dies individually may allow heterogeneous dies to be integrated with a small footprint. In some embodiments, an integrated circuit package is formed by encapsulating the die structure 100 and forming redistribution lines on the encapsulant to fan-out connections from the die structure 100. In some embodiments, an integrated circuit package is formed by attaching a die structure 100 to an additional component, such as an interposer, a package substrate, or the like.
In the illustrated embodiment, the die structure 100 is attached to the package component 202 with the conductive connectors 148. Die connectors 204 are at the front-side of the package component 202. The conductive connectors 148 are reflowed to attach the UBMs 146 of the die structure 100 to the die connectors 204 of the package component 202. The encapsulant 134 may expand during the reflowing process as a consequent of its large CTE. The buffer layer 132 reduces stress exerted on the bonding interfaces of the integrated circuit dies 50 and the wafer 110 by the encapsulant 134 during the reflowing process.
An underfill 206 may be formed around the conductive connectors 148, and between the package component 202 and the die structure 100. The underfill 206 may be formed by a capillary flow process after the die structure 100 is attached or may be formed by a suitable deposition method before the die structure 100 is attached. The underfill 206 may be a continuous material extending from the package component 202 to the die structure 100. The material of the underfill 206 is different from the stress reduction compound of the buffer layer 132, and may be formed by a different method than the stress reduction compound of the buffer layer 132.
An encapsulant 208 is formed on and around the various components. The encapsulant 208 encapsulates the die structure 100. The encapsulant 208 may be a molding compound, epoxy, or the like. The encapsulant 208 may be applied by compression molding, transfer molding, or the like. The encapsulant 208 may be applied in liquid or semi-liquid form and then subsequently cured.
Embodiments may achieve advantages. The encapsulant 134 has a large CTE as compared to that of the integrated circuit dies 50, such that there may be a CTE mismatch between the encapsulant 134 and the integrated circuit dies 50. The buffer layers 132 may reduce stress exerted on the bonding interfaces of the integrated circuit dies 50 and the wafer 110 as a result of CTE mismatch. Specifically, the buffer layers 132 are formed of a stress reduction compound, which has a CTE that is greater than the CTE of the semiconductor material of the integrated circuit dies 50, and is less than the CTE of the molding compound of the encapsulant 134. Thus, the buffer layers 132 may reduce the risk of the dielectric layers 62, 122 delaminating during expansion of the encapsulant 134 at high temperatures. The yield and reliability of the die structures 100 may thus be improved. In an experiment, the buffer layers 132 reduced stress exerted on the bonding interfaces of the integrated circuit dies 50 and the wafer 110 by about 32%.
In an embodiment, a device includes: a lower substrate; upper integrated circuit dies bonded to the lower substrate with dielectric-to-dielectric bonds and with metal-to-metal bonds, the upper integrated circuit dies including a semiconductor material; a buffer layer around the upper integrated circuit dies, the buffer layer including a stress reduction compound, a coefficient of thermal expansion of the stress reduction compound being greater than a coefficient of thermal expansion of the semiconductor material; and an encapsulant around the buffer layer and the upper integrated circuit dies, the encapsulant including a molding compound, a coefficient of thermal expansion of the molding compound being greater than the coefficient of thermal expansion of the stress reduction compound. In some embodiments of the device, the buffer layer physically contacts sidewalls of the upper integrated circuit dies. In some embodiments, the device further includes: a liner layer between the buffer layer and the upper integrated circuit dies. In some embodiments of the device, a gap portion of the buffer layer is between the upper integrated circuit dies, a gap portion of the encapsulant is between the upper integrated circuit dies, and the gap portion of the encapsulant is over the gap portion of the buffer layer. In some embodiments of the device, a gap portion of the buffer layer is between the upper integrated circuit dies, and the gap portion of the buffer layer is exposed through the encapsulant. In some embodiments of the device, front-sides of the upper integrated circuit dies are bonded to a front-side of the lower substrate. In some embodiments of the device, front-sides of the upper integrated circuit dies are bonded to a back-side of the lower substrate. In some embodiments of the device, the buffer layer extends continuously around each of the upper integrated circuit dies in a planar view. In some embodiments of the device, the buffer layer is one of a plurality of buffer layers that extend discontinuously around the upper integrated circuit dies in a planar view. In some embodiments of the device, the lower substrate is a lower integrated circuit die. In some embodiments of the device, the lower substrate is an interposer. In some embodiments of the device, the lower substrate is a redistribution structure.
In an embodiment, a device includes: a lower substrate; an upper integrated circuit die bonded to the lower substrate with dielectric-to-dielectric bonds and with metal-to-metal bonds; a liner layer on a sidewall of the upper integrated circuit die and a top surface of the lower substrate; a buffer layer on the liner layer; and an encapsulant around the buffer layer, a top surface of the encapsulant being coplanar with a top surface of the liner layer and a top surface of the upper integrated circuit die. In some embodiments of the device, the liner layer includes an oxide layer and a nitride layer on the oxide layer. In some embodiments of the device, the buffer layer includes a stress reduction compound, and the stress reduction compound includes a polymer material and a filler. In some embodiments of the device, the polymer material is a thermoplastic polymer and the filler is particles of silica.
In an embodiment, a method includes: bonding an upper integrated circuit die to a lower substrate with dielectric-to-dielectric bonds and with metal-to-metal bonds, the upper integrated circuit die having a first coefficient of thermal expansion; forming a stress reduction compound around the upper integrated circuit die, the stress reduction compound having a second coefficient of thermal expansion; forming a molding compound around the stress reduction compound, the molding compound having a third coefficient of thermal expansion, the second coefficient of thermal expansion being between the first coefficient of thermal expansion and the third coefficient of thermal expansion; and singulating the molding compound and the lower substrate. In some embodiments of the method, forming the stress reduction compound includes depositing the stress reduction compound with chemical vapor deposition. In some embodiments, the method further includes: depositing a liner layer on the upper integrated circuit die and the lower substrate, the stress reduction compound formed on the liner layer. In some embodiments, the method further includes: thinning the molding compound, a thickness of the molding compound being greater than a thickness of a fillet portion of the stress reduction compound, the fillet portion of the stress reduction compound disposed along an outer edge of the upper integrated circuit die.
The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.
This application claims the benefit of U.S. Provisional Application No. 63/507,197, filed on Jun. 9, 2023, which application is hereby incorporated herein by reference.
| Number | Date | Country | |
|---|---|---|---|
| 63507197 | Jun 2023 | US |
