Patent Application
20240387336
Implementations of the present disclosure relate to apparatus, systems, and methods of digitalized interconnect redistribution enabled chiplet packaging, for example to provide a better area and line input/output density than a 2.5D interposer method, 2D fan-out packaging method, and 2.3D silicon bridge method.
Electronic devices, such as are included in tablets, computers, copiers, digital cameras, smart phones, control systems, and automated teller machines, among others, often include integrated circuit die(s) for some desired functionality. A heterogeneous integration module (HIM) (which may also be referred to or be a type of multi-chip module (MCM)) is a type of microelectronics device that integrates multiple different chips, materials, components, and/or technologies into a single compact package. This approach allows designers to create more complex and powerful systems by integrating different components, without the need for full system-on-chip integration. For example, this type of device aims to provide a high level of functionality and performance while also reducing the overall size, cost, and complexity of the system. HIMs devices are commonly used in a wide range of applications, including smartphones, wearable devices, and internet of things (IoT) devices, as well as in various fields such as telecommunications, computing, and robotics. They are designed to overcome the limitations of traditional microelectronics devices, which often rely on a single technology or material, by bringing together complementary components and technologies in a single, integrated package. Some examples of HIMS devices include multi-layer microelectronics packages, system-in-package (SiP) devices, and 2D and 3D integrated circuits (3D ICs). These devices can offer improved performance, higher functional density, and better thermal management compared to traditional microelectronics devices. However, combining different components into a single component package can lead to alignment and other integration issues, requiring relatively larger interconnect pitch, resulting in higher interconnect resistivity, or both.
According to one or more embodiments, a method of forming a multichip module includes molding a set of chips in a medium to secure each chip relative to each other chip, mapping a position and orientation of the chips within the molded set of chips based on alignment marks disposed on each chip within the molded set of chips, forming an interconnect substrate including forming a first interconnect layer over a base substrate, patterning the first interconnect layer to include a first plurality of patterned vias that are patterned based at least in part on the mapping, and bonding the interconnect substrate the multichip module, wherein bonding comprises positioning and aligning the interconnect substrate to the molded set of chips such that interconnects of each chip within the molded set of chips are aligned with the first plurality of patterned vias formed in the interconnect substrate.
According to one or more embodiments, a method of forming a multichip module includes forming a set of alignment marks on a set of dies to be integrated into a multichip module, the set of dies comprising a first die unit comprising first dies and a second die unit comprising second dies, each die having at least one alignment mark, molding the set of dies in a medium to secure each die relative to each other die, mapping each alignment mark of each die in the set of dies that are molded in the medium, forming an interconnect substrate including forming a first interconnect layer over a base substrate, patterning the first interconnect layer to include a first plurality of patterned vias that are patterned based at least in part on the mapping, and dicing the interconnect substrate into individual interconnect substrate units including a first interconnect substrate unit corresponding to the first die unit and a second interconnect substrate unit corresponding to the second die unit, and bonding the first interconnect substrate unit to the first die unit and the second interconnect substrate unit to the second die unit.
According to one or more embodiments, a packaged multichip module includes a set of chips molded in a medium, each chip having at least one alignment mark, and an interconnect substrate bonded to the set of chips, the interconnect substrate comprising a first interconnect layer formed over a base substrate, and a first plurality of patterned vias formed through the base substrate and the first interconnect layer that are patterned based on a position and orientation of the chips determined based at least in part on a mapping of each alignment mark.
So that the manner in which the above-recited features of the disclosure can be understood in detail, a more particular description of the disclosure, briefly summarized above, may be had by reference to implementations, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only common implementations of this disclosure and are therefore not to be considered limiting of its scope, for the disclosure may admit to other equally effective implementations.
To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements disclosed in one or more implementations may be beneficially utilized on other implementations without specific recitation.
A multichip module (MCM) (or heterogeneous integration module (HIM)) may incorporate a number of semiconductor devices formed on or in a substrate (e.g., chips or chiplets). Examples of interconnection types used for HIMs include 2D fan-out type, 2.3D silicon bridge type, and 2.5D performance gap type.
A 2D fan-out packaging is a type of chip packaging technology that allows multiple chips or dies to be integrated onto a single package using a 2D layout. In this approach, the dies are mounted on a substrate, which is then molded with an insulating material to create a flat surface. The substrate is then etched to create a pattern of electrical interconnects, which connect the dies to each other and to the package's external pins. This packaging technique may allow for increased integration density and reduced form factor, as well as improved thermal performance due to the use of a thin and uniform package. Additionally, 2D fan-out packaging can offer better electrical performance compared to traditional packaging methods such as wire bonding, as the shorter interconnects and reduced parasitics can result in faster signal propagation and lower power consumption.
2.3D Si Bridge packaging is a type of semiconductor packaging technology that enables the integration of multiple dies or chips on a single package using a 2.5D or 3D layout. This approach involves using a silicon interposer or “bridge” that provides high-density electrical connections between the dies and other components, such as memory or sensors. In a 2.3D Si Bridge package, the interposer is thinned down to reduce the distance between the dies and minimize electrical parasitics, resulting in improved performance and power efficiency. This approach can also enable the use of heterogeneous integration, where different types of dies or technologies can be integrated on the same package. 2.3D Si Bridge packaging can offer a range of benefits, including increased performance, higher integration density, reduced power consumption, and improved thermal management, making it an attractive solution for high-performance computing, AI, and other advanced applications.
A multichip module that uses a 2.5D interposer is a type of electronic package that combines multiple chips or dies, that each may be fabricated using different processes and technologies, into a single module. In a 2.5D module, the individual dies are mounted on a silicon or organic interposer, which serves as a bridge between the dies and provides electrical and thermal connections.
In some cases, 2D fan out (X-Y) line space limits are at (2/2 um-5/5 um), which is typically not far from the line patterning capability of a system, but may present concerns of long-term reliability (e.g., on an organic dielectric) due to wafer/substrate global coefficient of thermal expansion (CTE) mismatch by and between one or more wafers and the substrate, CTE being the measure of the ability of a material to expand or contract with temperature changes. This problem may be especially acute for cross multi-die space areas.
In some cases, 2.3D (silicon (Si) Bridge) and 2.5D interposer type approaches use solder bumps (e.g., copper pillar (Cu-Pillar) solder bumps). Such solder bumps are typically associated with a higher electrical resistance than a direct Cu junction. The input/output area density is limited by solder bump pitch.
Embodiments of the present disclosure relate to apparatus, systems, and methods of digitalized interconnect redistribution enabled chiplet packaging, for example to provide a better area and line input/output density than a 2.5D interposer method, 2D fan-out packaging method, and 2.3D silicon bridge method. It is also believed that the disclosed packaging structure and methods provided herein will also provide a lower electrical resistance than 2.5D & 2.3D packaging and better packaging process-induced stress management from a localized direct CTE-compatible RDL stack scheme from traditional 2-D packaging.
One or more embodiments disclosed herein include a method of forming a multichip module, including forming a set of alignment marks on a set of chips to be integrated into a multichip module, each chip having at least one alignment mark, molding the set of chips in a medium to secure each chip relative to each other chip, mapping each alignment mark of for a corresponding chip of the set of chips that are molded in the medium, forming an interconnect substrate having a plurality of vias that are based at least in part on the mapping, and bonding the interconnect substrate to the medium having the molded set of chips.
In some embodiments, the multichip module 200 includes an interconnect structure and associated semiconductor devices (e.g., chiplets, including Active, Passive, or Electrical path chiplets) during formation of the multichip module. In some examples, the formed multichip module 200 may be or be referred to as digitalized interconnect redistribution enabled chiplet packaging.
At operation 302, a set of alignment marks 216 are formed on each chip of a set of chips to be integrated into multichip module 200 (
At operation 304 each chip of the set of chips are positioned and then molded into a medium to secure each chip relative to each other chip. In one example, operation 304 includes the operations shown in
The set of dies, including both the first type and second type, are adhered to the temporary carrier 202 (and tape 201) “face down” such that the pads or interconnects 203 of the dies contact face toward the temporary carrier 202. In some embodiments, the set of dies are arranged in separate die units across the surface of the temporary carrier 202, such as generally illustrated in
At operation 306, each of the alignment marks 216 of the molded set of dies are mapped by use of an optical inspection system that includes a camera and a system controller that includes a processor (CPU), nonvolatile memory and I/O components. For example, position and orientation information of the molded set of dies is determined based on the mapping of the alignment marks 216. The molded set of dies (i.e. chips) having the alignment marks 216 are scanned, analyzed and stored in memory of a system controller. Each chip (die) shift and orientation is scanned and recorded, for example in a graphic data system (GDS) file. In one or more embodiments, all digital map input and fiducial correction information is computed and consolidated at device level test as a file (e.g., GDS file) for separated interposer patterning use. As such, in some embodiments, the alignments marks 216 are die level alignment marks for use with a digital lithography technology (DLT) patterning process.
Some more of the advantages of this approach include that there is no reticle size limit on the interconnection pattern. Also, the digitalized interconnect redistribution substrate unit manufacturing process can be also decoupled from a single substrate manufacturing batch sequence and thus substrate units can be produced with other types of multiple-chiplet unit substrates as needed, which will provide additional manufacturing flexibility. In some embodiments, the recorded GDS file can also be reused in cases where the process needs to be repeated, or the data can be further pattern optimized through the substrate via interconnect and chiplet top metal patterning mapping. Moreover, it is easy to scale up the described operations to cover full multiple chiplet connection module, or both.
At operation 308, an interconnect substrate 218 (which may also be referred to as a direct interconnect land substrate (DILS)) is formed based on the scanned set of dies (i.e., the mapping). The interconnect substrate 218 is bonded to the multichip module 200 (i.e., the molded set of chips). The operations for forming the interconnect substrate 218 are illustrated in
In one or more examples, the base substrate 222 and the first interconnect layer 220 are etched in a pattern that is defined by the mapping process, as discussed in relation to operation 306.
In one or more embodiments, the interconnect substrate 218 is etched according to a pattern to form the first plurality of patterned vias 224 that are positioned and aligned based on their relative position and orientation variation within each of the die units, as determined by the data (position and orientation information) collected from the scanning process (i.e., the mapping during operation 306) discussed above in relation to
In some embodiments, the first interconnect layer 220 and the direct interconnection portions (direct connection layers), such as the base substrate 222, are etched prior to attachment to the molded set of dies. In other embodiments, one or more interconnect layers can be formed on the first interconnect layer 220 of the interconnect substrate 218 that is attached to the molded set of dies at a later step in the processing sequence (e.g., see
In one or more embodiments, a base substrate thinning process is performed. In some embodiments, the base substrate thinning process is performed before the first plurality of patterned vias 224 are etched. In other embodiments, the base substrate thinning process is performed after the first plurality of patterned vias 224 are etched. In one or more embodiments, the base substrate thickness can be modulated.
In one or more examples, the interconnect substrate 218 is then diced into individual interconnect units, as shown by the formation of a separating feature 247.
The interconnect substrate 218 may be aligned so that each individual interconnect unit is attached to the corresponding die unit. Stated differently the interconnect substrate 218 is aligned so that the interconnects 203 on each die (i.e. chip) in the molded set of dies (i.e., the set of chips) are aligned the first plurality of patterned vias 225.
The interconnect substrate 218 is then attached (bonded) to the molded set of dies (i.e., the multichip module 200) based on the alignment of the interconnect substrate units.
Next, the first plurality of patterned vias 224 are filled to form a first plurality of metal interconnects 225a.
In some embodiments, the connection between the interconnect substrate 218 (interposer) vias and the contacts of the chiplets (e.g., the pads of the chiplet, die or chip), which are not a solder interface, have a superior Cu line to Cu via interface connection (e.g., lowered resistivity) than prior conventional solder techniques. In some embodiments, the via density (input/output (I/O) area density is equal to or denser than prior techniques (e.g., a traditional 2.5D through substrate via (TSV) interposer approach). In some embodiments, the RDL line density is at least equal to Si interposer or Si bridge level, for example due to a similar rigid interconnect substrate (e.g., DILS substrate) flatness.
At operation 310, additional interconnect layers having interconnects that are tailored to both the first plurality of metal interconnects 225a and to be attached stacked chips may be formed over the first interconnect layer 220. In another example, the additional interconnect layers may be formed before the interconnect substrate 218 is attached to the molded set of dies.
In one or more embodiments, the second interconnect layer 230 are a second RDL layer structure. In other embodiments the second interconnect layer 230 is a C4/Cu pillar layer. The second interconnect layer 230 be added after via formation of the interconnect substrate, for example for next level substrate integration. In one or more embodiments, prior to attaching the second interconnect layer 230, an inter-die fill can be applied to (formed on) the interconnect substrate (e.g., as illustrated in
In one or more embodiments, the second interconnect layer 230 include a second interconnect substrate (e.g., which may be or be referred to as a second direct interconnect land interposer (DILI) herein, and the first interconnect layer also be or be referred to as a first DILI). The vias of the interconnect layer (e.g., interposer, DILI) can be form a connection to the chiplets without a solder interface, which can provide a superior copper line to copper via interface (e.g., more reliable, lower resistivity). In some embodiments, after the second interconnect layer 230 are attached, metalized traces of an interconnect layer on top of the second interconnect layer 230 can be processed (e.g., by a DLT tool) according to a file including die shift and orientation information (e.g., a second GDS file, or a second set of data in the GDS file associated with the previously formed interconnect layer or layers onto which the second interconnect layer 230 are to be attached. In some embodiments, the density can be equal to a silicon Si interposer or silicon bridge level approach due to a similar rigid DILS substrate flatness. According to one or more embodiments, the interconnect substrate and layers can be extended to further layers using further DILI (e.g., including a direct interconnect substrate and RDL), each of which can include active or passive components, RDL, and so on.
While the foregoing is directed to embodiments of the present disclosure, other and further embodiments of the disclosure may be devised without departing from the basic scope thereof. The present disclosure also contemplates that one or more aspects of the embodiments described herein may be substituted in for one or more of the other aspects described. The scope of the disclosure is determined by the claims that follow.
This application claims the benefit of U.S. Provisional Application Ser. No. 63/504,403, filed on May 25, 2023, and the benefit of U.S. Provisional Application Ser. No. 63/466,691, filed on May 15, 2023, which are both herein incorporated by reference.
| Number | Date | Country | |
|---|---|---|---|
| 63504403 | May 2023 | US | |
| 63466691 | May 2023 | US |
