Patent Application
20140306290
The present invention relates to dual silicidation techniques and more particularly, to dual silicidation techniques using a combination of self-aligned silicide and trench silicide (and potentially selective masking) in order to reduce overall contact resistance, and which are compatible with a gate-last fabrication process.
Silicide/silicon contact resistance becomes increasingly more dominating in the external resistance of an extremely scaled device. With technologically feasible source and drain epitaxial conditions, along with silicide metallurgy, overall contact resistance is limited by the specific contact resistivity and contact area.
Conventional gate-last fabrication process flows often employ a trench-silicidation scheme for forming source and drain contacts. There are however several notable drawbacks associated with this approach. First, a trench-silicidation scheme is a non-self-aligned contact process. Namely, gate-to-trench overlay requirements along with any misalignment of the trenches with the source and drain regions results in a smaller contact area. A smaller contact area can lead to greater contact resistance. Second, the etch (e.g., reactive ion etching (RIE)) used to form the trenches can also lead to gouging of the underlying source and drain regions. Gouging can lead to material loss that can lead to higher contact resistance as well as strain relaxation that hurts channel mobility.
Therefore, self-aligned silicidation schemes that are compatible with a gate-last fabrication process flow and which mitigate the aforementioned problems would be desirable.
The present invention provides dual silicidation techniques using a combination of self-aligned silicide and trench silicide (and potentially selective masking) in order to reduce overall contact resistance, which are compatible with a gate-last fabrication process. In one aspect of the invention, a method for fabricating an electronic device is provided. The method includes the following steps. A wafer is provided having at least one first active area and at least one second active area defined therein. One or more p-channel field effect transistor (p-FET) devices are formed in the first active area and one or more n-channel field effect transistor (n-FET) devices are formed in the second active area, wherein each of the p-FET devices includes a p-FET gate stack over the first active area and p-FET source and drain regions on opposite sides of the p-FET gate stack, and wherein each of the n-FET devices includes an n-FET gate stack over the second active area and n-FET source and drain regions on opposite sides of the n-FET gate stack. A first metal is deposited onto the wafer. The wafer is annealed to form a self-aligned silicide in each of the p-FET source and drain regions and in each of the n-FET source and drain regions from the first metal, wherein the self-aligned silicide has a melting point that is greater than about 1,000° C., and wherein the annealing is performed under conditions sufficient to form the self-aligned silicide in each of the p-FET source and drain regions having a thickness T1 and to form the self-aligned silicide in each of the n-FET source and drain regions having a thickness T2, wherein T1 is less than T2. A filler layer is deposited onto the wafer surrounding the p-FET gate stack and the n-FET gate stack. Trench contact openings are formed in the filler layer over each of the p-FET source and drain regions and over each of the n-FET source and drain regions. A second metal is deposited onto the wafer and lining the trench contact openings. The wafer is annealed to form a trench silicide in each of the p-FET source and drain regions from the second silicide metal, wherein the annealing is performed under conditions sufficient to i) diffuse the second metal through the self-aligned silicide in each of the p-FET source and drain regions to form the trench silicide, and to ii) prevent diffusion of the second metal through the self-aligned silicide in each of the n-FET source and drain regions based on the self-aligned silicide in each of the p-FET source and drain regions being thinner than the self-aligned silicide in each of the n-FET source and drain regions.
A gate-last fabrication process flow may be implemented wherein the p-FET gate stack and the n-FET gate stack are dummy gates. The method may further include the following steps. The p-FET gate stack and the n-FET gate stack may be removed forming trenches in the filler layer. Replacement gate stacks can be formed in the trenches after the self-aligned silicide has been formed and prior to forming the trench contact openings in the filler layer.
In another aspect of the invention, another method for fabricating an electronic device is provided. The method includes the following steps. A wafer is provided having at least one first active area and at least one second active area defined therein. One or more p-FET devices are formed in the first active area and one or more n-FET devices are formed in the second active area, wherein each of the p-FET devices includes a p-FET gate stack over the first active area and p-FET source and drain regions on opposite sides of the p-FET gate stack, and wherein each of the n-FET devices includes an n-FET gate stack over the second active area and n-FET source and drain regions on opposite sides of the n-FET gate stack. The p-FET devices are masked. A first metal is deposited onto the wafer. The wafer is annealed to form a self-aligned silicide in each of the n-FET source and drain regions from the first metal, wherein the masking prevents silicide formation in the p-FET devices and wherein the self-aligned silicide has a melting point that is greater than about 1,000° C. A filler layer is deposited onto the wafer surrounding the p-FET gate stack and the n-FET gate stack. Trench contact openings are formed in the filler layer over each of the p-FET source and drain regions and over each of the n-FET source and drain regions. A second metal is deposited onto the wafer and lining the trench contact openings. The wafer is annealed to form a trench silicide in each of the p-FET source and drain regions from the second metal, wherein silicide formation is prevented in the n-FET devices due to the self-aligned silicide in the n-FET source and drain regions.
In yet another aspect of the invention, yet another method for fabricating an electronic device is provided. The method includes the following steps. A wafer is provided having at least one first active area and at least one second active area defined therein. One or more p-FET devices are formed in the first active area and one or more n-FET devices are formed in the second active area, wherein each of the p-FETs includes a p-FET gate stack over the first active area and p-FET source and drain regions on opposite sides of the p-FET gate stack, and wherein each of the n-FETs includes an n-FET gate stack over the second active area and n-FET source and drain regions on opposite sides of the n-FET gate stack. The p-FET devices are masked. A first metal is deposited onto the wafer. The wafer is annealed to form a self-aligned silicide in each of the n-FET source and drain regions from the first metal, wherein the masking prevents silicide formation in the p-FET devices and wherein the self-aligned silicide has a melting point that is greater than about 1,000° C. A filler layer is deposited onto the wafer surrounding the p-FET gate stack and the n-FET gate stack. First trench contact openings are formed in the filler layer over each of the p-FET source and drain regions. A second metal is deposited onto the wafer and lining the trench contact openings. The wafer is annealed to form a trench silicide in each of the p-FET source and drain regions from the second metal. Second trench contact openings are formed in the filler layer over each of the n-FET source and drain regions.
In still yet another aspect of the invention, an electronic device is provided. The electronic device includes a wafer having at least one first active area and at least one second active area defined therein; one or more p-FET devices formed in the first active area and one or more n-FET devices formed in the second active area, wherein each of the p-FET devices includes a p-FET gate stack over the first active area and p-FET source and drain regions on opposite sides of the p-FET gate stack, and wherein each of the n-FET devices includes an n-FET gate stack over the second active area and n-FET source and drain regions on opposite sides of the n-FET gate stack; a self-aligned silicide formed in each of the p-FET source and drain regions and in each of the n-FET source and drain regions, wherein the self-aligned silicide includes a first metal and has a melting point that is greater than about 1,000° C., and wherein the self-aligned silicide in each of the p-FET source and drain regions has a thickness T1 and the self-aligned silicide in each of the n-FET source and drain regions has a thickness T2, wherein T1 is less than T2; a filler layer on the wafer surrounding the p-FET gate stack and the n-FET gate stack; trench contact openings in the filler layer over each of the p-FET source and drain regions and over each of the n-FET source and drain regions; and a trench silicide formed in the trench contact openings in each of the p-FET source and drain regions, wherein the trench silicide comprises a second metal.
In yet a further aspect of the invention, another electronic device is provided. The electronic device includes a wafer having at least one first active area and at least one second active area defined therein; one or more p-FET devices formed in the first active area and one or more n-FET devices formed in the second active area, wherein each of the p-FET devices includes a p-FET gate stack over the first active area and p-FET source and drain regions on opposite sides of the p-FET gate stack, and wherein each of the n-FET devices includes an n-FET gate stack over the second active area and n-FET source and drain regions on opposite sides of the n-FET gate stack; a self-aligned silicide formed in each of the n-FET source and drain regions, wherein the self-aligned silicide comprises a first metal and has a melting point that is greater than about 1,000° C.; a filler layer on the wafer surrounding the p-FET gate stack and the n-FET gate stack; trench contact openings in the filler layer over each of the p-FET source and drain regions and over each of the n-FET source and drain regions; and a trench silicide formed in the trench contact openings in each of the p-FET source and drain regions, wherein the trench silicide comprises a second metal.
A more complete understanding of the present invention, as well as further features and advantages of the present invention, will be obtained by reference to the following detailed description and drawings.
As provided above, silicidation process flows incorporating conventional trench-silicidation schemes can have notable drawbacks related to contact resistivity, e.g., reduced contact area due to the non-self-aligned process and potential gouging of the underlying source and drain regions during the trench etch. Advantageously, provided herein are silicidation techniques which avoid these problems by employing a self-aligned, high-temperature-stable silicide in combination with a (subsequent) trench silicide. The self-aligned silicide serves to reduce contact resistance and to protect the source and drain regions during the trench etch. Further, since the self-aligned silicide is high-temperature-stable, the present process can be employed (if so desired) in the context of a self-aligned silicide first, gate-last process flow which can maximize the contact area for a fixed gate pitch.
The implementation of a dual silicide scheme in a silicide first, gate-last process flow is described, for example, in U.S. patent application Ser. No. 13/755,427, filed by Baraskar et al. on Jan. 31, 2013, entitled “Dual Silicide Process,” the entire contents of which are incorporated by reference herein. In general, however, a silicide first, gate-last approach involves forming a dummy gate, performing the silicidation and then replacing the dummy gate with a replacement gate. Forming the replacement gate generally involves a high temperature anneal (e.g., to set the workfunction and/or to improve the reliability of the gate by reducing bias-temperature-instability (BTI) effects). The silicide formed by conventional processes would be degraded during this anneal. By contrast, a high-temperature-stable silicide is employed in the present techniques and thus does not have the same temperature constraints. It is notable however that, as will be described in detail below, the use of a dummy gate/replacement gate scheme is merely one example, and that the present techniques are more generally applicable to any dual silicide process.
Several different exemplary embodiments for forming an electronic device having at least one p-FET and at least one n-FET that includes a dual silicidation scheme are now provided. As highlighted above, the present dual silicidation process involves forming self-aligned, high-temperature-stable silicide contacts on both nFET and pFET devices. The high-temperature stability of the self-aligned silicide permits use of a silicide-first, gate-last approach (if so desired) in which the self-aligned silicide is formed before the replacement gate—followed by formation of a trench silicide after the replacement gate is in place. By way of the present techniques, the self-aligned silicide serves to compensate for the comparatively higher specific contact resistivity (Rho_c) values in the nFET device(s) (as compared to the pFET devices), and a more controlled etch stop in both the nFETs and pFET devices (thus protecting the source and drain regions from gouging).
Subsequently (e.g., after the replacement gate has been formed—if a gate-last approach is followed) a trench silicide is formed on both nFETs and pFETs. This trench silicide can involve conventional silicide metals since the high-temperature process (e.g., such as those associated with the replacement gate formation) have already been performed. The use of a self-aligned silicide in combination with a subsequent trench silicide leads to acceptable contact resistance values in the pFET device(s) which is facilitated by small Rho_c values. As provided above, overall contact resistance is limited by the specific contact resistivity and contact area. Thus, even if misalignment of the trench silicide occurs (which affects contact area), the overall contact resistance with the present devices is lower than conventional products due to the larger contact area attained by use of the self-aligned silicide.
A first exemplary embodiment employing the present techniques will now be described in conjunction with the description of
By way of example only, the starting wafer can be a semiconductor-on-insulator (SOI) wafer or a bulk semiconductor wafer. A SOI wafer includes a SOI layer (e.g., silicon (Si), germanium (Ge), silicon-germanium (SiGe), etc. separated from a substrate by a buried oxide or BOX. See
Suitable bulk semiconductor wafers include, but are not limited to, bulk Si, Ge, or SiGe wafers. STI can also be used to define active areas in a bulk wafer.
As shown in
The gate stacks may be formed by forming/depositing the gate stack materials (e.g., the gate dielectric, the gate electrode material, etc.) on the wafer and then patterning the materials into the individual gate stacks. A hardmask is used during the patterning. See, for example,
In general, each FET device includes a source region and a drain region interconnected by a channel. The gate stack is located over the channel and regulates electron flow through the channel. The source and drain regions of the device can be formed (on opposite sides of the gate stacks) in-situ or ex-situ (e.g., by way of an ion implantation process) followed by an activation anneal of the dopants. With an in-situ process, dopants can be introduced during the growth of an epitaxial material in the source and drain regions of the device. According to an exemplary embodiment, the source and drain regions 110 of the p-FET device(s) are formed from in-situ boron doped (ISBD) silicon germanium (SiGe). Namely, boron is introduced during growth of a SiGe epitaxial material in the source and drain regions of the p-FET device(s). According to an exemplary embodiment, the source and drain regions 112 of the n-FET device(s) are formed from in-situ phosphorous doped silicon carbon (SiC:P). Namely, phosphorous is introduced during growth of a silicon carbon epitaxial material in the source and drain regions of the n-FET device(s).
The source and drain doping may be carried out by first masking the p-FET device(s) (or alternatively the n-FET device(s)) and forming the source and drain regions in the n-FET device(s) (or alternatively the p-FET device(s)). The mask is then removed and the process is repeated for the opposite polarity device, again using selective masking. The mask used during this process can be a hardmask formed from a suitable hardmask material, such as silicon nitride that is deposited onto the wafer and then patterned into the selective hardmask using standard lithography and etching techniques. While these hardmasks are not shown in
It is notable that while the instant embodiments are directed to planar devices, the present techniques are applicable, in the same manner described, to non-planar devices, such as FINFET and nanowire FET devices. FINFET devices generally include a source region and a drain region connected by one or more fin-shaped channels. See, for example, U.S. Patent Application Publication Number 2010/0264497 filed by Chang et al., entitled “Multiple Vt Field-Effect Transistor Devices,” the entire contents of which are incorporated by reference herein. A gate covers a portion of the fins that serve as a channel region of the device. Portions of the fins extending out form the gate serve as the source and drain regions of the device. The above-described source and drain epitaxy may, in the context of a FINFET process flow, fully merge, partially merge, or not merge the fins. Nanowire FET devices generally include one or more nanowire channels that interconnect a source and a drain region. A gate covers at least a portion of each of the nanowire channels. When the gate completely surrounds a portion of each of the nanowire channels, this configuration is called a gate-all-around (GAA) structure. See, for example, U.S. Patent Application Publication Number 2012/0007051 filed by Bangsaruntip et al., entitled “Process for Forming a Surrounding Gate for a Nanowire Using a Sacrificial Patternable Dielectric,” the contents of which are incorporated by reference herein.
As described above, due to the use of high-temperature-stable silicide contacts, the present dual silicide process may uniquely be implemented in a gate-last fabrication process flow. In a gate-last process, a dummy gate is formed early on in the process which acts as a placeholder for a replacement gate that, once the dummy gate is removed, will replace the dummy gate. In the case where the present techniques are being implemented in accordance with a gate-last process flow, the gate stacks (i.e., gate stacks 102a, 102b, etc.) shown in
As shown in
As shown in
In a two-step anneal, an anneal at a lower temperature (e.g., from about 400° C. to about 800° C.) is performed for a duration of from about 1 second to about 60 seconds, followed by an etch to remove unreacted metal. A second annealing may then be performed at a higher temperature (e.g., from about 600° C. to about 1,000° C.) for a duration of from about 1 second to about 60 seconds, to obtain the desired phase of the silicide material. It is also possible to perform the second step at a higher temperature (e.g., from about 800° C. to about 1,200° C.) for a shorter duration (e.g., from about 0.1 msec to about 5 msec).
According to an exemplary embodiment, it is preferable to attain differential silicide thickness on the p-FET device(s) versus the n-FET device(s). Specifically, the materials (silicide metal(s), deposited thickness, etc.) and/or the silicidation conditions (anneal temperature and/or duration) are chosen such that there is a greater amount (quantified, e.g., based on thickness) of the high-temperature-stable, self-aligned silicide formed in the source and drain regions of the n-FET device(s) as compared to the source and drain regions of the p-FET devices, i.e., a lesser amount of the high-temperature-stable, self-aligned silicide is formed in the source and drain regions of the p-FET devices as compared to the source and drain regions of the n-FET devices. By way of example only, as provided above, the source and drain regions 110 of the p-FET devices may include ISBD SiGe, whereas the source and drain regions 112 of the n-FET devices may include in-situ doped SiC:P. The high-temperature stable silicide metal may be Ti. Using the above-provided metal thickness and annealing parameters, a lesser amount of the high-temperature-stable, self-aligned silicide will be formed in the source and drain regions of the p-FET devices as compared to the source and drain regions of the n-FET devices, since Ti silicide growth on ISBD SiGe pFET source/drain regions is limited compared to that on nFET source/drain regions. Ta when used as the high-temperature stable silicide metal 202 will behave the same as Ti. Using the above conditions, Co will exhibit differential silicide growth since cobalt-silicide does not grow well on SiGe, and thus will be thinner. It is notable that while the source/drain regions of the devices may include materials such as Si, SiGe, and SiC (see above) in order to adhere to conventional terminology the resulting product is referred to generically herein as a “silicide” which is meant to encompass Si-based silicides, SiGe-based germanosilicides, and silicon carbon-based silicides.
The differential silicide thickness will be employed later in the process to permit the subsequent trench silicide to diffuse through the self-aligned silicide in the p-FET device(s), but not so in the n-FET device(s), see below. Thus, according to this exemplary embodiment, the high-temperature-stable, self-aligned silicide 302a formed in the source and drain regions of the p-FET device(s) has a thickness T1 and the self-aligned silicide 302b formed in the source and drain regions of the n-FET device(s) has a thickness T2, wherein T1<T2. According to an exemplary embodiment, T1 (i.e., the thickness of the high-temperature-stable, self-aligned silicide 302a formed in the source and drain regions of the p-FET device(s)) is from about 0.5 nanometers (nm) to about 5 nm, and T2 (i.e., the thickness of the self-aligned silicide 302b formed in the source and drain regions of the n-FET device(s)) is from about 2 nm to about 30 nm.
As highlighted above, the present techniques may advantageously be integrated with a gate-last process flow, and in that case (as detailed above) the gate stacks (i.e., gate stacks 102a, 102b, etc.) present up to this point in the process are called “dummy gates”—e.g., poly-silicon gates that serve as a placeholder and are meant to be removed and replaced with a “replacement” gate. According to an exemplary gate-last approach, in order to permit effective removal and replacement of the dummy gates, a filler layer 402 is deposited onto the wafer and planarized, using for example, chemical-mechanical polishing (CMP). See
Next, as shown in
As shown in
With a high-k dielectric, such as hafnium oxide, it may be desirable to perform a high-temperature anneal (e.g., at a temperature of from about 900° C. to about 1,200° C.) following deposition of the gate dielectric in order to set the workfunction and/or to improve the reliability of the gate (see above). As provided above, the self-aligned silicide is resistant to high temperatures (due to the use of high-temperature stable silicide metal(s)) and thus is not damaged during this process. This is not so with conventional techniques. Specifically, conventional silicides will agglomerate during this high temperature anneal, damaging the contact. Accordingly, the silicide contacts are typically not formed until late in the process and thus involve multiple masking levels—which add complexity and cost to the manufacturing process along with the drawbacks of the trench-silicide scheme mentioned above.
Following deposition of the gate dielectric, one or more conformal gate metal layers are then deposited into the trenches 502 using, for example, evaporation, sputtering, or atomic layer deposition (ALD). The conformal gate metal layer(s) are represented schematically in the figures as a single conformal layer 606a, 606b, etc. with the understanding that the layer may in fact be composed of multiple conformal metal layers. According to an exemplary embodiment, each of the conformal gate metal layers 606a, 606b, etc. serves as a gate workfunction setting material and as a liner (for the subsequently deposited fill metal—see below). Suitable workfunction setting/liner metals include, but are not limited to lanthanum (La), aluminum (Al), tantalum nitride (TaN), and titanium nitride (TiN). Following deposition of the workfunction setting/liner metal(s), the trenches 502 are then filled with a fill metal (i.e., fill metal 608a, 608b, etc.) using, for example, evaporation, sputtering, or ALD. Suitable fill metals include, but are not limited to, Al and/or tungsten (W). As shown in
It is notable that the use of a gate last approach is only one possible exemplary implementation of the present techniques. The depiction of a gate last process is provided merely to illustrate its compatibility with the present techniques. The present techniques could however be implemented in the same manner as described above in a gate first (or any other) device fabrication scenario. For instance, in a gate-first scenario, the gate stacks 102a and 102b would constitute the final gates of the device, and beginning with the structure shown illustrated in
Namely, whether a gate-first or a gate-last approach has been taken, as shown in
The trench silicide contacts to the source and drain regions of the n-FET and p-FET devices are now formed through the filler layer. To begin the trench silicide process, a patterned hardmask 702 is first formed on the filler layer 402 above the gate stacks. By way of example only, the patterned hardmask 702 may be formed from a nitride material, such as silicon nitride. The hardmask may be patterned using conventional lithography and etching techniques.
Next, as shown in
As described above, the self-aligned silicide 302a in the p-FET device(s) source and drain regions is thinner than the self-aligned silicide 302b in the n-FET device(s) source and drain regions. This configuration is employed to now selectively form a trench silicide 802 in the p-FET device(s) (and not in the n-FET device(s)). Specifically, the conditions chosen for forming the trench silicide are such that the trench silicide metal 706 diffuses through the pre-formed (thinner) self-aligned silicide 302a in the p-FET device(s), but not through the (thicker) self-aligned silicide 302b in the n-FET device(s)—i.e., the thickness of the self-aligned silicide 302b in the n-FET device(s) prevents diffusion of the trench silicide metal therethrough. The trench silicide metal 706 that diffuses through the (thinner) self-aligned silicide 302a in the p-FET device(s) will then react with the underlying source/drain material (e.g., ISBD SiGe—see above) to form the trench silicide 802. Accordingly, in this example, the trench silicide 802 will form only in the source and drain regions of the p-FET device(s). See
Exemplary thickness values of the (thinner) self-aligned silicide 302a and the (thicker) self-aligned silicide 302b were provided in conjunction with the description of
As described above, the silicide process involves using an anneal to form the silicide and then removing the unreacted metal, for example, using a wet etch. The anneal can be performed in a one-step or multi-step process. For example, with a one-step anneal, the silicide-forming anneal can be performed at a temperature of from about 400° C. to about 700° C. for a duration of from about 1 second to about 60 seconds, followed by a wet etch to remove the unreacted metal. In a two-step anneal, an anneal at a lower temperature (e.g., from about 280° C. to about 500° C. for a duration of from about 1 second to about 60 seconds) is performed, followed by an etch to remove unreacted metal. A second annealing may then be performed at a higher temperature (e.g., from about 500° C. to about 700° C. for a duration of from about 1 second to about 60 seconds) to obtain the desired phase of the silicide material. It is also possible to perform the second anneal at a higher temperature (e.g., from about 700° C. to about 1,000° C.) for a shorter duration (e.g., from about 0.1 msec to about 5 msec) by using, for example, laser or flash annealing methods.
Thus, according to this example, the only reacted trench metal will be that forming trench silicide 802 in the p-FET device(s). All of the trench silicide metal 706 deposited in the n-FET device(s) will be unreacted and thus removed following the anneal.
It is notable that diffusion of the trench silicide metal through the self-aligned silicide 302b (in the n-FET device(s)) can be slowed due to the presence of carbon in n-FET SiC source and drain regions that is beneficial for the present embodiment. Further, the diffusion of, for example, NiPt through the self-aligned silicide 302a in p-FET device(s) source and drain regions will form NiPt silicide underneath (i.e., the trench silicide 802 will be NiPt silicide). The same is true for the other exemplary trench silicide metals given above. Additionally, the etch (e.g., RIE) used to pattern the trench contact openings 704 in the filler layer 402 (see above) will remove some of the self-aligned silicide in both the n-FET and p-FET devices. By further thinning the self-aligned silicide 302a diffusion of the trench silicide metal 706 through the self-aligned silicide in the p-FET device(s) is insured. Namely, it is notable that the trench RIE may be configured to etch the self-aligned silicide in the p-FET device(s) at a faster rate than the self-aligned silicide in the n-FET device(s) based on the presence of Ge in the p-FET source and drain regions (see, for example, the description of
Next, as shown in
A second exemplary embodiment employing the present techniques will now be described in conjunction with the description of
This exemplary embodiment will now be described in detail. The starting structure for this second exemplary embodiment is the same as that shown in
In this example, a self-aligned, preferably high-temperature-stable silicide is selectively formed only in the source and drain regions of the n-FET device(s). This is achieved, for example, by forming a hardmask 1002 over, covering and thus masking the p-FET device(s) on the wafer. See
As described in conjunction with the description of
The above-described self-aligned silicidation process is then carried out, this time only in the source and drain regions 112 of the n-FET device(s) (since the p-FET devices are masked by hardmask 1002). Namely, as shown in
As shown in
According to an exemplary embodiment, the self-aligned silicide 1202 is formed having a thickness T3 of from about 2 nm to about 30 nm. Since there is no self-aligned silicide being formed in the p-FET device(s), the self-aligned silicide 1202 has to be sufficiently thick (e.g., having a thickness T3 in the above-provided range) so to permit a trench silicide to be formed in the p-FET devices without the deposited trench silicide metal diffusing through the self-aligned silicide 1202 in the n-FET device(s)—see below.
The process then proceeds in the same manner as the first embodiment presented above, except that there is no self-aligned silicide present in the p-FET source and drain regions 110. The remainder of the process is now described.
As highlighted above, the present techniques may advantageously be integrated with a gate-last process flow, and in that case the gate stacks present up to this point in the process are called “dummy gates”—e.g., poly-silicon gates that serve as a placeholder and are meant to be removed and replaced with a “replacement” gate. The process for removing the dummy gates and replacing the dummy gates with a replacement gate stack (including depositing a filler layer) were described, in detail, in conjunction with the description of
As highlighted above, since the previously formed self-aligned silicide 1202 is high-temperature-stable (due to the use of the high-temperature stable silicide metal 1102), the self-aligned silicide can withstand the high temperatures involved in the replacement gate-formation process. Thus, advantageously, the self-aligned silicide 1202 can be formed prior to the replacement gate process, avoiding multiple/complex masking levels commonly associated with conventional dual silicide fabrication flows.
As noted above, the use of a gate last approach is only one possible exemplary implementation of the present techniques. The depiction of a gate last process is provided merely to illustrate its compatibility with the present techniques. The present techniques could however be implemented in the same manner as described above in a gate first (or any other) device fabrication scenario. For instance, in a gate-first scenario, the gate stacks 102a and 102b would constitute the final gates of the device, and beginning with the structure shown illustrated in
Next, as shown in
A trench silicide metal 1314 (e.g., Ni, NiPt, and/or Pt) is then conformally deposited onto the wafer, and into/lining the trench contact openings 1312. Thus the same trench contact metal 1314 is being used for both the p-FET and n-FET devices. By way of example only, the trench silicide metal 1314 is deposited to a thickness of from about 2 nm to about 25 nm.
Since there is no pre-formed silicide present in the p-FET device(s), the following silicidation will serve to form a trench silicide 1402 only in the source and drain regions 110 of the p-FET device(s), i.e., the pre-formed self-aligned silicide 1202 in the source and drain regions 112 of the n-FET device(s) will block/prevent any trench silicide from forming in the n-FET device. See
The conditions chosen for forming the trench silicide are such that the trench silicide metal 1314 forms trench silicide 1402 in the source and drain regions 110 of the p-FET device(s) but does not diffuse through the pre-formed self-aligned silicide 1202 in the n-FET device(s). The trench silicide metal 1314 will react with the underlying source/drain material (e.g., ISBD SiGe—see above) to form the trench silicide 1402. Accordingly, in this example, the trench silicide 1402 will form only in the source and drain regions of the p-FET device(s). See
It is assumed here that the same trench silicide metal is deposited, as described above, to a uniform thickness of from about 2 nm to about 25 nm in both the n-FET and p-FET devices. Conditions that may be employed in order to form the trench silicide 1402 without having the trench silicide metal 1314 diffuse through the pre-formed self-aligned silicide 1202 (e.g., having a thickness T3 in the above-provided range) in the source and drain regions 112 of the n-FET device(s) are now provided.
As described above, the silicide process involves using an anneal to form the silicide and then removing the unreacted metal, for example, using a wet etch. The anneal can be performed in a one-step or multi-step process. For example, with a one-step anneal, the silicide-forming anneal can be performed at a temperature of from about 400° C. to about 700° C. for a duration of from about 1 second to about 60 seconds, followed by a wet etch to remove the unreacted metal. In a two-step anneal, an anneal at a lower temperature (e.g., from about 280° C. to about 500° C. for a duration of from about 1 second to about 60 seconds) is performed, followed by an etch to remove unreacted metal. A second annealing may then be performed at a higher temperature (e.g., from about 500° C. to about 700° C. for a duration of from about 1 second to about 60 seconds) to obtain the desired phase of the silicide material. It is also possible to perform the second anneal at a higher temperature (e.g., from about 700° C. to about 1,000° C.) for a shorter duration (e.g., from about 0.1 msec to about 5 msec) by using, for example, laser or flash annealing methods.
It is notable that, as described above, diffusion of the trench silicide metal through the self-aligned silicide 1202 (in the n-FET device(s)) can be slowed due to the presence of carbon in n-FET SiC source and drain regions. Further, diffusion of the trench silicide metal through the self-aligned silicide 1202 (in the n-FET device(s)) can be slowed due to the low-temperature RTA used in the trench silicidation process.
According to this example, the only reacted trench metal will be that forming trench silicide 1402 in the p-FET device(s). All of the trench silicide metal 1314 deposited in the n-FET device(s) will be unreacted and thus removed following the anneal.
Next, as shown in
A third exemplary embodiment employing the present techniques will now be described in conjunction with the description of
This example begins with the structure shown in
As highlighted above, the present techniques may advantageously be integrated with a gate-last process flow, and in that case the gate stacks present up to this point in the process are called “dummy gates”—e.g., poly-silicon gates that serve as a placeholder and are meant to be removed and replaced with a “replacement” gate. The process for removing the dummy gates and replacing the dummy gates with a replacement gate stack (including depositing a filler layer) were described, in detail, in conjunction with the description of
As highlighted above, since the previously formed self-aligned silicide 1202 is high-temperature-stable (due to the use of the high-temperature stable silicide metal 1102), the self-aligned silicide 1202 can withstand the high temperatures involved in the replacement gate-formation process. Thus, advantageously, the self-aligned silicide 1202 can be formed prior to the replacement gate process, avoiding multiple/complex masking levels commonly associated with conventional dual silicide fabrication flows.
As noted above, the use of a gate last approach is only one possible exemplary implementation of the present techniques. The depiction of a gate last process is provided merely to illustrate its compatibility with the present techniques. The present techniques could however be implemented in the same manner as described above in a gate first (or any other) device fabrication scenario. For instance, in a gate-first scenario, the gate stacks 102a and 102b would constitute the final gates of the device, and beginning with the structure shown illustrated in
In this example, trench contacts will be formed in the p-FET and n-FET devices separately (i.e., in separate steps) through the filler layer. Namely, as shown in
In the same manner as described above, a trench silicide metal 1614 (e.g., Ni, NiPt, and/or Pt) is then conformally deposited onto the wafer, and into/lining the trench contact openings 1612. By way of example only, the trench silicide metal 1614 is deposited to a thickness of from about 2 nm to about 25 nm.
Since the n-FET device(s) are blocked by the patterned hardmask 1610, the following silicidation will serve to form a trench silicide 1702 only in the source and drain regions 110 of the p-FET device(s). See
As described above, the silicide process involves using an anneal to form the silicide and then removing the unreacted metal, for example, using a wet etch. The anneal can be performed in a one-step or multi-step process. For example, with a one-step anneal, the silicide-forming anneal can be performed at a temperature of from about 400° C. to about 700° C. for a duration of from about 1 second to about 60 seconds, followed by a wet etch to remove the unreacted metal. In a two-step anneal, an anneal at a lower temperature (e.g., from about 280° C. to about 500° C. for a duration of from about 1 second to about 60 seconds) is performed, followed by an etch to remove unreacted metal. A second annealing may then be performed at a higher temperature (e.g., from about 500° C. to about 700° C. for a duration of from about 1 second to about 60 seconds) to obtain the desired phase of the silicide material. It is also possible to perform the second anneal at a higher temperature (e.g., from about 700° C. to about 1,000° C.) for a shorter duration (e.g., from about 0.1 msec to about 5 msec) by using, for example, laser or flash annealing methods.
Next, in order to form contact to the n-FET device(s) trench contact openings (i.e., trench contact openings 1804) have to be formed in the filler layer over the source and drain regions 112 of the n-FET devices. In order to protect the trench contact openings 1612 (over the p-FET device(s)) and the trench silicide 1702, a dielectric material 1802 is first deposited onto the wafer, filling the contact openings 1612 over the p-FET device(s). See
Other suitable organic materials for use as the dielectric material 1802 include but are not limited to those materials described in U.S. Pat. No. 7,037,994 issued to Sugita et al. entitled “Acenaphthylene Derivative, Polymer, and Antireflection Film-Forming Composition,” U.S. Pat. No. 7,244,549 issued to Iwasawa et al. entitled “Pattern Forming Method and Bilayer Film,” U.S. Pat. No. 7,303,855 issued to Hatakeyama et al. entitled “Photoresist Undercoat-Forming Material and Patterning Process” and U.S. Pat. No. 7,358,025 issued to Hatakeyama entitled “Photoresist Undercoat-Forming Material and Patterning Process.” The contents of each of the foregoing patents are incorporated by reference herein. A post-apply bake is then performed to cross-link the organic dielectric material 1802 and bake off the solvent. According to an exemplary embodiment, the post-apply bake is conducted at a temperature of up to about 250° C., e.g., from about 200° C. to about 250° C.
Next, as shown in
As shown in
Although illustrative embodiments of the present invention have been described herein, it is to be understood that the invention is not limited to those precise embodiments, and that various other changes and modifications may be made by one skilled in the art without departing from the scope of the invention.
